SG11201803730TA - Systems and methods for implementing coherent memory in a multiprocessor system - Google Patents
Systems and methods for implementing coherent memory in a multiprocessor systemInfo
- Publication number
- SG11201803730TA SG11201803730TA SG11201803730TA SG11201803730TA SG11201803730TA SG 11201803730T A SG11201803730T A SG 11201803730TA SG 11201803730T A SG11201803730T A SG 11201803730TA SG 11201803730T A SG11201803730T A SG 11201803730TA SG 11201803730T A SG11201803730T A SG 11201803730TA
- Authority
- SG
- Singapore
- Prior art keywords
- location
- cache
- node
- international
- go6f
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/082—Associative directories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/0822—Copy directories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/0824—Distributed directories, e.g. linked lists of caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
- G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1048—Scalability
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562250653P | 2015-11-04 | 2015-11-04 | |
US201562258692P | 2015-11-23 | 2015-11-23 | |
PCT/IB2016/056655 WO2017077502A1 (en) | 2015-11-04 | 2016-11-04 | Systems and methods for implementing coherent memory in a multiprocessor system |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201803730TA true SG11201803730TA (en) | 2018-06-28 |
Family
ID=57286762
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201803730TA SG11201803730TA (en) | 2015-11-04 | 2016-11-04 | Systems and methods for implementing coherent memory in a multiprocessor system |
Country Status (6)
Country | Link |
---|---|
US (3) | US10754777B2 (ko) |
EP (1) | EP3371707B1 (ko) |
KR (1) | KR20180078253A (ko) |
CN (1) | CN108475234B (ko) |
SG (1) | SG11201803730TA (ko) |
WO (1) | WO2017077502A1 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2560336B (en) * | 2017-03-07 | 2020-05-06 | Imagination Tech Ltd | Address generators for verifying integrated circuit hardware designs for cache memory |
KR102157354B1 (ko) | 2017-11-20 | 2020-09-17 | 삼성전자 주식회사 | 효율적으로 압축된 캐시 라인의 저장 및 처리를 위한 시스템 및 방법 |
KR102151180B1 (ko) * | 2017-11-20 | 2020-09-02 | 삼성전자주식회사 | 효율적인 가상 캐시 구현을 위한 시스템 및 방법 |
TWI795470B (zh) * | 2017-11-20 | 2023-03-11 | 南韓商三星電子股份有限公司 | 資料管理方法、多處理器系統和非暫態計算機可讀儲存媒體 |
KR102079868B1 (ko) * | 2018-07-26 | 2020-02-20 | 고려대학교 산학협력단 | 멀티코어 기반의 단말 장치에 적용되는 잠금 패턴의 보안 강도를 측정하는 장치 및 방법 |
US11714753B2 (en) | 2018-12-13 | 2023-08-01 | Telefonaktiebolaget Lm Ericsson (Publ) | Methods and nodes for handling memory |
US11106609B2 (en) | 2019-02-28 | 2021-08-31 | Micron Technology, Inc. | Priority scheduling in queues to access cache data in a memory sub-system |
US11288199B2 (en) | 2019-02-28 | 2022-03-29 | Micron Technology, Inc. | Separate read-only cache and write-read cache in a memory sub-system |
US10970222B2 (en) | 2019-02-28 | 2021-04-06 | Micron Technology, Inc. | Eviction of a cache line based on a modification of a sector of the cache line |
US10908821B2 (en) | 2019-02-28 | 2021-02-02 | Micron Technology, Inc. | Use of outstanding command queues for separate read-only cache and write-read cache in a memory sub-system |
US11782835B2 (en) * | 2020-11-30 | 2023-10-10 | Electronics And Telecommunications Research Institute | Host apparatus, heterogeneous system architecture device, and heterogeneous system based on unified virtual memory |
US20230325316A1 (en) * | 2022-04-11 | 2023-10-12 | Arteris, Inc. | System and method to enter and exit a cache coherent interconnect |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5265232A (en) * | 1991-04-03 | 1993-11-23 | International Business Machines Corporation | Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data |
US6560681B1 (en) * | 1998-05-08 | 2003-05-06 | Fujitsu Limited | Split sparse directory for a distributed shared memory multiprocessor system |
US6108764A (en) | 1998-12-17 | 2000-08-22 | International Business Machines Corporation | Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention |
US6266743B1 (en) | 1999-02-26 | 2001-07-24 | International Business Machines Corporation | Method and system for providing an eviction protocol within a non-uniform memory access system |
US7398304B2 (en) | 2003-06-23 | 2008-07-08 | Microsoft Corporation | General dependency model for invalidating cache entries |
US20060143384A1 (en) * | 2004-12-27 | 2006-06-29 | Hughes Christopher J | System and method for non-uniform cache in a multi-core processor |
US7454576B2 (en) | 2004-12-27 | 2008-11-18 | Intel Corporation | System and method for cache coherency in a cache with different cache location lengths |
US9026742B2 (en) * | 2007-12-21 | 2015-05-05 | Freescale Semiconductor, Inc. | System and method for processing potentially self-inconsistent memory transactions |
US8706982B2 (en) * | 2007-12-30 | 2014-04-22 | Intel Corporation | Mechanisms for strong atomicity in a transactional memory system |
US8327101B2 (en) * | 2008-02-01 | 2012-12-04 | International Business Machines Corporation | Cache management during asynchronous memory move operations |
US8806101B2 (en) * | 2008-12-30 | 2014-08-12 | Intel Corporation | Metaphysical address space for holding lossy metadata in hardware |
WO2010142432A2 (en) | 2009-06-09 | 2010-12-16 | Martin Vorbach | System and method for a cache in a multi-core processor |
US8812796B2 (en) | 2009-06-26 | 2014-08-19 | Microsoft Corporation | Private memory regions and coherence optimizations |
EP2668565B1 (en) * | 2011-01-27 | 2019-11-06 | Intel Corporation | Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor |
US8891535B2 (en) * | 2012-01-18 | 2014-11-18 | International Business Machines Corporation | Managing a global forwarding table in a distributed switch |
CN103049422B (zh) * | 2012-12-17 | 2013-11-27 | 浪潮电子信息产业股份有限公司 | 一种具有多cache一致性域的多处理器节点系统构建方法 |
US9514044B2 (en) * | 2013-05-24 | 2016-12-06 | Hewlett Packard Enterprise Development Lp | Multi-level cache tracking table |
WO2015075673A1 (en) * | 2013-11-21 | 2015-05-28 | Green Cache AB | Systems and methods for reducing first level cache energy by eliminating cache address tags |
JP2016004461A (ja) * | 2014-06-18 | 2016-01-12 | 富士通株式会社 | 情報処理装置、入出力制御装置および情報処理装置の制御方法 |
US10437479B2 (en) * | 2014-08-19 | 2019-10-08 | Samsung Electronics Co., Ltd. | Unified addressing and hierarchical heterogeneous storage and memory |
US10146690B2 (en) * | 2016-06-13 | 2018-12-04 | Intel Corporation | Synchronization logic for memory requests |
US10579527B2 (en) * | 2018-01-17 | 2020-03-03 | International Business Machines Corporation | Remote node broadcast of requests in a multinode data processing system |
-
2016
- 2016-11-04 KR KR1020187012983A patent/KR20180078253A/ko not_active Application Discontinuation
- 2016-11-04 WO PCT/IB2016/056655 patent/WO2017077502A1/en active Application Filing
- 2016-11-04 CN CN201680077811.9A patent/CN108475234B/zh active Active
- 2016-11-04 EP EP16794749.8A patent/EP3371707B1/en active Active
- 2016-11-04 SG SG11201803730TA patent/SG11201803730TA/en unknown
- 2016-11-04 US US15/773,357 patent/US10754777B2/en active Active
-
2020
- 2020-08-03 US US16/983,345 patent/US11237969B2/en active Active
-
2022
- 2022-01-31 US US17/588,545 patent/US11615026B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US11237969B2 (en) | 2022-02-01 |
US20220156191A1 (en) | 2022-05-19 |
EP3371707B1 (en) | 2021-10-27 |
US20200364144A1 (en) | 2020-11-19 |
CN108475234B (zh) | 2022-07-12 |
EP3371707A1 (en) | 2018-09-12 |
KR20180078253A (ko) | 2018-07-09 |
US11615026B2 (en) | 2023-03-28 |
US20180329819A1 (en) | 2018-11-15 |
CN108475234A (zh) | 2018-08-31 |
US10754777B2 (en) | 2020-08-25 |
WO2017077502A1 (en) | 2017-05-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG11201803730TA (en) | Systems and methods for implementing coherent memory in a multiprocessor system | |
SG11201904942YA (en) | Blockchain-based service execution method and apparatus, and electronic device | |
SG11201806404SA (en) | Systems and methods for storing and sharing transactional data using distributed computer systems | |
SG11201908813QA (en) | Anti-sirp alpha antibodies | |
SG11201909946UA (en) | Logistic regression modeling scheme using secrete sharing | |
SG11201906372PA (en) | Computer-implemented system and method for generating and extracting user related data stored on a blockchain | |
SG11201908451UA (en) | Method, apparatus, and system for blockchain consensus | |
SG11201908294TA (en) | System and method for parallel-processing blockchain transactions | |
SG11201805794XA (en) | Webinterface generation and testing using artificial neural networks | |
SG11201906834SA (en) | Achieving consensus among network nodes in a distributed system | |
SG11201901577SA (en) | Method and system for fast tracking navigation of blockchains via data manipulation | |
SG11201907842XA (en) | Method and apparatus for consensus verification | |
SG11201804538UA (en) | Systems and methods for improving security in blockchain-asset exchange | |
SG11201909868YA (en) | Compositions and methods of treating huntington's disease | |
SG11201900816TA (en) | A hybrid memory device | |
SG11201811426UA (en) | Distributed electronic record and transaction history | |
SG11201901548SA (en) | Anti-tim-3 antibodies and use thereof | |
SG11201909963YA (en) | Methods for treating dravet syndrome | |
SG11201909943SA (en) | System and method for high accuracy location determination and parking | |
SG11201907650RA (en) | Personal therapy and exercise monitoring and oversight devices, systems, and related methods | |
SG11201909561RA (en) | Octree-based convolutional neural network | |
SG11201809805WA (en) | Three-dimensional bioreactor for cell expansion and related applications | |
SG11201903670QA (en) | Packet loss tolerant transmission control protocol congestion control | |
SG11201909732QA (en) | Method of data aggregation for cache optimization and efficient processing | |
SG11201806570SA (en) | Barrier composites |