SG11201803518UA - Apparatuses and methods for adjusting write parameters based on a write count - Google Patents
Apparatuses and methods for adjusting write parameters based on a write countInfo
- Publication number
- SG11201803518UA SG11201803518UA SG11201803518UA SG11201803518UA SG11201803518UA SG 11201803518U A SG11201803518U A SG 11201803518UA SG 11201803518U A SG11201803518U A SG 11201803518UA SG 11201803518U A SG11201803518U A SG 11201803518UA SG 11201803518U A SG11201803518U A SG 11201803518UA
- Authority
- SG
- Singapore
- Prior art keywords
- write
- apparatuses
- methods
- parameters based
- adjusting
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
- G11C14/0045—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/927,329 US10643700B2 (en) | 2015-10-29 | 2015-10-29 | Apparatuses and methods for adjusting write parameters based on a write count |
| PCT/US2016/057488 WO2017074737A1 (en) | 2015-10-29 | 2016-10-18 | Apparatuses and methods for adjusting write parameters based on a write count |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201803518UA true SG11201803518UA (en) | 2018-05-30 |
Family
ID=58630824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201803518UA SG11201803518UA (en) | 2015-10-29 | 2016-10-18 | Apparatuses and methods for adjusting write parameters based on a write count |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US10643700B2 (en) |
| EP (1) | EP3368990B1 (en) |
| JP (1) | JP6716693B2 (en) |
| KR (1) | KR102076434B1 (en) |
| CN (1) | CN108292283B (en) |
| SG (1) | SG11201803518UA (en) |
| WO (1) | WO2017074737A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10643700B2 (en) | 2015-10-29 | 2020-05-05 | Micron Technology, Inc. | Apparatuses and methods for adjusting write parameters based on a write count |
| US10475519B2 (en) * | 2018-03-23 | 2019-11-12 | Micron Technology, Inc. | Methods for detecting and mitigating memory media degradation and memory devices employing the same |
| US11550650B2 (en) * | 2018-12-21 | 2023-01-10 | Micron Technology, Inc. | Methods for activity-based memory maintenance operations and memory devices and systems employing the same |
| US11158358B2 (en) * | 2019-07-22 | 2021-10-26 | Micron Technology, Inc. | Adaptive write operations for a memory device |
| US11403195B2 (en) * | 2019-08-07 | 2022-08-02 | Micron Technology, Inc. | Application of dynamic trim strategy in a die-protection memory sub-system |
| US10943657B1 (en) * | 2019-08-19 | 2021-03-09 | Micron Technology, Inc. | Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device |
| KR20210104499A (en) * | 2020-02-17 | 2021-08-25 | 에스케이하이닉스 주식회사 | Self write method and semiconductor device using the same |
| DE102021106756A1 (en) * | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUIT |
Family Cites Families (45)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08138374A (en) | 1994-11-10 | 1996-05-31 | Nec Corp | Semiconductor memory and refresh method therefor |
| KR100189530B1 (en) * | 1996-05-21 | 1999-06-01 | 윤종용 | Data interfacing method between microprocessor and memory |
| US6108764A (en) * | 1998-12-17 | 2000-08-22 | International Business Machines Corporation | Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention |
| JP2002133887A (en) | 2000-10-31 | 2002-05-10 | Matsushita Electric Ind Co Ltd | Non-volatile semiconductor memory |
| US7058668B2 (en) | 2002-01-11 | 2006-06-06 | International Business Machines Corporation | System for estimating the temporal validity of location reports through pattern analysis |
| JP2003242787A (en) | 2002-02-14 | 2003-08-29 | Mitsubishi Electric Corp | Nonvolatile semiconductor memory device |
| US7058665B1 (en) * | 2002-06-21 | 2006-06-06 | Unisys Corporation | Verification of data coherency in word-addressable files that support concurrent access |
| JP4633334B2 (en) * | 2003-01-27 | 2011-02-16 | パナソニック株式会社 | Information processing apparatus and memory access arbitration method |
| US6944063B2 (en) * | 2003-01-28 | 2005-09-13 | Sandisk Corporation | Non-volatile semiconductor memory with large erase blocks storing cycle counts |
| US20060282610A1 (en) | 2005-06-08 | 2006-12-14 | M-Systems Flash Disk Pioneers Ltd. | Flash memory with programmable endurance |
| JP4282636B2 (en) * | 2005-06-22 | 2009-06-24 | 株式会社東芝 | Nonvolatile semiconductor memory device and data writing method thereof |
| JP2007115099A (en) * | 2005-10-21 | 2007-05-10 | Toshiba Corp | Memory system and recording media |
| DE112006004187B4 (en) | 2006-12-27 | 2015-09-10 | Intel Corporation | A method, nonvolatile memory device, and an initiating wear compensation computer system for a nonvolatile memory |
| US7916543B2 (en) | 2007-10-22 | 2011-03-29 | Micron Technology, Inc. | Memory cell operation |
| JP5451011B2 (en) * | 2008-08-29 | 2014-03-26 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor memory device and information processing system |
| US8374036B2 (en) | 2008-11-14 | 2013-02-12 | Hynix Semiconductor Inc. | Method of operating nonvolatile memory device |
| US8250293B2 (en) * | 2009-01-19 | 2012-08-21 | Qimonda Ag | Data exchange in resistance changing memory for improved endurance |
| JP4666080B2 (en) * | 2009-02-09 | 2011-04-06 | Ｔｄｋ株式会社 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD |
| US7948798B1 (en) * | 2009-07-22 | 2011-05-24 | Marvell International Ltd. | Mixed multi-level cell and single level cell storage device |
| US8305812B2 (en) | 2009-08-26 | 2012-11-06 | Densbits Technologies Ltd. | Flash memory module and method for programming a page of flash memory cells |
| JP2013525937A (en) * | 2010-04-26 | 2013-06-20 | モサイド・テクノロジーズ・インコーポレーテッド | Write method in phase change memory |
| JP2012014816A (en) * | 2010-07-05 | 2012-01-19 | Toshiba Corp | Nonvolatile semiconductor storage device |
| US8737141B2 (en) | 2010-07-07 | 2014-05-27 | Stec, Inc. | Apparatus and method for determining an operating condition of a memory cell based on cycle information |
| US9741436B2 (en) * | 2010-07-09 | 2017-08-22 | Seagate Technology Llc | Dynamically controlling an operation execution time for a storage device |
| KR101686590B1 (en) | 2010-09-20 | 2016-12-14 | 삼성전자주식회사 | Flash memory system and wl interleaving method thereof |
| US8737138B2 (en) * | 2010-11-18 | 2014-05-27 | Micron Technology, Inc. | Memory instruction including parameter to affect operating condition of memory |
| JP2012203951A (en) | 2011-03-24 | 2012-10-22 | Toshiba Corp | Semiconductor storage device |
| US9047955B2 (en) | 2011-03-30 | 2015-06-02 | Stec, Inc. | Adjusting operating parameters for memory cells based on wordline address and cycle information |
| CN102915273B (en) * | 2011-08-02 | 2015-06-10 | 群联电子股份有限公司 | Data writing method, memory controller and memory storage device |
| US8694754B2 (en) * | 2011-09-09 | 2014-04-08 | Ocz Technology Group, Inc. | Non-volatile memory-based mass storage devices and methods for writing data thereto |
| WO2013040083A2 (en) * | 2011-09-15 | 2013-03-21 | The Regents Of The University Of California | Electro-mechanical diode non-volatile memory cell for cross-point memory arrays |
| US9195589B2 (en) * | 2011-12-27 | 2015-11-24 | Intel Corporation | Adaptive configuration of non-volatile memory |
| US8576651B2 (en) | 2012-01-20 | 2013-11-05 | Sandisk 3D Llc | Temperature compensation of conductive bridge memory arrays |
| US8819380B2 (en) * | 2012-03-21 | 2014-08-26 | International Business Machines Corporation | Consideration of adjacent track interference and wide area adjacent track erasure during block allocation |
| US8724388B2 (en) | 2012-04-02 | 2014-05-13 | Spansion Llc | Adaptively programming or erasing flash memory blocks |
| US8750045B2 (en) * | 2012-07-27 | 2014-06-10 | Sandisk Technologies Inc. | Experience count dependent program algorithm for flash memory |
| KR102015053B1 (en) * | 2013-02-20 | 2019-08-27 | 삼성전자주식회사 | Nonvolatile memory device and data processing method thereof |
| US9122404B2 (en) | 2013-03-15 | 2015-09-01 | International Business Machines Corporation | Adaptive reference tuning for endurance enhancement of non-volatile memories |
| US9153777B2 (en) * | 2013-06-03 | 2015-10-06 | Micron Technology, Inc. | Thermally optimized phase change memory cells and methods of fabricating the same |
| KR20150044753A (en) * | 2013-10-17 | 2015-04-27 | 에스케이하이닉스 주식회사 | Operating method for data storage device |
| CN206471309U (en) * | 2013-11-26 | 2017-09-05 | 珀金埃尔默健康科学股份有限公司 | Electron multiplier and the mass spectrograph using electron multiplier |
| US9001573B1 (en) | 2013-12-06 | 2015-04-07 | Micron Technology, Inc. | Method and apparatuses for programming memory cells |
| US20160070643A1 (en) * | 2014-09-08 | 2016-03-10 | Sandisk Technologies Inc. | System and method of counting program/erase cycles |
| US10101938B2 (en) * | 2014-12-30 | 2018-10-16 | International Business Machines Corporation | Data storage system selectively employing multiple data compression techniques |
| US10643700B2 (en) | 2015-10-29 | 2020-05-05 | Micron Technology, Inc. | Apparatuses and methods for adjusting write parameters based on a write count |
-
2015
- 2015-10-29 US US14/927,329 patent/US10643700B2/en active Active
-
2016
- 2016-10-18 SG SG11201803518UA patent/SG11201803518UA/en unknown
- 2016-10-18 KR KR1020187014407A patent/KR102076434B1/en active IP Right Grant
- 2016-10-18 CN CN201680070981.4A patent/CN108292283B/en active Active
- 2016-10-18 WO PCT/US2016/057488 patent/WO2017074737A1/en active Application Filing
- 2016-10-18 JP JP2018521640A patent/JP6716693B2/en active Active
- 2016-10-18 EP EP16860514.5A patent/EP3368990B1/en active Active
-
2020
- 2020-03-27 US US16/832,061 patent/US11145369B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20200227116A1 (en) | 2020-07-16 |
| JP2018532219A (en) | 2018-11-01 |
| EP3368990B1 (en) | 2022-02-23 |
| WO2017074737A1 (en) | 2017-05-04 |
| KR20180061383A (en) | 2018-06-07 |
| US20170125099A1 (en) | 2017-05-04 |
| CN108292283B (en) | 2022-03-29 |
| US10643700B2 (en) | 2020-05-05 |
| US11145369B2 (en) | 2021-10-12 |
| CN108292283A (en) | 2018-07-17 |
| EP3368990A1 (en) | 2018-09-05 |
| JP6716693B2 (en) | 2020-07-01 |
| KR102076434B1 (en) | 2020-02-11 |
| EP3368990A4 (en) | 2019-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| HK1245613A1 (en) | Multiple-firing securing device and methods for using and manufacturing same | |
| PL3378273T3 (en) | Methods and apparatuses for performing a resume procedure | |
| IL246992B (en) | Purge device and purge method | |
| SG11201702152VA (en) | System and method for a semi-lit market | |
| EP3280183A4 (en) | Path selection method and device | |
| SG10201501339QA (en) | Magnetoelectric Device, Method For Forming A Magnetoelectric Device, And Writing Method For A Magnetoelectric Device | |
| HK1210828A1 (en) | Path planning method and device | |
| SG11201803518UA (en) | Apparatuses and methods for adjusting write parameters based on a write count | |
| EP3104459A4 (en) | Antenna-direction adjusting device and antenna-direction adjusting method | |
| EP3057780A4 (en) | Systems and methods for producing a ball | |
| SG10201910372UA (en) | A hearing device and a method for operating thereof | |
| PL3552108T3 (en) | Apparatuses and methods for a processor architecture | |
| SG11201706615WA (en) | Methods and apparatuses for pushing a message | |
| HUE045440T2 (en) | Method and device for forming a battery | |
| PT3259667T (en) | Method and arrangement for checking a surface | |
| GB2532923B (en) | Methods and apparatus for securing a line | |
| EP4054108C0 (en) | Method for reporting channel status and device | |
| SE1550721A1 (en) | Method and control unit for adjusting a gap | |
| SG10201502903WA (en) | Integrated Demand Control Method And Integrated Demand Control Device | |
| GB2548644B (en) | Method for manufacturing magnetoresistive device | |
| EP3118188A4 (en) | Method and device for producing dicyanobenzene | |
| PL2930649T3 (en) | Devices and methods for determining a magnetic field | |
| GB2539611B (en) | Belt-finishing device and method for operating a belt-finishing device | |
| PL2930650T3 (en) | Devices and methods for determining a magnetic field | |
| GB201407900D0 (en) | A seating device |