SG11201701434SA - Method of constructing flat xor codes from integer indexed tanner graphs - Google Patents

Method of constructing flat xor codes from integer indexed tanner graphs

Info

Publication number
SG11201701434SA
SG11201701434SA SG11201701434SA SG11201701434SA SG11201701434SA SG 11201701434S A SG11201701434S A SG 11201701434SA SG 11201701434S A SG11201701434S A SG 11201701434SA SG 11201701434S A SG11201701434S A SG 11201701434SA SG 11201701434S A SG11201701434S A SG 11201701434SA
Authority
SG
Singapore
Prior art keywords
tanner graphs
flat xor
constructing flat
xor codes
indexed
Prior art date
Application number
SG11201701434SA
Inventor
Chao Jin
Weiya Xi
Khai Leong Yong
Shibin Chen
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Priority to SG11201701434SA priority Critical patent/SG11201701434SA/en
Publication of SG11201701434SA publication Critical patent/SG11201701434SA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/373—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
SG11201701434SA 2014-10-03 2015-09-29 Method of constructing flat xor codes from integer indexed tanner graphs SG11201701434SA (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG11201701434SA SG11201701434SA (en) 2014-10-03 2015-09-29 Method of constructing flat xor codes from integer indexed tanner graphs

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SG10201406332W 2014-10-03
SG11201701434SA SG11201701434SA (en) 2014-10-03 2015-09-29 Method of constructing flat xor codes from integer indexed tanner graphs
PCT/SG2015/050353 WO2016053188A1 (en) 2014-10-03 2015-09-29 Method of constructing flat xor codes from integer indexed tanner graphs

Publications (1)

Publication Number Publication Date
SG11201701434SA true SG11201701434SA (en) 2017-04-27

Family

ID=55631065

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201701434SA SG11201701434SA (en) 2014-10-03 2015-09-29 Method of constructing flat xor codes from integer indexed tanner graphs

Country Status (6)

Country Link
US (1) US10122381B2 (en)
EP (1) EP3178001A4 (en)
JP (1) JP2017533627A (en)
CN (1) CN107077401A (en)
SG (1) SG11201701434SA (en)
WO (1) WO2016053188A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101868785B (en) * 2007-09-21 2014-09-24 惠普开发有限公司 Generating a parallel recovery plan for a data storage system
US8250427B2 (en) * 2008-06-18 2012-08-21 Hewlett-Packard Development Company Selecting erasure codes for a fault tolerant system
US7925927B2 (en) * 2008-06-23 2011-04-12 Hewlett-Packard Development Company, L.P. Simulator for determining data loss in a fault tolerant system
US8689083B2 (en) 2010-06-15 2014-04-01 California Institute Of Technology Rate-compatible protograph LDPC codes

Also Published As

Publication number Publication date
WO2016053188A1 (en) 2016-04-07
JP2017533627A (en) 2017-11-09
EP3178001A1 (en) 2017-06-14
US10122381B2 (en) 2018-11-06
EP3178001A4 (en) 2018-03-28
US20170279462A1 (en) 2017-09-28
CN107077401A (en) 2017-08-18

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