SG11201610647PA - Mid-thread pre-emption with software assisted context switch - Google Patents

Mid-thread pre-emption with software assisted context switch

Info

Publication number
SG11201610647PA
SG11201610647PA SG11201610647PA SG11201610647PA SG11201610647PA SG 11201610647P A SG11201610647P A SG 11201610647PA SG 11201610647P A SG11201610647P A SG 11201610647PA SG 11201610647P A SG11201610647P A SG 11201610647PA SG 11201610647P A SG11201610647P A SG 11201610647PA
Authority
SG
Singapore
Prior art keywords
emption
mid
context switch
thread pre
software assisted
Prior art date
Application number
SG11201610647PA
Other languages
English (en)
Inventor
Brian D Rauchfuss
Naveen R Matam
Michael K Dwyer
Aditya Navale
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG11201610647PA publication Critical patent/SG11201610647PA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/253—Centralized memory
    • G06F2212/2532—Centralized memory comprising a plurality of modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Processing (AREA)
  • Image Generation (AREA)
SG11201610647PA 2014-07-23 2015-06-19 Mid-thread pre-emption with software assisted context switch SG11201610647PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/338,729 US9996386B2 (en) 2014-07-23 2014-07-23 Mid-thread pre-emption with software assisted context switch
PCT/US2015/036538 WO2016014182A1 (en) 2014-07-23 2015-06-19 Mid-thread pre-emption with software assisted context switch

Publications (1)

Publication Number Publication Date
SG11201610647PA true SG11201610647PA (en) 2017-01-27

Family

ID=55163509

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201610647PA SG11201610647PA (en) 2014-07-23 2015-06-19 Mid-thread pre-emption with software assisted context switch

Country Status (7)

Country Link
US (1) US9996386B2 (ko)
EP (1) EP3172660A4 (ko)
JP (1) JP6387571B2 (ko)
KR (1) KR102219545B1 (ko)
CN (1) CN106662995B (ko)
SG (1) SG11201610647PA (ko)
WO (1) WO2016014182A1 (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9996386B2 (en) 2014-07-23 2018-06-12 Intel Corporation Mid-thread pre-emption with software assisted context switch
US10453427B2 (en) 2017-04-01 2019-10-22 Intel Corporation Register spill/fill using shared local memory space
US10459751B2 (en) * 2017-06-30 2019-10-29 ATI Technologies ULC. Varying firmware for virtualized device
US10467159B2 (en) 2017-07-14 2019-11-05 Arm Limited Memory node controller
US10613989B2 (en) 2017-07-14 2020-04-07 Arm Limited Fast address translation for virtual machines
US10534719B2 (en) 2017-07-14 2020-01-14 Arm Limited Memory system for a data processing network
US10592424B2 (en) 2017-07-14 2020-03-17 Arm Limited Range-based memory system
US10489304B2 (en) 2017-07-14 2019-11-26 Arm Limited Memory address translation
US10565126B2 (en) 2017-07-14 2020-02-18 Arm Limited Method and apparatus for two-layer copy-on-write
US10353826B2 (en) * 2017-07-14 2019-07-16 Arm Limited Method and apparatus for fast context cloning in a data processing system
US10884850B2 (en) 2018-07-24 2021-01-05 Arm Limited Fault tolerant memory system
US11556374B2 (en) 2019-02-15 2023-01-17 International Business Machines Corporation Compiler-optimized context switching with compiler-inserted data table for in-use register identification at a preferred preemption point
US10909652B2 (en) 2019-03-15 2021-02-02 Intel Corporation Enabling product SKUs based on chiplet configurations
US11204767B2 (en) 2020-01-06 2021-12-21 International Business Machines Corporation Context switching locations for compiler-assisted context switching
US11874742B2 (en) * 2021-04-22 2024-01-16 Nvidia Corporation Techniques for recovering from errors when executing software applications on parallel processors
US20220413899A1 (en) * 2021-06-25 2022-12-29 Intel Corporation Barrier state save and restore for preemption in a graphics environment

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2523101B1 (en) * 2006-11-14 2014-06-04 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
US8589943B2 (en) 2007-08-15 2013-11-19 Sony Computer Entertainment Inc. Multi-threaded processing with reduced context switching
US8933953B2 (en) 2008-06-30 2015-01-13 Intel Corporation Managing active thread dependencies in graphics processing
US20130124838A1 (en) 2011-11-10 2013-05-16 Lacky V. Shah Instruction level execution preemption
US20130162661A1 (en) 2011-12-21 2013-06-27 Nvidia Corporation System and method for long running compute using buffers as timeslices
US8572573B2 (en) * 2012-03-09 2013-10-29 Nvidia Corporation Methods and apparatus for interactive debugging on a non-preemptible graphics processing unit
US8963933B2 (en) 2012-07-23 2015-02-24 Advanced Micro Devices, Inc. Method for urgency-based preemption of a process
US10095526B2 (en) 2012-10-12 2018-10-09 Nvidia Corporation Technique for improving performance in multi-threaded processing units
US9710874B2 (en) 2012-12-27 2017-07-18 Nvidia Corporation Mid-primitive graphics execution preemption
US9384036B1 (en) * 2013-10-21 2016-07-05 Google Inc. Low latency thread context caching
US9477480B2 (en) * 2014-01-30 2016-10-25 Nvidia Corporation System and processor for implementing interruptible batches of instructions
US9996386B2 (en) 2014-07-23 2018-06-12 Intel Corporation Mid-thread pre-emption with software assisted context switch
CN105801338B (zh) 2015-03-06 2018-08-14 胡淑婷 一种应用乙酰丙酮钯合成医药中间体菲类化合物的方法

Also Published As

Publication number Publication date
EP3172660A4 (en) 2018-03-21
US9996386B2 (en) 2018-06-12
CN106662995A (zh) 2017-05-10
CN106662995B (zh) 2019-12-03
JP6387571B2 (ja) 2018-09-12
KR20170010833A (ko) 2017-02-01
JP2017518575A (ja) 2017-07-06
WO2016014182A1 (en) 2016-01-28
US20160026494A1 (en) 2016-01-28
EP3172660A1 (en) 2017-05-31
KR102219545B1 (ko) 2021-02-23

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