SG10202007832SA - Composite ic chips including a chiplet embedded within metallization layers of a host ic chip - Google Patents
Composite ic chips including a chiplet embedded within metallization layers of a host ic chipInfo
- Publication number
- SG10202007832SA SG10202007832SA SG10202007832SA SG10202007832SA SG10202007832SA SG 10202007832S A SG10202007832S A SG 10202007832SA SG 10202007832S A SG10202007832S A SG 10202007832SA SG 10202007832S A SG10202007832S A SG 10202007832SA SG 10202007832S A SG10202007832S A SG 10202007832SA
- Authority
- SG
- Singapore
- Prior art keywords
- host
- composite
- chip
- metallization layers
- chips including
- Prior art date
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- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80909—Post-treatment of the bonding area
- H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US16/586,145 US11094672B2 (en) | 2019-09-27 | 2019-09-27 | Composite IC chips including a chiplet embedded within metallization layers of a host IC chip |
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DE (1) | DE102020123485A1 (en) |
SG (1) | SG10202007832SA (en) |
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US11094672B2 (en) | 2019-09-27 | 2021-08-17 | Intel Corporation | Composite IC chips including a chiplet embedded within metallization layers of a host IC chip |
US11205630B2 (en) | 2019-09-27 | 2021-12-21 | Intel Corporation | Vias in composite IC chip structures |
US11984376B2 (en) * | 2021-04-22 | 2024-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor device including a cooling structure |
US20230095914A1 (en) * | 2021-09-24 | 2023-03-30 | Intel Corporation | Test and debug support with hbi chiplet architecture |
TWI790036B (en) * | 2021-12-10 | 2023-01-11 | 財團法人工業技術研究院 | Electronic device having alignment mark |
CN114420681B (en) * | 2022-01-26 | 2024-05-07 | 西安电子科技大学 | Wafer-level reconfigurable Chiplet integrated structure |
CN115206952B (en) * | 2022-07-27 | 2023-03-17 | 北京数字光芯集成电路设计有限公司 | Micro-LED Micro-display chip adopting stacked package |
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US20080246126A1 (en) | 2007-04-04 | 2008-10-09 | Freescale Semiconductor, Inc. | Stacked and shielded die packages with interconnects |
JP5593053B2 (en) | 2009-10-09 | 2014-09-17 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device |
US20110175218A1 (en) | 2010-01-18 | 2011-07-21 | Shiann-Ming Liou | Package assembly having a semiconductor substrate |
KR20150066555A (en) | 2012-10-15 | 2015-06-16 | 피에스4 뤽스코 에스.에이.알.엘. | Semiconductor device |
KR101401708B1 (en) | 2012-11-15 | 2014-05-30 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
US9324698B2 (en) | 2013-08-13 | 2016-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip structure and method of forming same |
CN103730379A (en) | 2014-01-16 | 2014-04-16 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and structure |
US9368479B2 (en) | 2014-03-07 | 2016-06-14 | Invensas Corporation | Thermal vias disposed in a substrate proximate to a well thereof |
KR102254104B1 (en) | 2014-09-29 | 2021-05-20 | 삼성전자주식회사 | Semiconductor package |
US9570399B2 (en) | 2014-12-23 | 2017-02-14 | Mediatek Inc. | Semiconductor package assembly with through silicon via interconnect |
JP2016174101A (en) | 2015-03-17 | 2016-09-29 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
US9773757B2 (en) | 2016-01-19 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices, packaged semiconductor devices, and semiconductor device packaging methods |
KR102649471B1 (en) | 2016-09-05 | 2024-03-21 | 삼성전자주식회사 | Semiconductor package and method of fabricating the same |
US10347598B2 (en) | 2017-05-19 | 2019-07-09 | Samsung Electro-Mechanics Co., Ltd. | Composite antenna substrate and semiconductor package module |
KR102442623B1 (en) | 2017-08-08 | 2022-09-13 | 삼성전자주식회사 | Semiconductor package |
JP2019054181A (en) | 2017-09-19 | 2019-04-04 | 東芝メモリ株式会社 | Semiconductor package |
US10727217B2 (en) | 2017-09-29 | 2020-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor device that uses bonding layer to join semiconductor substrates together |
US10510650B2 (en) | 2018-02-02 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias |
US10910344B2 (en) * | 2018-06-22 | 2021-02-02 | Xcelsis Corporation | Systems and methods for releveled bump planes for chiplets |
US10867929B2 (en) | 2018-12-05 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods of forming the same |
US11139249B2 (en) | 2019-04-01 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of forming the same |
US11205630B2 (en) | 2019-09-27 | 2021-12-21 | Intel Corporation | Vias in composite IC chip structures |
US11094672B2 (en) | 2019-09-27 | 2021-08-17 | Intel Corporation | Composite IC chips including a chiplet embedded within metallization layers of a host IC chip |
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TW202127616A (en) | 2021-07-16 |
KR20210037530A (en) | 2021-04-06 |
US20210375830A1 (en) | 2021-12-02 |
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