SG10201900023RA - Semiconductor Memory Devices, Memory Systems And Methods Of Operating Semiconductor Memory Devices - Google Patents

Semiconductor Memory Devices, Memory Systems And Methods Of Operating Semiconductor Memory Devices

Info

Publication number
SG10201900023RA
SG10201900023RA SG10201900023RA SG10201900023RA SG10201900023RA SG 10201900023R A SG10201900023R A SG 10201900023RA SG 10201900023R A SG10201900023R A SG 10201900023RA SG 10201900023R A SG10201900023R A SG 10201900023RA SG 10201900023R A SG10201900023R A SG 10201900023RA
Authority
SG
Singapore
Prior art keywords
error
semiconductor memory
memory devices
syndrome
error bit
Prior art date
Application number
SG10201900023RA
Inventor
Cha Sang-Uhn
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201900023RA publication Critical patent/SG10201900023RA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3746—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with iterative decoding

Abstract

A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit. FIG. 2
SG10201900023RA 2018-01-25 2019-01-02 Semiconductor Memory Devices, Memory Systems And Methods Of Operating Semiconductor Memory Devices SG10201900023RA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020180009188A KR102453437B1 (en) 2018-01-25 2018-01-25 Semiconductor memory devices, memory systems including the same and method of operating semiconductor memory devices

Publications (1)

Publication Number Publication Date
SG10201900023RA true SG10201900023RA (en) 2019-08-27

Family

ID=67300316

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201900023RA SG10201900023RA (en) 2018-01-25 2019-01-02 Semiconductor Memory Devices, Memory Systems And Methods Of Operating Semiconductor Memory Devices

Country Status (5)

Country Link
US (2) US10698763B2 (en)
KR (1) KR102453437B1 (en)
CN (1) CN110085277B (en)
SG (1) SG10201900023RA (en)
TW (1) TWI769336B (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102350644B1 (en) * 2018-01-26 2022-01-14 에스케이하이닉스 주식회사 Memory controller and memory system having the same
US11016843B2 (en) * 2018-12-06 2021-05-25 Micron Technology, Inc. Direct-input redundancy scheme with adaptive syndrome decoder
US10956262B2 (en) * 2019-03-14 2021-03-23 Micron Technology, Inc. Deferred error code correction with improved effective data bandwidth performance
US10963336B2 (en) 2019-08-29 2021-03-30 Micron Technology, Inc. Semiconductor device with user defined operations and associated methods and systems
US11200118B2 (en) 2019-08-29 2021-12-14 Micron Technology, Inc. Semiconductor device with modified command and associated methods and systems
US11042436B2 (en) 2019-08-29 2021-06-22 Micron Technology, Inc. Semiconductor device with modified access and associated methods and systems
FR3100347B1 (en) 2019-09-04 2022-07-22 St Microelectronics Rousset Error detection
FR3100346B1 (en) 2019-09-04 2022-07-15 St Microelectronics Rousset Error detection
US11050442B2 (en) * 2019-09-17 2021-06-29 SK Hynix Inc. Reducing the latency of a syndrome-based quasi-cyclic decoder
KR20210034999A (en) * 2019-09-23 2021-03-31 에스케이하이닉스 주식회사 AIM device and method of multiplying/accumulation in the AIM device
KR20210038753A (en) * 2019-09-30 2021-04-08 에스케이하이닉스 주식회사 Data Storage Apparatus and Operating Method Thereof
KR20210088916A (en) * 2020-01-07 2021-07-15 에스케이하이닉스 주식회사 Apparatus and method for selecting an error solution operation of memory system by analyzing previously occurring error and data process system including the same
KR20210089016A (en) * 2020-01-07 2021-07-15 삼성전자주식회사 Memory controller and memory system
KR20210088917A (en) * 2020-01-07 2021-07-15 삼성전자주식회사 Semiconductor memory devices and memory systems including the same
JP7018089B2 (en) * 2020-04-02 2022-02-09 ウィンボンド エレクトロニクス コーポレーション Semiconductor storage device and readout method
KR20210132784A (en) 2020-04-27 2021-11-05 삼성전자주식회사 Memory device and method for reading data from memory device
CN112349343A (en) * 2020-11-06 2021-02-09 海光信息技术股份有限公司 Circuit structure, chip and electronic equipment
CN116940986A (en) * 2021-03-02 2023-10-24 美光科技公司 Method and system for reducing ECC power consumption
CN116343891A (en) * 2021-12-23 2023-06-27 长鑫存储技术有限公司 Memory block and memory
KR102619353B1 (en) * 2022-11-07 2023-12-29 넷솔 주식회사 Method of operating Memory for having high Reliability and Memory of implementing the same

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755779A (en) 1971-12-14 1973-08-28 Ibm Error correction system for single-error correction, related-double-error correction and unrelated-double-error detection
US4058851A (en) * 1976-10-18 1977-11-15 Sperry Rand Corporation Conditional bypass of error correction for dual memory access time selection
US4139148A (en) 1977-08-25 1979-02-13 Sperry Rand Corporation Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory
US4245303A (en) * 1978-10-25 1981-01-13 Digital Equipment Corporation Memory for data processing system with command and data buffering
US4319357A (en) 1979-12-14 1982-03-09 International Business Machines Corp. Double error correction using single error correcting code
US4319356A (en) * 1979-12-19 1982-03-09 Ncr Corporation Self-correcting memory system
US4597084A (en) * 1981-10-01 1986-06-24 Stratus Computer, Inc. Computer memory apparatus
JPH05197580A (en) 1992-01-21 1993-08-06 Nec Ibaraki Ltd Two-bit error correction circuit
US5502732A (en) * 1993-09-20 1996-03-26 International Business Machines Corporation Method for testing ECC logic
JPH1145595A (en) 1997-07-24 1999-02-16 Nec Corp Error correcting circuit for multilevel cell
JP2000348497A (en) * 1999-06-08 2000-12-15 Toshiba Corp Semiconductor memory device
JP2002056671A (en) 2000-08-14 2002-02-22 Hitachi Ltd Method for holding data for dynamic ram and semiconductor integrated circuit device
US7117420B1 (en) * 2001-05-17 2006-10-03 Lsi Logic Corporation Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories
JP2005310313A (en) * 2004-04-23 2005-11-04 Toshiba Corp Semiconductor storage device
US7437597B1 (en) * 2005-05-18 2008-10-14 Azul Systems, Inc. Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines
US7523381B2 (en) * 2005-09-01 2009-04-21 Micron Technology, Inc. Non-volatile memory with error detection
US7900100B2 (en) * 2007-02-21 2011-03-01 International Business Machines Corporation Uncorrectable error detection utilizing complementary test patterns
TWI397080B (en) * 2009-03-12 2013-05-21 Realtek Semiconductor Corp Memory apparatus and testing method thereof
CN102034552A (en) * 2009-09-25 2011-04-27 威刚科技（苏州）有限公司 Memory device and data processing method applied by same
WO2012039983A1 (en) 2010-09-24 2012-03-29 Rambus Inc. Memory device with ecc history table
US8984367B2 (en) * 2011-02-25 2015-03-17 Altera Corporation Error detection and correction circuitry
US9362953B2 (en) 2013-08-02 2016-06-07 Infineon Technologies Ag Efficient error correction of multi-bit errors
US9690640B2 (en) * 2013-09-26 2017-06-27 Intel Corporation Recovery from multiple data errors
US9529665B2 (en) 2014-03-26 2016-12-27 Intel Corporation Double consecutive error correction
KR101999288B1 (en) 2014-07-15 2019-07-11 에스케이하이닉스 주식회사 Error correcting Device and method for memory data
KR102189780B1 (en) * 2014-08-11 2020-12-11 삼성전자주식회사 Semiconductor memory device and memory system including the same
KR102210327B1 (en) * 2014-08-21 2021-02-01 삼성전자주식회사 Memory device having error inform function
KR102178137B1 (en) 2014-08-26 2020-11-12 삼성전자주식회사 Semiconductor memory device, method of correcting error in the same and memory system including the same
TWI521531B (en) * 2015-02-25 2016-02-11 群聯電子股份有限公司 Data reading method, memory controlling circuit unit and memory storage device
TWI573146B (en) * 2015-05-28 2017-03-01 旺宏電子股份有限公司 memory device and OPERATION method thereof
KR102296738B1 (en) * 2015-06-01 2021-09-01 삼성전자 주식회사 Semiconductor memory device, memory system including the same, and method of error correction of the same
KR102290020B1 (en) * 2015-06-05 2021-08-19 삼성전자주식회사 Semiconductor memory device providing analiysis and relief of soft data fail in stacked chips
KR102324769B1 (en) * 2015-06-29 2021-11-10 삼성전자주식회사 Error correction circuit, semiconductor memory device and memory system including the same
US9800271B2 (en) 2015-09-14 2017-10-24 Qualcomm Incorporated Error correction and decoding
KR20170045803A (en) * 2015-10-20 2017-04-28 삼성전자주식회사 Semiconductor memory device and memory system including the same
US10097207B2 (en) 2016-03-10 2018-10-09 Toshiba Memory Corporation ECC circuit, storage device and memory system
KR20170121798A (en) * 2016-04-26 2017-11-03 삼성전자주식회사 Semiconductor memory device and method of operating the same

Also Published As

Publication number Publication date
TWI769336B (en) 2022-07-01
US10698763B2 (en) 2020-06-30
CN110085277A (en) 2019-08-02
US20190229753A1 (en) 2019-07-25
US11385960B2 (en) 2022-07-12
US20200301776A1 (en) 2020-09-24
KR102453437B1 (en) 2022-10-12
KR20190090472A (en) 2019-08-02
CN110085277B (en) 2023-07-28
TW201933099A (en) 2019-08-16

Similar Documents

Publication Publication Date Title
SG10201900023RA (en) Semiconductor Memory Devices, Memory Systems And Methods Of Operating Semiconductor Memory Devices
US9690650B2 (en) Storage scheme for built-in ECC operations
TWI792682B (en) Error correcting memory systems
CN102385538B (en) Semiconductor memory device and method of controlling the same
US9819362B2 (en) Apparatus and method for detecting and mitigating bit-line opens in flash memory
US9312885B2 (en) Nonvolatile semiconductor memory system error correction capability of which is improved
US9535785B2 (en) ECC method for flash memory
US9923578B2 (en) Parity check circuit and memory device including the same
US10885972B2 (en) SRAM with error correction in retention mode
TWI643062B (en) Flash memory apparatus and storage management method for flash memory
US9412465B2 (en) Reliable readout of fuse data in an integrated circuit
KR20150090414A (en) Semicondcutor device performing error correction
US10741212B2 (en) Error correction code (ECC) encoders, ECC encoding methods capable of encoding for one clock cycle, and memory controllers including the ECC encoders
US20150143187A1 (en) Implementing enhanced performance with read before write to phase change memory
KR20190064100A (en) Memory system and error correcting method of the same
KR20200052842A (en) Memory system, memory module and operation method of memory system
JP2010238363A (en) Semiconductor storage device
JPH09288895A (en) Ternary storage semiconductor storage system
US10319455B2 (en) Semiconductor device
US11949428B2 (en) Iterative error correction in memory systems
US9092354B2 (en) Storage device, CRC generation device, and CRC generation method
US9275758B2 (en) Error detection circuit and semiconductor integrated circuit using the same
US20120144278A1 (en) Error code pattern generation circuit and semiconductor memory device including the same
US9286158B2 (en) Programming method, reading method and operating system for memory
TWI829252B (en) Method and computer program product and apparatus for decoding low-density parity-check (ldpc) code