SG10201804015PA - Memory device including voltage regions and method of operating same - Google Patents

Memory device including voltage regions and method of operating same

Info

Publication number
SG10201804015PA
SG10201804015PA SG10201804015PA SG10201804015PA SG10201804015PA SG 10201804015P A SG10201804015P A SG 10201804015PA SG 10201804015P A SG10201804015P A SG 10201804015PA SG 10201804015P A SG10201804015P A SG 10201804015PA SG 10201804015P A SG10201804015P A SG 10201804015PA
Authority
SG
Singapore
Prior art keywords
memory device
path region
power voltage
read
device including
Prior art date
Application number
SG10201804015PA
Inventor
Kim Young-Hwa
Oh Tae-Young
Jang Jin-Hoon
Cho Seok-Jin
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201804015PA publication Critical patent/SG10201804015PA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A memory device having a plurality of voltage regions and a method of operating the same are provided. The memory device includes a memory cell array, a data path region including data processing blocks transmitting read/write data from/to the memory cell array during read/write operations, and a control signal path region including control blocks controlling the data processing blocks during the read/write operations. The data path region selectively receives a first high power voltage or a first low power voltage in accordance with an operating mode of the memory device. The control signal path region receives the first high power voltage regardless of the operating mode. FIG. 1
SG10201804015PA 2017-07-20 2018-05-11 Memory device including voltage regions and method of operating same SG10201804015PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20170092261 2017-07-20
KR1020170147612A KR20190010390A (en) 2017-07-20 2017-11-07 Memory Device including a plurality of voltage regions and Operating Method thereof

Publications (1)

Publication Number Publication Date
SG10201804015PA true SG10201804015PA (en) 2019-02-27

Family

ID=65276681

Family Applications (3)

Application Number Title Priority Date Filing Date
SG10201804015PA SG10201804015PA (en) 2017-07-20 2018-05-11 Memory device including voltage regions and method of operating same
SG10201806160YA SG10201806160YA (en) 2017-07-20 2018-07-18 Memory device including a plurality of power rails and method of operating the same
SG10201806186UA SG10201806186UA (en) 2017-07-20 2018-07-19 Memory device including dynamic voltage and frequency scaling switch and method of operating the same

Family Applications After (2)

Application Number Title Priority Date Filing Date
SG10201806160YA SG10201806160YA (en) 2017-07-20 2018-07-18 Memory device including a plurality of power rails and method of operating the same
SG10201806186UA SG10201806186UA (en) 2017-07-20 2018-07-19 Memory device including dynamic voltage and frequency scaling switch and method of operating the same

Country Status (2)

Country Link
KR (3) KR20190010390A (en)
SG (3) SG10201804015PA (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9921916B2 (en) 2015-12-18 2018-03-20 Intel Corporation Management of power loss in a memory device
US10754404B2 (en) * 2016-09-30 2020-08-25 Intel Corporation Compensation control for variable power rails

Also Published As

Publication number Publication date
KR102504288B1 (en) 2023-02-28
KR20190010437A (en) 2019-01-30
SG10201806160YA (en) 2019-02-27
KR20190010442A (en) 2019-01-30
KR102477269B1 (en) 2022-12-14
KR20190010390A (en) 2019-01-30
SG10201806186UA (en) 2019-02-27

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