SG10201707700WA - Performing Kernel Striding In Hardware - Google Patents

Performing Kernel Striding In Hardware

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Publication number
SG10201707700WA
SG10201707700WA SG10201707700WA SG10201707700WA SG10201707700WA SG 10201707700W A SG10201707700W A SG 10201707700WA SG 10201707700W A SG10201707700W A SG 10201707700WA SG 10201707700W A SG10201707700W A SG 10201707700WA SG 10201707700W A SG10201707700W A SG 10201707700WA
Authority
SG
Singapore
Prior art keywords
tensor
neural network
convolutional neural
network layer
generate
Prior art date
Application number
SG10201707700WA
Inventor
Reginald Clifford Young
William John Gulland
Original Assignee
Google Llc
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Publication date
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Publication of SG10201707700WA publication Critical patent/SG10201707700WA/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/045Combinations of networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/0464Convolutional networks [CNN, ConvNet]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks

Abstract

PERFORMING KERNEL STRIDING IN HARDWARE Methods for receiving a request to process, on a hardware circuit, a neural network comprising a first convolutional neural network layer having a stride greater than one, and in response, generating instructions that cause the hardware circuit to, during processing of an input tensor, generate a layer output tensor equivalent to an output of the first convolutional neural network layer by processing the input tensor using a second convolutional neural network layer having a stride equal to one but that is otherwise equivalent to the first convolutional neural network layer to generate a first tensor, zeroing out elements of the first tensor that would not have been generated if the second convolutional neural network layer had the stride of the first convolutional neural network layer to generate a second tensor, and performing max pooling on the second tensor to generate the layer output tensor. Fig. 9
SG10201707700WA 2016-11-10 2017-09-18 Performing Kernel Striding In Hardware SG10201707700WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/348,199 US10733505B2 (en) 2016-11-10 2016-11-10 Performing kernel striding in hardware
US15/467,382 US9721203B1 (en) 2016-11-10 2017-03-23 Performing kernel striding in hardware

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SG10201707700WA true SG10201707700WA (en) 2018-06-28

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US (3) US10733505B2 (en)
EP (2) EP4336411A3 (en)
JP (2) JP6987860B2 (en)
KR (2) KR102512936B1 (en)
CN (2) CN114897132A (en)
DE (2) DE202017105729U1 (en)
GB (2) GB2556670B (en)
HK (1) HK1254699A1 (en)
IE (1) IE20170205A1 (en)
SG (2) SG10201804284XA (en)
WO (1) WO2018089079A1 (en)

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SG10201804284XA (en) 2018-07-30
EP3539059B1 (en) 2024-02-28
JP7394104B2 (en) 2023-12-07
KR20220047680A (en) 2022-04-18
US20180129936A1 (en) 2018-05-10
US10733505B2 (en) 2020-08-04
WO2018089079A1 (en) 2018-05-17
GB201715309D0 (en) 2017-11-08
DE202017105729U1 (en) 2018-01-03
GB2556670A (en) 2018-06-06
GB2583594A (en) 2020-11-04
US11816532B2 (en) 2023-11-14
JP2022037022A (en) 2022-03-08
US9721203B1 (en) 2017-08-01
GB2583594B (en) 2021-07-28
DE102017121887A1 (en) 2018-05-17
JP2019537139A (en) 2019-12-19
HK1254699A1 (en) 2019-07-26
EP4336411A2 (en) 2024-03-13
CN108073983A (en) 2018-05-25
EP4336411A3 (en) 2024-04-24
EP3539059A1 (en) 2019-09-18
KR102512936B1 (en) 2023-03-21
CN114897132A (en) 2022-08-12
JP6987860B2 (en) 2022-01-05
GB202008121D0 (en) 2020-07-15
KR20190084088A (en) 2019-07-15
KR102385843B1 (en) 2022-04-11
CN108073983B (en) 2022-04-26
IE20170205A1 (en) 2018-05-16
US20200334536A1 (en) 2020-10-22
GB2556670B (en) 2020-07-15

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