SG10201406424SA - A hybrid tsv and method for forming the same - Google Patents

A hybrid tsv and method for forming the same

Info

Publication number
SG10201406424SA
SG10201406424SA SG10201406424SA SG10201406424SA SG10201406424SA SG 10201406424S A SG10201406424S A SG 10201406424SA SG 10201406424S A SG10201406424S A SG 10201406424SA SG 10201406424S A SG10201406424S A SG 10201406424SA SG 10201406424S A SG10201406424S A SG 10201406424SA
Authority
SG
Singapore
Prior art keywords
forming
same
hybrid tsv
tsv
hybrid
Prior art date
Application number
SG10201406424SA
Inventor
Hong Yu
Huang Liu
Feng Zhao
Original Assignee
Globalfoundries Sg Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Sg Pte Ltd filed Critical Globalfoundries Sg Pte Ltd
Publication of SG10201406424SA publication Critical patent/SG10201406424SA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG10201406424SA 2011-04-21 2012-04-13 A hybrid tsv and method for forming the same SG10201406424SA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/091,277 US9006102B2 (en) 2011-04-21 2011-04-21 Hybrid TSV and method for forming the same

Publications (1)

Publication Number Publication Date
SG10201406424SA true SG10201406424SA (en) 2014-11-27

Family

ID=47020667

Family Applications (2)

Application Number Title Priority Date Filing Date
SG10201406424SA SG10201406424SA (en) 2011-04-21 2012-04-13 A hybrid tsv and method for forming the same
SG2012027009A SG185219A1 (en) 2011-04-21 2012-04-13 A hybrid tsv and method for forming the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG2012027009A SG185219A1 (en) 2011-04-21 2012-04-13 A hybrid tsv and method for forming the same

Country Status (2)

Country Link
US (2) US9006102B2 (en)
SG (2) SG10201406424SA (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8822336B2 (en) * 2011-06-16 2014-09-02 United Microelectronics Corp. Through-silicon via forming method
US20130119543A1 (en) * 2011-11-16 2013-05-16 Globalfoundries Singapore Pte. Ltd. Through silicon via for stacked wafer connections
FR2993400A1 (en) * 2012-07-12 2014-01-17 St Microelectronics Crolles 2 THREE-DIMENSIONAL INTEGRATED STRUCTURE FOR DETECTING TEMPERATURE ELEVATION
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
US20150021773A1 (en) * 2013-07-22 2015-01-22 Conversant Intellectual Property Management Inc. Through Semiconductor via Structure with Reduced Stress Proximity Effect
US9147642B2 (en) * 2013-10-31 2015-09-29 Nanya Technology Corporation Integrated circuit device
US9543229B2 (en) 2013-12-27 2017-01-10 International Business Machines Corporation Combination of TSV and back side wiring in 3D integration
US9412736B2 (en) 2014-06-05 2016-08-09 Globalfoundries Inc. Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias
US9343385B2 (en) * 2014-07-30 2016-05-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device comprising a chip substrate, a mold, and a buffer layer
US9553080B1 (en) * 2015-09-18 2017-01-24 Globalfoundries Inc. Method and process for integration of TSV-middle in 3D IC stacks
WO2017052472A1 (en) * 2015-09-22 2017-03-30 Agency For Science, Technology And Research Semiconductor device and method of forming the same
US9728506B2 (en) 2015-12-03 2017-08-08 Globalfoundries Inc. Strain engineering devices using partial depth films in through-substrate vias
US9691864B1 (en) * 2016-05-13 2017-06-27 Infineon Technologies Americas Corp. Semiconductor device having a cavity and method for manufacturing thereof
FR3076074A1 (en) 2017-12-21 2019-06-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR MANUFACTURING A THROUGH DEVICE
CN110491847B (en) * 2018-05-14 2020-12-29 北京信息科技大学 Silicon through hole-based neuron functional circuit unit
KR20220001956A (en) * 2020-06-30 2022-01-06 삼성전자주식회사 Integrated circuit device and semiconductor package including the same
KR20220017023A (en) 2020-08-03 2022-02-11 삼성전자주식회사 Semiconductor device and semiconductor package
US11810857B2 (en) * 2020-08-25 2023-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Via for semiconductor device and method
US20220115295A1 (en) * 2020-10-13 2022-04-14 Changxin Memory Technologies, Inc. Conductive structure, semiconductor structure and manufacturing method thereof
US12119286B2 (en) * 2021-05-19 2024-10-15 Changxin Memory Technologies, Inc. Die, memory and method of manufacturing die
CN115376993A (en) * 2021-05-19 2022-11-22 长鑫存储技术有限公司 Chip, memory and preparation method of chip

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222254B1 (en) 1997-03-31 2001-04-24 Intel Corporation Thermal conducting trench in a semiconductor structure and method for forming the same
CN101079408A (en) 2006-05-22 2007-11-28 中芯国际集成电路制造(上海)有限公司 Double-inlay structure and its making method
US7812459B2 (en) * 2006-12-19 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuits with protection layers
US7615480B2 (en) * 2007-06-20 2009-11-10 Lam Research Corporation Methods of post-contact back end of the line through-hole via integration
US8062975B2 (en) 2009-04-16 2011-11-22 Freescale Semiconductor, Inc. Through substrate vias
US8822329B2 (en) * 2009-09-28 2014-09-02 Infineon Technologies Ag Method for making conductive interconnects

Also Published As

Publication number Publication date
US20120267788A1 (en) 2012-10-25
SG185219A1 (en) 2012-11-29
US9269651B2 (en) 2016-02-23
US9006102B2 (en) 2015-04-14
US20150179547A1 (en) 2015-06-25

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