CN110491847B - Silicon through hole-based neuron functional circuit unit - Google Patents
Silicon through hole-based neuron functional circuit unit Download PDFInfo
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- 210000002569 neuron Anatomy 0.000 title claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 26
- 239000010703 silicon Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000007667 floating Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 9
- 239000003990 capacitor Substances 0.000 abstract description 8
- 230000008569 process Effects 0.000 abstract description 6
- 210000004027 cell Anatomy 0.000 abstract description 4
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- 230000008901 benefit Effects 0.000 description 5
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- 238000013459 approach Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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Abstract
The invention relates to a neuron functional circuit unit based on a through silicon via, which comprises a substrate, the through silicon via, a transistor and an interconnection, wherein a capacitor consisting of metal, silicon dioxide and an N-type heavily doped layer in the through silicon via is connected with the transistor to form a floating gate structure. The cell provided by the invention utilizes the principle of a floating gate, and has the function of comparing the weighted sum of a plurality of input voltage signals with a threshold value to obtain a binary output so as to form a basic circuit cell for calculating the nerve morphology. Meanwhile, the floating gate structure is realized by adopting a mature process technology, so that the unit is easy to process, the difficulty in manufacturing is avoided, and meanwhile, the working principle of the floating gate structure is based on charge summation rather than current summation, so that the power consumption is effectively reduced.
Description
Technical Field
The invention relates to a silicon through hole-based neuron functional circuit unit and a manufacturing method thereof.
Background
The three-dimensional integration technology is an important supporting technology for high-density system formation in the future, and compared with the traditional plane integration scheme for obtaining higher integration level by reducing the characteristic size, the three-dimensional integration technology provides a technical approach exceeding Moore's law, and can realize higher integration level, lower power consumption and lower cost on the basis of the original integration level. Whether on three-dimensional integrated circuits (3D-ICs) or system-in-package systems with interposers (3D-SIP) as above, Through Silicon Vias (TSVs) are always indispensable key components, which function as vertical interconnect channels for electrical signals. The human brain can realize interaction with the external environment and autonomous learning, and has the advantages of low power consumption, high fault tolerance, high parallelism, asynchronous information processing and the like. The construction of computer systems that can learn autonomously as well as the human brain and have brain-like general intelligence is an ultimate goal of the development of computers and intelligent technologies, and in such a context, "brain-like computing" has come to mind. In a brain-like computing system, the traditional von Neumann architecture is completely abandoned, the performance problem caused by the von Neumann bottleneck is fundamentally solved through the simulated neural network architecture, highly parallel operation is realized, the intelligent level which cannot be reached by the traditional computer is realized at extremely low hardware cost, and the technology becomes a key enabling technology of a new generation of computers and intelligent industries. Neuromorphic computing is a new and important way to revolutionize artificial intelligence. The novel electronic component is used for simulating the functions of synapses and neurons, and a new idea is formed. Having highly active through-silicon vias (TSVs) in three-dimensional integrated interconnects has proven to be a potential for completing the physical processes of brain-activated computing circuits. Also, the coupling capacitance between the through-silicon vias can be utilized as the membrane capacitance of the neuron, making it feasible to implement this technique with through-silicon vias.
Disclosure of Invention
The invention aims to provide a semiconductor structure containing silicon through holes and transistors and a manufacturing method thereof aiming at a three-dimensional integrated system, so as to complete the function of a neuron.
According to one aspect of the invention, a through silicon via based neuron functional circuit unit comprises a substrate, an interconnection layer, a transistor and a through hole. The method is characterized in that the substrate is a P-type substrate; the number of the through holes is at least two, and the filling sequence of the through holes is respectively metal and SiO from inside to outside2And the insulating layer and the heavily doped N-type polycrystalline silicon are filled in a coaxial cylindrical ring mode. The metal is a solid cylinder, the heavily doped N-type polycrystalline silicon is in direct contact with the P-type substrate, no other medium is needed in the middle, and a depletion region is formed due to contact. The coaxial capacitor has the beneficial effects that the coaxial capacitor is formed by the three layers of materials to form the input coupling capacitor. The transistors are NMOS transistors, and the number of the transistors is not less than one. The heavily doped N-type polysilicon is electrically connected with the gate of the NMOS transistor through an interconnection layer. The floating gate structure has the beneficial effects that the floating gate structure is formed, wherein the metal in each through hole is equivalent to the control gate and SiO in the floating gate structure2The insulating layer is equal to the insulating layer between a control gate and a floating gate in the floating gate structure, the heavily doped N-type polycrystalline silicon and the P-type substrate form a reverse bias type PN junction so as to achieve the purpose of insulation, and the coupling capacitance between the gate and the channel of the NMOS is equal to the coupling capacitance between the floating gate and the channel in the floating gate structure, so that the neuron weighting and summing function of the Rosen-blat sensor to be completed by the floating gate structure is completed.
In some embodiments, the transistors in the present invention are NMOS type transistors; integrated on the surface of the P-type substrate. The substrate potential thereof needs to be grounded. This embodiment may include guard rings which have the benefit of preventing noise coupling from the substrate from interfering with the vias.
In other embodiments, the transistors in the present invention are NMOS type transistors; integrated on a separate chip rather than on a single chip with vias.
The substrate in the invention is a bare chip or one or more of the following structures on the first surface and/or the second surface of the substrate: a semiconductor device, an electrical interconnect layer, a microsensor structure, a pad, or a passivation layer.
According to another aspect of the invention, the substrate has first and second opposing surfaces, wherein the first surface has a layer of the auxiliary wafer bonded thereto.
The circuit unit comprises a rewiring layer and a metal solder ball, wherein the metal solder ball is positioned on the rewiring layer and is electrically connected with the rewiring layer, and the rewiring layer is electrically connected with the through hole.
The invention has the beneficial effect that the framework of the Rosen-blatt sensor is formed, namely, a plurality of inputs are multiplied by a fixed weight value respectively and then summed, and an output which is turned on or turned off is obtained at the transistor. The weight value is input by a coupling capacitor CiDetermining the potential V on the floating gateFGThe result of the summation is indicated.
The invention provides a manufacturing method aiming at the circuit unit, which comprises the following steps:
(1) etching a plurality of deep holes on the first surface of the substrate; wherein the substrate has opposing first and second surfaces. (2) Formation of heavily doped n-type polysilicon and SiO by diffusion, LPCVD2An insulating layer. (3) And filling metal or heavily doped polysilicon into the residual through holes. (4) And thinning the second surface of the substrate to expose the bottom of the substrate. (5) The substrate may be bonded to a secondary wafer before thinning of the substrate.
In the manufacturing method provided by the invention, the etching method of the deep hole comprises the following steps:
(1) forming a mask layer on the first surface of the substrate, and patterning the mask layer to form a plurality of openings; (2) and etching the substrate according to the opening on the mask layer to form a plurality of deep holes.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. one is a schematic diagram of a Rosen-blatt sensor.
Fig. two is a schematic diagram of a neuron transistor structure formed by a floating gate structure.
Fig. three is an equivalent circuit diagram of fig. two.
Fig. four is a schematic view of a horizontal cross section of the through-silicon via of the present invention as shown in claim 1.
FIG. five is a schematic diagram of the TSV based neuron functional circuit unit of the present invention as described in claim 2.
Fig. six is a schematic diagram of the tsv-based neuron functional circuit unit according to the present invention as shown in fig. 3.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the applicability of other processes and/or the use of other materials. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
The structure of the invention is suitable for being applied to a three-dimensional integrated system with a Through Silicon Via (TSV) structure, the main structure of the structure is a circuit unit with a neuron function, which is formed by connecting a semiconductor structure with a TSV and a transistor through an interconnection line, and the circuit unit is characterized by comprising a substrate, a through hole, a transistor and an interconnection layer. The method is characterized in that the substrate is a P-type substrate; the filling sequence of the through holes is respectively metal and SiO from inside to outside2The insulating layer and the heavily doped N-type polycrystalline silicon are filled in a coaxial cylindrical ring mode from inside to outside; there is no other material between each layer of material. The transistor is an NPN transistor; the transistor may or may not be integrated on the same substrate, either on the surface of the P-type substrate where the through-silicon via is also located. The heavily doped N-type polysilicon is electrically connected with the gate of the NMOS transistor through an interconnection layer. Metal, SiO2The insulating layer and the heavily doped N-type polycrystalline silicon form an MIS structure in semiconductor physics, and have remarkable capacitance characteristics, and the whole through hole forms a cylindrical capacitor. The floating gate structure has the advantages that the capacitance characteristics of the silicon through holes are connected with the transistors to form the floating gate structure, the capacitance value between the silicon through holes can be used as the weight of the neuron, and output can be obtained on the floating gate according to the weighted sum of the capacitance value and the weight of the neuron. Thus, the output of the transistor constitutes a Rosen-blatt perceptron, performing neuronal function. The heavily doped N-type polycrystalline silicon and the P substrate form a PN junction in a reverse bias state, and noise coupling transmitted from the substrate is effectively prevented.
One important advantage of this circuit cell over the structure of conventional three-dimensional integrated systems is that the through-silicon-via no longer operates merely as a signal transmission path, but rather as a capacitor, exploiting its function as a semiconductor device. The invention can utilize redundant silicon through holes in the three-dimensional integrated circuit to play the function of the three-dimensional integrated circuit. Compared with the traditional floating gate structure, the circuit utilizes the technology of a three-dimensional integrated circuit and combines the neuromorphic calculation with the three-dimensional integrated circuit, so that the neuromorphic calculation structure is closer to a biological neuron.
According to one aspect of the present invention, there is provided a system of through-silicon-via based neuron functional circuit cellsThe manufacturing method comprises the following steps of 1) etching a plurality of deep holes on the surface of a substrate; wherein the substrate has opposing first and second surfaces; 2) etching a plurality of deep holes on the first surface of the substrate; formation of heavily doped n-type polysilicon and SiO by diffusion, LPCVD2An insulating layer. 3) Filling metal or heavily doped polysilicon into the remaining through holes; 4) and thinning the second surface of the substrate to expose the bottom of the substrate. The manufacturing method has high feasibility.
Compared with the prior art, the invention has the following positive effects: as a physical implementation of neuromorphic computational techniques, both the neuron through-silicon-via cells and the interconnections therein benefit from the flexibility and similarity of through-silicon-vias. The neuron through silicon via unit is a three-dimensional structure unit, the design simulates the biological brain, and the silicon via for signal or energy transmission among different layers stacked by chips is utilized. The through silicon vias have an oxide layer and an N-type doped epitaxial layer and can work together as a strong input coupling capacitor with MOS transistors on the same silicon wafer or transistors on other silicon wafers.
The invention applies the nerve morphological structure to three-dimensional integration for the first time, and utilizes the existing semiconductor process and technology to realize the structure of the neuron function.
Claims (10)
1. A neuron functional circuit unit based on a through silicon via comprises a substrate, a through hole, a transistor and an interconnection, and is characterized in that the substrate is a P-type substrate; the through hole is filled with metal, a silicon dioxide insulating layer and an N-type heavily doped layer in a coaxial cylindrical ring mode from inside to outside, and the N-type heavily doped layer is electrically connected with a grid electrode of the transistor through interconnection to form a floating gate structure.
2. The neuron functional circuit unit of claim 1, wherein the transistor is an NMOS type transistor; integrated on the surface of the P-type substrate.
3. The neuron functional circuit unit of claim 1, wherein the transistor is an NMOS type transistor; integrated on another separate chip.
4. The neuron functional circuit unit of claim 2 or 3, wherein the N-type heavily doped layer is connected to a gate of the NMOS transistor through an interconnect.
5. The neuron functional circuit unit of claim 2 or 3, wherein the substrate is a die or has one or more of the following structures on the first surface and/or the second surface of the substrate: semiconductor devices, passive components, interconnects, microsensor structures, pads, or passivation layers.
6. The neuron functional circuit unit of claim 2 or 3, wherein the substrate has first and second opposing surfaces, and wherein the first surface has a layer of an assist wafer bonded thereto.
7. A manufacturing method of a neuron functional circuit unit based on a through silicon via comprises the following steps:
1) etching a plurality of deep holes on the first surface of the substrate; wherein the substrate has opposing first and second surfaces;
2) forming an N-type heavily doped polysilicon layer in the through hole by LPCVD;
3) forming a silicon dioxide layer in the via hole by LPCVD;
4) filling metal into the through hole;
5) thinning the second surface of the substrate to expose the bottom of the substrate;
6) and the N-type heavily doped polysilicon layer is electrically connected with the grid electrode of the transistor through interconnection to form a floating gate structure.
8. A manufacturing method of a neuron functional circuit unit based on a through silicon via comprises the following steps:
1) etching a plurality of deep holes on the first surface of the substrate; wherein the substrate has opposing first and second surfaces;
2) forming an N-type heavily doped monocrystalline silicon layer in the through hole by injection or diffusion;
3) forming a silicon dioxide layer in the via hole by LPCVD;
4) filling metal into the through hole;
5) thinning the second surface of the substrate to expose the bottom of the substrate;
6) and the N-type heavily doped polysilicon layer is electrically connected with the grid electrode of the transistor through interconnection to form a floating gate structure.
9. The method according to claim 7 or 8, wherein the deep hole is etched by the following method:
1) forming a mask layer on the first surface of the substrate, and patterning the mask layer to form a plurality of openings;
2) and etching the substrate according to the opening on the mask layer to form a plurality of deep holes.
10. The method of claim 7 or 8, wherein the substrate is bonded to a secondary wafer prior to thinning of the substrate.
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| CN101789390A (en) * | 2009-01-23 | 2010-07-28 | 财团法人工业技术研究院 | Manufacturing method of silicon through hole and silicon through hole structure |
| CN102088014A (en) * | 2009-12-04 | 2011-06-08 | 中国科学院微电子研究所 | 3D integrated circuit structure, semiconductor device and forming method thereof |
| US9006102B2 (en) * | 2011-04-21 | 2015-04-14 | Globalfoundries Singapore Pte Ltd | Hybrid TSV and method for forming the same |
| CN103545275B (en) * | 2012-07-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole encapsulating structure and formation method |
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