SE9601777L - Process for manufacturing cavities under membrane, as well as a micromechanical component - Google Patents

Process for manufacturing cavities under membrane, as well as a micromechanical component

Info

Publication number
SE9601777L
SE9601777L SE9601777A SE9601777A SE9601777L SE 9601777 L SE9601777 L SE 9601777L SE 9601777 A SE9601777 A SE 9601777A SE 9601777 A SE9601777 A SE 9601777A SE 9601777 L SE9601777 L SE 9601777L
Authority
SE
Sweden
Prior art keywords
layer
substrate
holes
membrane
cover
Prior art date
Application number
SE9601777A
Other languages
Swedish (sv)
Other versions
SE9601777D0 (en
SE513072C2 (en
Inventor
Haakan Elderstig
Christian Vieider
Original Assignee
Imc Ind Mikroelektronikcentrum
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imc Ind Mikroelektronikcentrum filed Critical Imc Ind Mikroelektronikcentrum
Priority to SE9601777A priority Critical patent/SE513072C2/en
Publication of SE9601777D0 publication Critical patent/SE9601777D0/en
Publication of SE9601777L publication Critical patent/SE9601777L/en
Publication of SE513072C2 publication Critical patent/SE513072C2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Pressure Sensors (AREA)
  • Micromachines (AREA)

Abstract

Creating cavities in an etchable material beneath a membrane comprises depositing a mask layer onto a substrate, forming two or more holes in the mask layer, etching the substrate by bringing it into contact with an etching liquid in the mask holes and optionally sealing the resulting cavities. A monocrystalline silicon substrate (1) is used, onto which a sacrificial etchable material layer is applied to cover part of the substrate surface or come to lie within the substrate beneath this surface. A cover layer (4) is applied onto the substrate surface layer and covers the sacrificial layer too. A pattern of small holes (2) is etched into the cover layer and then an etching liquid that can etch away the sacrificial layer without etching the cover layer is applied via the holes in order to remove the sacrificial layer. Anisotropic silicon is applied onto the substrate through the resulting holes up to fill the cavity as far down as a crystal plane (9) in the monocrystalline silicon. A layer can be deposited over the substrate surface to cover the holes. An accelerometer comprising a monocrystalline silicon wafer substrate, a weight supported by a membrane and an indicator for measuring elongation in the membrane, is also claimed. The weight layer comprises boron-doped monocrystalline silicon. The membrane comprises a layer deposited onto the silicon substrate after part of it has been doped with boron and holes in the membrane allow a cavity to be etched in the silicon substrate beneath the weight layer. A cover layer is deposited to seal the holes and cavity. The indicator is deposited onto the cover layer to extend between an outer region of the membrane and part of the cover layer lying outside the cavity.
SE9601777A 1996-05-09 1996-05-09 Making micro-mechanical components, e.g. accelerometers SE513072C2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SE9601777A SE513072C2 (en) 1996-05-09 1996-05-09 Making micro-mechanical components, e.g. accelerometers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9601777A SE513072C2 (en) 1996-05-09 1996-05-09 Making micro-mechanical components, e.g. accelerometers

Publications (3)

Publication Number Publication Date
SE9601777D0 SE9601777D0 (en) 1996-05-09
SE9601777L true SE9601777L (en) 1997-11-10
SE513072C2 SE513072C2 (en) 2000-07-03

Family

ID=20402517

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9601777A SE513072C2 (en) 1996-05-09 1996-05-09 Making micro-mechanical components, e.g. accelerometers

Country Status (1)

Country Link
SE (1) SE513072C2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1130631A1 (en) 2000-02-29 2001-09-05 STMicroelectronics S.r.l. Process for forming a buried cavity in a semiconductor material wafer
US6825127B2 (en) * 2001-07-24 2004-11-30 Zarlink Semiconductor Inc. Micro-fluidic devices
US7045407B2 (en) * 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates

Also Published As

Publication number Publication date
SE9601777D0 (en) 1996-05-09
SE513072C2 (en) 2000-07-03

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Legal Events

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