SE9302158L - En extremt snabb adderaranordning - Google Patents

En extremt snabb adderaranordning

Info

Publication number
SE9302158L
SE9302158L SE9302158A SE9302158A SE9302158L SE 9302158 L SE9302158 L SE 9302158L SE 9302158 A SE9302158 A SE 9302158A SE 9302158 A SE9302158 A SE 9302158A SE 9302158 L SE9302158 L SE 9302158L
Authority
SE
Sweden
Prior art keywords
architecture
adder
new
clock
dblc
Prior art date
Application number
SE9302158A
Other languages
English (en)
Swedish (sv)
Other versions
SE9302158D0 (sv
Inventor
Jiren Yuan
Original Assignee
Jiren Yuan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiren Yuan filed Critical Jiren Yuan
Priority to SE9302158A priority Critical patent/SE9302158L/
Publication of SE9302158D0 publication Critical patent/SE9302158D0/xx
Priority to PCT/SE1994/000614 priority patent/WO1995000900A1/en
Priority to AU70896/94A priority patent/AU7089694A/en
Priority to EP94919952A priority patent/EP0705459A1/en
Publication of SE9302158L publication Critical patent/SE9302158L/

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3872—Precharge of output to prevent leakage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
SE9302158A 1993-06-22 1993-06-22 En extremt snabb adderaranordning SE9302158L (sv)

Priority Applications (4)

Application Number Priority Date Filing Date Title
SE9302158A SE9302158L (sv) 1993-06-22 1993-06-22 En extremt snabb adderaranordning
PCT/SE1994/000614 WO1995000900A1 (en) 1993-06-22 1994-06-21 An ultrafast adder arrangement
AU70896/94A AU7089694A (en) 1993-06-22 1994-06-21 An ultrafast adder arrangement
EP94919952A EP0705459A1 (en) 1993-06-22 1994-06-21 An ultrafast adder arrangement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9302158A SE9302158L (sv) 1993-06-22 1993-06-22 En extremt snabb adderaranordning

Publications (2)

Publication Number Publication Date
SE9302158D0 SE9302158D0 (sv) 1993-06-22
SE9302158L true SE9302158L (sv) 1994-12-23

Family

ID=20390377

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9302158A SE9302158L (sv) 1993-06-22 1993-06-22 En extremt snabb adderaranordning

Country Status (4)

Country Link
EP (1) EP0705459A1 ( )
AU (1) AU7089694A ( )
SE (1) SE9302158L ( )
WO (1) WO1995000900A1 ( )

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG79988A1 (en) * 1998-08-06 2001-04-17 Oki Techno Ct Singapore Pte Apparatus for binary addition
US6329838B1 (en) * 1999-03-09 2001-12-11 Kabushiki Kaisha Toshiba Logic circuits and carry-lookahead circuits
US6314507B1 (en) 1999-11-22 2001-11-06 John Doyle Address generation unit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956802A (en) * 1988-12-14 1990-09-11 Sun Microsystems, Inc. Method and apparatus for a parallel carry generation adder
US5166899A (en) * 1990-07-18 1992-11-24 Hewlett-Packard Company Lookahead adder
JPH056263A (ja) * 1991-06-27 1993-01-14 Nec Corp 加算器およびその加算器を用いた絶対値演算回路

Also Published As

Publication number Publication date
SE9302158D0 (sv) 1993-06-22
EP0705459A1 (en) 1996-04-10
WO1995000900A1 (en) 1995-01-05
AU7089694A (en) 1995-01-17

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