SE7602904L - Av flera delsystem bestaende databehandlingssystem - Google Patents

Av flera delsystem bestaende databehandlingssystem

Info

Publication number
SE7602904L
SE7602904L SE7602904A SE7602904A SE7602904L SE 7602904 L SE7602904 L SE 7602904L SE 7602904 A SE7602904 A SE 7602904A SE 7602904 A SE7602904 A SE 7602904A SE 7602904 L SE7602904 L SE 7602904L
Authority
SE
Sweden
Prior art keywords
data processing
processing systems
existing data
several subsystems
subsystems existing
Prior art date
Application number
SE7602904A
Other languages
Unknown language ( )
English (en)
Other versions
SE405517B (sv
Inventor
H Ruckdeschel
T Rambold
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19752517553 external-priority patent/DE2517553C3/de
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of SE7602904L publication Critical patent/SE7602904L/sv
Publication of SE405517B publication Critical patent/SE405517B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Dram (AREA)
  • Multi Processors (AREA)
  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
SE7602904A 1975-04-21 1976-02-27 Databehandlingssystem bestaende av flera delsystem SE405517B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752517553 DE2517553C3 (de) 1975-04-21 Datenverarbeitungssystem aus mehreren Teilsystemen

Publications (2)

Publication Number Publication Date
SE7602904L true SE7602904L (sv) 1976-10-22
SE405517B SE405517B (sv) 1978-12-11

Family

ID=5944546

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7602904A SE405517B (sv) 1975-04-21 1976-02-27 Databehandlingssystem bestaende av flera delsystem

Country Status (12)

Country Link
US (1) US4133029A (sv)
JP (1) JPS51130133A (sv)
AT (1) AT346915B (sv)
AU (1) AU500780B2 (sv)
BE (1) BE840957A (sv)
CH (1) CH608902A5 (sv)
FR (1) FR2308983A1 (sv)
GB (1) GB1542136A (sv)
IT (1) IT1059164B (sv)
NL (1) NL7603797A (sv)
SE (1) SE405517B (sv)
ZA (1) ZA761804B (sv)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491907A (en) * 1980-12-15 1985-01-01 Texas Instruments Incorporated Plurality of processors sharing the memory, the arithmetic logic unit and control circuitry all on a single semiconductor chip
US5768623A (en) * 1995-09-19 1998-06-16 International Business Machines Corporation System and method for sharing multiple storage arrays by dedicating adapters as primary controller and secondary controller for arrays reside in different host computers
US10684797B2 (en) * 2018-08-31 2020-06-16 Micron Technology, Inc. Command-in-pipeline counter for a memory device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3253262A (en) * 1960-12-30 1966-05-24 Bunker Ramo Data processing system
US3287705A (en) * 1963-03-07 1966-11-22 Rca Corp Computer system
US3302185A (en) * 1964-01-20 1967-01-31 Jr Andrew P Cox Flexible logic circuits for buffer memory
US3517174A (en) * 1965-11-16 1970-06-23 Ericsson Telefon Ab L M Method of localizing a fault in a system including at least two parallelly working computers
SE313849B (sv) * 1966-03-25 1969-08-25 Ericsson Telefon Ab L M
CH515557A (it) * 1969-06-21 1971-11-15 Olivetti & Co Spa Calcolatore elettronico
GB1268283A (en) * 1970-04-02 1972-03-29 Ibm Connect module
NL7007615A (sv) * 1970-05-27 1971-11-30
DE2027567A1 (de) * 1970-06-04 1971-12-09 Siemens Ag Speicher zur Zwischenspeicherung von Daten
US3678467A (en) * 1970-10-20 1972-07-18 Bell Telephone Labor Inc Multiprocessor with cooperative program execution
US3676861A (en) * 1970-12-30 1972-07-11 Honeywell Inf Systems Multiple mask registers for servicing interrupts in a multiprocessor system
NL7202501A (sv) * 1972-02-25 1973-08-28
GB1422952A (en) * 1972-06-03 1976-01-28 Plessey Co Ltd Data processing system fault diagnostic arrangements
US3964056A (en) * 1974-04-08 1976-06-15 International Standard Electric Corporation System for transferring data between central units and controlled units

Also Published As

Publication number Publication date
ATA150876A (de) 1978-04-15
DE2517553B2 (de) 1977-02-24
AU1241076A (en) 1977-09-29
SE405517B (sv) 1978-12-11
IT1059164B (it) 1982-05-31
JPS51130133A (en) 1976-11-12
AU500780B2 (en) 1979-05-31
CH608902A5 (sv) 1979-01-31
BE840957A (fr) 1976-10-21
NL7603797A (nl) 1976-10-25
GB1542136A (en) 1979-03-14
DE2517553A1 (de) 1976-11-04
ZA761804B (en) 1977-03-30
FR2308983A1 (fr) 1976-11-19
FR2308983B1 (sv) 1978-05-12
AT346915B (de) 1978-12-11
US4133029A (en) 1979-01-02

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