SE537214C2 - Functional encapsulation - Google Patents

Abstract

SUMMARY The invention relates to a semiconductor device comprising a semiconductor substrate and at least one passive electronic / electrical component integrated in the semiconductor substrate (6; 9). This integrated component has at least one functional part which extends through the substrate and has an extension in the plane of the substrate. Separately, the passive component consists of a capacitor and / or a coil.

Description

The present invention relates to the encapsulation of semiconductor devices and in particular to a roofing substrate which comprises functional parts.

Background of the invention In so-called encapsulation of semiconductor devices, it is sometimes required that various components be enclosed in a controlled atmosphere, ie. that a cavity is sealed in a controlled atmosphere, in some cases and even most often to form a hermetic seal. This procedure involves bonding two sheets together, often under pressure and with heating. This is a neat task when the discs are thin, as they are very law breaking & linder.

Representative prior art for this field of technology is WO 2007/089201, WO 2008/091220, WO 2008/091221, which describe various aspects of technology which include insulating silicon penetrations, such as silicon vias, through encapsulation to prevent overhorning between various ranges ("zero cross-talk") and micro-scale disk encapsulation of discrete or monolithically integrated components.

Summary of the Invention The present invention provides a method of manufacturing a semiconductor device comprising CMOS and / or MEMS components in a hermetically sealed cavity, without risk of damaging the overlying structure. It also provides integration of various types of electrical functionalities into the overhead structure, functionalities that are not process compatible with the temperature sensitive CMOS structures.

The method according to the invention is defined in claim 1.

The method involves the use of an SOI disk (Silicon On Insulator) to manufacture the overhanging structures, the vials being manufactured in the component layer, while maintaining the bar layer. This approach will ensure stability and robustness in the process and substantially reduce, if not completely eliminate, the risk of damaging the discs during manufacture.

Brief description of the drawings Fig. 1 shows in perspective view a device comprising the ideas of the invention; Fig. 2 illustrates details of the functional cover.

Detailed Description of the Invention The present invention is based on the inventive idea of using a method of making a metal wire substrate, i.e. a substrate having impedance-adapted through-going electrical connections of metal for RF applications, and in the same process sequence in the method optionally a set of passive components is manufactured, e.g. resistors, capacitors and / or inductors, which passive components extend through the substrate. Such a metal wire substrate is suitable for use in hermetic coating of CMOS or MEMS devices, e.g. CMOS structures including switches.

The invention can be used to manufacture a single transmitter / receiver chip integrated with switches and RCL filters which filter out the correct frequency and which switch to the antenna in the mobile telephone or to the receiving chip. Providing such an RF switch allows the choice of which band (frequency) one wishes to use; 900 MHz (GSM), 1800 or 1900 MHz (3G in Europe and the USA respectively), 2800 MHz for Bluetooth and the various WLAN standards.

Fig. 1 is a cross-sectional perspective view of a functionally covering substrate, i.e. before it has been bonded to a CMS and / or MEMS device disk.

It generally comprises a roofing substrate 1, i.e. a tacking structure for encapsulation, mandatory hermetic sealing, CMOS or MEMS structures 2 (indicated below the roofing substrate). 2 537 214 Taek substrate I, Typically made of arc resistive silicon, although other materials are possible, comprises several functional components. Some companies have arranged relatively wide depressions R in order to provide spaces in which the CMOS / IVENS components are to be operated in a controlled atmosphere when the covering structure is bonded to a component board, Don pri, but functional detaben providing so-called via structures, generally referred to as 3. 10 In the most general form, the metal wire is a simple via, i.e., only a metal "plug", which extends through the substrate.

In RF applications, these coils are suitably made as coaxial electrical couplings which extend through the substrate and thereby achieve impodance measurement. a thin insulating layer of tex .. oxide arranged indian metal and sheet material. At a radial distance, an annular metal structure is provided which thus encloses the central "metal plug". Donna annular metal structure is also preferably insulated against the sheet material with thin insulating layers at both the inner and outer circuit. The annular metal structure forms a screen, and together these structures form a coaxial redirecting connection, which imparts impedance-fed properties to RF signals. Some embodiments of the coaxial connections ('Osacle in Fig. I)) comprise the central "plug" itself a central portion. 4 of a material that is compatible with the material in the board frArt from which the substrate is manufactured, Lex. oxide (TEOS) or polycycle.1 30 (or any other material which has a coefficient of expansion equal to the sheet material from which the substrate is made). This central portion is surrounded by the metal 4 '1. an annular current through which electrical signals can be transmitted. In this case, ie the "plug" is a composite structure. 3 537 214 For very small dimensions, the central plug can be made entirely of metal, ie there is no void created during manufacture which is then filled, but the metal will fill the vial completely during manufacture.

Metal metal and substrate materials in the respective structures there is a thin oxide layer (not shown) to electrically insulate from the silicon in the substrate 1.

Furthermore, a structure 5, 5 'is arranged concentrically around and at a radial distance from the insulated metal wire 4. Between via 4 and this structure 5, 5' there is an annular silicon portion 4 "surrounding the metal wire 4 '. The concentric structure is indicated by broken lines at 5 ".

The concentric structures 5, 5 'comprise two concentric, annular metal structures 5', between which (ie at 5) the same material is arranged as in the central portion 4, i.e. oxy (eg TEOS) or polysilicon (or any other material having a coefficient of expansion similar to the sheet material of which the substrate is made).

The annular metal structure 5 'will act as a shield for the centrally coated wire 4. Properly designed, the impedance in such a structure will be 50 Ohms, which allows RF signals to be transmitted in the metal wire with minimal reflection and damping.

The overall structure will be a coaxial coupling between the two sides of the Overcoating substrate 1, thereby forming an ohmic coupling between the MEMS / CMOS devices through the Overcoating substrate to the external devices.

Another functional feature of the roofing substrate may be the arrangement of a capacitor structure 6 within the substrate. Such a capacitor structure is provided by arranging a metal in thin segments 7 (six are shown in Fig. 1), which preferably extends the entire path through the substrate and also extends to the plane of the Wars Over substrate). If such segments are arranged next to each other and in parallel as shown in Fig. 1, with only a very small intrusion between them, the material segments 8 in the substrate will melt these insulating elements to have the function of corridor capacitor plates.

Another functional part of the scan shown in Fig. 1, at least 9, is the arrangement of a structure which forms a coil to provide. and inclusion.

The inductance includes the On Metals. E: for example, provided by Ni or preferably a Ni / Q alloy, which the fibers preferably extend through the thickness of the substrate and have an elongated shape, the soul extending substantially in the plane of the substrate. Furthermore, a winding is arranged around the kthtian consisting of a combinatorial tint). ay OP set viastructures 11, arranged in two-dimensional. matrices (array) kings metal core and which & tracker itself groom substrate, () eh arranged on rear sides of the curry 10, and metal strips 12, .sorn & - connect via the structures 11 in pairs tVars Over the core 10. (-know. to charge it first, on one side 4.in the core and on the lower surface of the substrate (seen in the figure) adjoin a resistor via arranged on the other side of the core and then connect this resistor via on the bottom side of: the substrate (seen in the figure) with an adjacent via to the first .20 mentioned wire, etc., i.e., to provide a substantially zigzag connection between a helical conductor provided around the metal core and on this salt an inductance is provided.

Fig. 1 shows a double row of wires arranged in a zigzag configuration. This allows the metal strips to be placed closer together, since the strips can be made narrower on the diameter of the wires themselves. In this way, the number on the winding can vary significantly and the properties of the inductance can be adjusted to a greater extent.

The trionolytically integrated capacitor () and inductance parts can be used to replace discrete assemblies. For example, parallel "trenches" (suitably with DRIE; Deep Reactive Ion Etching) are etched in order to fabricate capacitors and to fabricate the inductors' cores, and hal are etched to provide via structures. The trenches and tail are etched down to the insulating stop bearing. In this way, selected trenches and halls are obtained.

The entire board is then oxidized to provide a thin (approx. 0.5 .mu.m) insulating layer on the board and in all halls and trenches. A saddle bearing of conductive material, such as metal, e.g. Cu or Au, are arranged, for example, by sputtering, evaporation or plating, or plasma-reinforced polysilicon to facilitate subsequent metallization, e.g. by electroplating or electroless metal precipitation.

The next step is to manufacture the core for the inductance, if one is obscured.

For this purpose, the entire disc is masked and sampled to expose only the trenches for the manufacture of the karnan. The masking can be done by thanking the entire ski van with a film or by spinning a resist on the disc. The mask is opened up over the trenches that will form the inductance core. Electroplating is used to fill the trenches with the desired metal. Preferably anyands a Ni / Co alloy for this purpose. 6 537 214 Then the disk is masked and sampled as described above to expose the remaining structures, i.e. trenches for capacitor plates and for via structures. Anyo plating is used to wax Au, CU or Al to a thickness of at least nd.gra fa pm with low resistivity. This will in most cases leave a void inside the tail / trenches.

Preferably, but optionally, these rum cavities are filled with a material that is compatible with the substrate sheet material in terms of coefficient of expansion, so that thermal action does not cause the substrate to crack.

Suitable materials for filling are oxide (eg TEOS) or polysilicon.

In a particularly preferred embodiment of the invention, routing structures are manufactured, i.e. structural elements for interconnecting components on the substrate, in the same process sequence as described above. Sadana routing structures are narrow strips of metal.

There are two alternative procedures for manufacturing these routing structures.

In one embodiment, the initial step of sampling and etching the trenches and tail is divided into two sub-steps. First, the disk is sampled to define the routing structures and the disk is subjected to an etching to a depth of only a few microns. In this case, shallow grooves or recesses in the surface are provided. The disk is then resampled to provide the trenches and tail, as described above.

The scale of using this sequence is that it would be more appropriate to spin resist on the more complicated topography provided by the deep trenches and tail, although the latter is possible. When the metal is deposited on the substrate, the grooves will be completely filled with metal and form conductive strips. In this way, the routing structures will be provided so that they are suspect, ie. they will be arranged in the surface of the substrate rather than on it. In an alternative embodiment, the routing structure is provided after the other structures have been fabricated. In this case, the entire disk is sampled after the final step of filling the voids (if this is performed) to define the routing structures. Metal is deposited on the disc in the openings in the sample. In this alternative, the routing structures are provided on the surface of the substrate.

These methods of manufacturing routing structures are also suitable for providing the metal strips that form an integral part of the winding (ph the side 10 of the substrate constituting the component layer) to the inductance as described above.

The metal strips for the inductance ph opposite side of the substrate are manufactured after the overlying substrate has been bonded to the CMOS / MEMS board and will be described below.

In order to enable a thermocompression bonding of the covering substrate on a CMOS / MEMS device, it may be required to provide a metallization 20 running along the circumference around the surface defining the final mending, corresponding to a matching metallization on the CMOS / MEMS device.

Such metallization is preferably Au or Cu.

It is also possible with different eutectic bonding methods, e.g. Au / polysilicon, AuSN / AU or many other eutectic alloys which are the choice of the person skilled in the art.

Another preferred feature of the invention is not to actually stop etching at the etch stop layer in the SOI wafer when the handles and trenches are made in the initial stage of the process without actually continuing to etch further into the stop bearing. It is also possible to completely etch through the stop bearing.

The advantage of this is that when the carrier layer is finally removed, the metal deposited in the viahAlen will be exposed and can form contact surfaces without any need for further processing, such as sampling and etching, to expose the metal. The exposed metal can then be plated directly or otherwise processed to provide pads 22 for electrically coupling the CMOS / MEMS components to the wire.

When all the desired functions and components have been manufactured in the component layer on the SOI board, the whole board is patterned again to define the further depressions R which are to provide the hermetically sealed spaces with a controlled atmosphere. Appropriate etching to a desired depth will result in appropriately hermetically sealed spaces.

At this stage, the overlay substrate is still provided with the SOI disk handle layer. Now it must be bonded to the CMOS / MEMS substrate 2. For this purpose, the circumferential metallizations are matched and pressed against each other, forming a hermetically sealed seal, either by thermocompression or by eutectic narrow bonding.

After the overlapping structure and the CMOS / MEMS device are bonded together, the handle layer is deposited in a conventional manner, e.g. by grinding or etching or any other method which is \ radicand to the person skilled in the art.

As already indicated, if the tail and trench etching are challenged by the insulator layer of the SOI board, the metal deposited in the tail and the trenches will be exposed and form suitable contact points to provide connection surfaces for further connection. At this stage is also manufactured. routing on the back in a similar way as already described above.

It should be noted that cross-coupling of metal strips belonging to the inductance is now manufactured, apparently at the same time as the other routing structures. By manufacturing solder balls 28 of solderable material (eg Ni / Au), surface mounting becomes possible, for example flip-chip type mounting.

The inductance functionality described above can also be provided in other ways. For example, such structures could also comprise a thin, 9,537,214 insulating segment, i.e. a filled trench, which extends through the substrate but which runs in a helical sample to form an inductance coil.

In a further preferred embodiment, insulating enclosures 26 may be provided surrounding selected elements of the roofing substrate. Such insulating enclosures prevent crosstalk between components and regions, thereby minimizing signal strength losses. Methods for manufacturing such inclusions are described in the applicant's own international patent application, WO 2008/091220. 10

Claims (4)

537 214 PATENT CLAIMS: A passive electrical component (6; 9) integrated in a roofing substrate, wherein the integrated component is an inductance, and comprises a coil consisting of a combination of a set of viastructures (11), arranged in two-dimensional matrices ( arrays) and extending through the substrate, and metal strips (12) interconnecting the vias structures (11) in pairs where a via on the upper surface of the substrate is connected to an opposite via and this opposite via on the bottom side of the substrate is connected by an adjacent via to the first mentioned vian, said that there is a substantially zigzagging connection between vior, whereby a spirally wound conductor is present. A passive component according to claim 1, wherein the inductance (9) comprises a metal core (10) which the cores preferably extend through the thickness of the substrate and have an elongate shape which extends substantially in the plane of the substrate. A passive component according to claim 2, wherein the core comprises Ni, preferably a Ni / Co alloy. Passive component according to any one of the preceding claims, comprising two, three or four rows of vias. 11 537 214 1/2 Co c \ I 537 214 2/2