SE1150413A1 - Functional encapsulation - Google Patents

Abstract

SUMMARY The invention relates to a semiconductor device comprising a semiconductor substrate and at least one passive, electronic / electrical component integrated in the semiconductor substrate (6; 9). This integrated component has at least one functional part which extends through the substrate and has an extension in the plane of the substrate. Separately, the passive component consists of a capacitor and / or a coil.

Description

FUNCTIONAL ENCLOSURE The present winding refers to the encapsulation of semiconductor devices and in particular a roofing substrate which comprises functional parts.

Background of the invention In so-called encapsulation of semiconductor devices, it is sometimes required that various components be enclosed in a controlled atmosphere, ie. that a cavity is sealed in a controlled atmosphere, in some cases and even usually allowed to form a hermetic seal.

This procedure involves bonding two discs together, often under pressure and with heating. This is a tricky task when the discs are thin, as they are very easily broken.

Representative prior art for this field of technology is WO 2007/089201, WO 2008/091220, WO 2008/091221, which describe various aspects of technology which include insulating silicon penetrations, such as silicon vias, TSH, to prevent overhorning between different areas ("zero cross-talk") and enclosure on a micro-scale disk level of discrete or monolithically integrated components.

Summary of the Invention The present invention provides a method of manufacturing a semiconductor device comprising CMOS and / or MEMS components in a hermetically sealed cavity, without risk of damaging the overlying structure. It also provides integration of different types of electrical functionalities into the overhead structure, functionalities that are not process compatible with the temperature sensitive CMOS structures.

The method according to the invention is defined in claim 1.

The method involves the use of an SOI disk (Silicon On Insulator) to manufacture the overhanging structures, the vials being manufactured in the component layer, while maintaining the bar layer. This approach will ensure stability 2 and robustness in the process and substantially reduce, if not completely eliminate, the risk of damaging the discs during manufacture.

Brief description of the drawings Fig. 1 shows in perspective view a device comprising the ideas of the invention; Fig. 2 illustrates details of the functional cover.

Detailed Description of the Invention The present invention is based on the inventive idea of using a method of making a metal wire substrate, i.e. a substrate carrying impedance-matched continuous electrical connections of metal for RF applications, and in the same process sequence in the method optionally a set of passive components is manufactured, e.g. resistors, capacitors and / or inductors, which passive components extend through the substrate. Such a metal wire substrate is suitable for use in hermetic roofing of CMOS or MEMS devices, e.g. CMOS structures including switches.

The invention can be used to manufacture a single transmitter / receiver chip integrated with switches and RCL filters which filter out the correct frequency and which switch to the antenna in the mobile telephone or to the receiving chip. Providing such an RF switch allows the choice of which band (frequency) one wishes to use; 900 MHz (GSM), 1800 or 1900 MHz (3G in Europe and the USA respectively), 2800 MHz for Bluetooth and the various WLAN standards.

Fig. 1 is a cross-sectional perspective view of a functionally covering substrate, i.e. before it was bonded to a CMS and / or MEMS device disk.

It generally comprises a roofing substrate 1, i.e. a tacking structure for encapsulation, mandatory hermetic sealing, CMOS or MEMS structures 2 (indicated below the roofing substrate).

The teak substrate 1, suitably made of high-resistive silicon, also other materials may contain several functional components. There are also relatively wide depressions R for all associated spaces in which the CMOS / MEMS components can be operated in a controlled atmosphere when the Overlay structure is bonded to a component board.

Their primary functional detail is the provision of so-called via structures, generally referred to as 3. In the most general form, the metal vian is a single via, i.e., only a metal "plug," extending through the substrate.

For RF applications, these wires are suitably made as coaxial electrical couplings extending through the substrate and thereby achieving impedance matching, a further embodiment comprising such coaxial wires on "metal plugs" extending through a disc with: a thin insulating layer of tex .. oxide arranged between the metal and the sheet material., P0 a radial distance firms arranged a ring-shaped metal structure corn sahmda inneshrter don eentrala. "meta-plugs". Donna annular metal structure Or: also widely insulated, against the sheet material against thin ,. insulating layer by bath don hire cell the outer orn circle. The annular metal structure forms a screen, () eh together these structures form a ho - axial genorrigaeride connection, son ?, JilbandatiAlior impedance-matched properties 25.for RF signals. The embodiments of the coaxial joints (shown in Fig. 1) comprise the central plugs: "itself an integral portion. 4 of a material which is compatible with the material of the disc from which the substrate is made, lox. oxide in (TFOS) oiler polysilicon 30 feller any other material having a similar expansion, coefficient corn sheet material film from which the substrate is made). This central portion is formed by the metal 4 'an annular strulaur, genora.which electrical signals can be transmitted. In this fail is salundo. " . "a composite structure. 4 For very small dimensions, the central plug can be made entirely and the hall of metal, ie there is no void created during manufacture which is then filled, but the metal will fill the gap completely during manufacture.

Metal metal and substrate materials in the respective structures there is a thin oxide layer (not shown) to electrically insulate from the silicon in the substrate 1.

Furthermore, a structure 5, 5 'is arranged concentrically around and at a radial distance from the insulated metal wire 4. Between via 4 and this structure 5, 5' there is an annular silicon portion 4 "surrounding the metal wire 4 '. The concentric structure is indicated by broken lines at 5 ".

The concentric structures 5, 5 'comprise two concentric, annular metal structures 5', between which (ie at 5) the same material is arranged as in the central portion 4, i.e. oxy (eg TEOS) or polysilicon (or any other material having a coefficient of expansion similar to the sheet material of which the substrate is made).

The annular metal structure 5 'will function as a shield for the centrally coated wire 4. Properly designed, the impedance in such a structure will be 50 Ohms, which allows RF signals to be transmitted in the metal wire with minimal reflection and damping.

The overall structure will be a coaxial coupling between the two sides of the Overcoating substrate 1, thereby forming an ohmic coupling between the MEMS / CMOS devices through the overcoating substrate to the external devices.

Another functional feature of the roofing substrate may be the arrangement of a capacitor structure 6 within the substrate. Such a capacitor structure is provided by arranging a metal in thin segments 7 (six are shown in Fig. 1), which preferably extends the whole path through the substrate and also6. stretcher: across the plane of the substrate). If several such segments are arranged next to each other and in parallel as shown in Fig. 1, with only a very small space between them, the material segments 8 in the substrate between these insulating elements corrode to have the function of capacitor plates.

A further functional part shown in Fig. 1, alinin at 9, is the arrangement of a structure which forms a coil to provide an inductance.

The inductance comprises a metal core. For example made of Ni or preferably a Ni / CO alloy, which the cores preferably extend through the thickness of the substrate orb had an elongated shape which extends substantially in the plane of the substrate. Furthermore, a winding is arranged around the core consisting of a combination of a set of vias structures 11, arranged in two-dimensional ways. arrays along the metal core and extending through the substrate, () arranged on rear sides of the core 10, and metal strips 12, which connect via the structures 11 in pairs across the core 10. By charging the first via the side of the core and on the upper surface of the substrate (seen in the figure) connect to an opposite via arranged on al-1 (3rd side of the core and then connect the opposite via on the bottom side of the substrate (seen in the figure) tried an adjacent via to the first 20 narcissistic wire, etc., i.e., provide a substantially zigzag connection between the wire, attached to a so-called helically wound conductor around the metal core and on, (Jetta salt creates an inductance.

Fig. 1 shows a double row of wires scarred in a zigzag configuration. This is because the metal strips are placed closer together, since the strips can be narrower than the diatneter. themselves. viorna .. Del is possible to arrange triple or quadruple windows of vior. In the eight ways, the number of variations on the winding can increase significantly ooh. the properties of the inductance can be tailored to a higher extent.

The monolithically integrated capacitor-orb inductor parts can be used to replace discreetly mounted Is: o porters. With the use of high-direction conductors, inductors or resistors, various breeding or lettering functions can be integrated. Now, a preferred process for manufacturing a roofing substrate as described above and including optional functionalities will be described. The process utilizes a so-called SOI disk as a starting substrate. An SOI disk has a relatively thin so-called component layer, in which processing is performed, and a much thinner bar layer, to facilitate handling of the disc. This bar layer is then removed.

A first step in a general process according to the invention is to sample the component bearings of the SOT board as required to manufacture the components. For example, parallel "trenches" (aptly with DRIE; Deep Reactive Ion Etching) are etched in order to fabricate capacitors and to fabricate the inductors' cores, and hal are etched to provide via structures. The trenches and tail are etched down to the insulating stop bearing. In this way, selected trenches and halls are obtained.

The entire board is then oxidized to provide a thin (approx. 0.5 .mu.m) insulating layer on the board and in all halls and trenches. A saddle bearing of conductive material, such as metal, e.g. Cu or Au, are arranged, for example, by sputtering, evaporation or plating, or plasma-reinforced polysilicon to facilitate subsequent metallization, e.g. by electroplating or strOmlOs metal precipitation.

Lampligen dr next step to manufacture the karnan for the inductance, if such is onskyard.

For this purpose, the entire disc is masked and sampled to expose only the trenches for the manufacture of the karnan. The masking can be done by thanking the whole ski van with a film or by spinning a resist on the disc. The mask opens up over the trenches that will form the inductance core. Electroplating is used to fill the trenches with the desired metal. Preferably a Ni / Co alloy was used for this andama.l. 7 The disk is then masked and sampled as described above to expose the remaining structures, i.e. trenches for capacitor plates and for via structures. Anyo plating is used to wax Au, CU or Al to a thickness of at least a few pm with low resistivity. This will in most cases leave a void inside the tail / trenches.

Preferably, but optionally, these voids are filled with a material that is compatible with the substrate sheet material in terms of coefficient of expansion, so that thermal action does not cause the substrate to crack.

Suitable materials for filling with oxide (eg TEOS) or polysilicon.

In a particularly preferred embodiment of the invention, routing structures are manufactured, i.e. structural elements for interconnecting components on the substrate, in the same process sequence as described above. Sadana routing structures are narrow strips of metal.

There are two alternative procedures for manufacturing these routing structures.

In one embodiment, the initial step of sampling and etching the trenches and tail is divided into two sub-steps. First, the disk is sampled to define the routing structures and the disk is subjected to an etching to a depth of only a few. pm. In this case, shallow grooves or recesses in the surface are provided. The board is then re-patterned to provide the trenches and tail, as described above.

The reason for using this sequence is that it would be more appropriate to spin resist on the more complicated topography provided by the deep trenches and the Mien, although the latter is possible.

When the metal is deposited on the substrate, the grooves will be completely filled with metal and form conductive strips. On this salt, the routing structures will be provided so that they Or are submerged, ie. they will be arranged in the surface of the substrate rather On it. In an alternative embodiment, the routing structure is provided after the other structures have been fabricated. In this case, the entire disk is sampled after the final step of filling the voids (if performed) to define the routing structures. Metal is deposited on the disk in the openings in the monster. In this alternative, the routing structures are provided on the surface of the substrate.

These methods of manufacturing routing structures are also suitable for providing the metal strips which form an integral part of the winding (on the side of the substrate constituting the component layer) to the inductance as described above.

The metal strips for the inductance on the opposite side of the substrate are manufactured after the overlying substrate has been bonded to the CMOS / MEMS board and will be described below.

In order to enable a thermocompression bonding of the covering substrate on a CMOS / MEMS device, it may be required to provide a metallization which runs along the circumference around the surface defining the final device, corresponding to a matching metallization on the CMOS / MEMS device.

Such metallization is preferably Au or Cu.

It is also possible with different eutectic bonding methods, e.g. Au / polysilicon, AuSN / AU or many other eutectic alloys that are elective to those skilled in the art.

A further preferred feature of the invention is not to actually stop etching flake at the etch stop layer in the SOI sheet when the tail and trenches are made in the initial stage of the process without actually continuing to etch further into the stop layer. It is also possible to completely etch through the stop bearing.

The advantage of this is that when the carrier layer is finally deposited, the metal deposited in the via tail will be exposed and can form contact surfaces without any need for further processing, such as sampling and etching, to expose the metal. The exposed metal can then be plated directly or otherwise processed to provide pads 22 for electrically coupling the CMOS / MEMS components to the wire.

When all the desired functions and components have been manufactured in the component layer of the SOI board, the whole board is sampled again to define the further depressions R which are to provide the hermetically sealed spaces with a controlled atmosphere. Appropriate etching to a desired depth will result in appropriately hermetically sealed spaces.

At this stage, the Overcoat substrate is still provided with the SOI disk handle layer. Now it is to be bonded to the CMOS / MEMS substrate 2. For this purpose, the circumferences of the traps are matched to the metallizations and pressed against each other, forming a hermetically sealed seal, either by thermocompression or by eutectic narrow bonding.

After the overlapping structure and the CMOS / MEMS device are bonded together, the handle layer is deposited in a conventional manner, e.g. by grinding or etching or flaking another method which is optional for the person skilled in the art.

As already indicated, if the tail and trench etching are challenged by the insulator layer of the SOI board, the metal deposited in the tail and the trenches will be exposed and form suitable contact points to provide connection surfaces for further connection. At this stage, routing on the back is also manufactured in a similar manner as already described above.

It should be noted that cross-coupling of metal strips belonging to the inductance is now manufactured, apparently at the same time as the other routing structures. By manufacturing solder balls 28 of solderable material (eg Ni / Au), surface mounting becomes possible, for example flip-chip type mounting.

The inductance functionality described above can also be provided in other ways. For example, such structures could also include a thin, insulating segment, i.e. a filled trench which extends through the substrate but which runs in a helical sample to form an inductance coil.

In a further preferred embodiment, insulating enclosures 26 may be provided surrounding selected elements of the roofing substrate. Such insulating enclosures prevent crosstalk between components and regions, thereby minimizing signal strength losses. Methods for manufacturing such inclusions are described in the applicant's own international patent application, WO 2008/091220. 11

Claims (15)

CLAIMS: A semiconductor device comprising a semiconductor substrate and at least one passive electronic / electrical component (6; 9) integrated in the semiconductor substrate, the integrated component having at least one functional part extending through the substrate and extending in the plane of the substrate. A semiconductor device according to claim 1, wherein the passive component is a capacitor structure (6). A semiconductor device according to claim 2, wherein the capacitor is provided by the presence of metal in thin segments (7), which preferably extend the entire path through the substrate and also extend transversely across the plane of the substrate. A semiconductor device according to claim 3, wherein the segments (7) are arranged next to each other and in parallel, with only a very small space between them, the segments (7) having the function of capacitor plates. The semiconductor device according to claim 1, wherein the passive component is an inductance (9). A semiconductor device according to claim 5, wherein the inductance (9) comprises a metal core (10) which the cores preferably extend through the thickness of the substrate and have an elongate shape which extends substantially in the plane of the substrate. The semiconductor device according to claim 6, wherein the core comprises Ni, preferably a Ni / Co alloy. The semiconductor device according to claim 7, further comprising a winding around the core consisting of a combination of a set of via structures (11), arranged in two-dimensional matrices (arrays) along the metal core (10) and extending through the substrate, and arranged on rear sides of the core (10), and metal strips (12) connecting the viastructures (11) in pairs across the core (10). A semiconductor device according to claim 7, wherein the first wire on one side of the core (10) and on the upper surface of the substrate is connected to a resistor via a device on the other side of the core (10) and this resistor via the bottom side of the substrate is connected to an adjacent via to the first-mentioned wire, so that an essentially zigzagging connection between wire is provided, whereby a spirally wound conductor around the metal core is present. A semiconductor device according to claim 9, comprising double, triple or quadruple rows of vias. A method of manufacturing a passive functional component in a substrate, said component comprising a functional member extending through the substrate and extending in the plane of the substrate, the method comprising the steps of: providing an SOI disk with a component layer, a carrier layer and a stop layer between the component layer and the carrier layer, as a starting substrate; sampling the component layer of the SOI disk to define the desired components; etching of trenches down to the stop bearing; oxidation of the entire board providing a thin insulating layer on the board and in all halls and trenches; depositing a seed layer of conductive material to facilitate subsequent metallization, 13 masking of the entire disk and sampling to expose only the trenches; metallization to fill the trenches with damaged metal; removal of the bar stock. A method according to claim 11, wherein the oxidation is Ors to a thickness of about 0.5 μm. A method according to claim 11, wherein the metallization takes place by electroplating or electroless metal precipitation, preferably using a Ni / Co alloy. A method according to claim 11, wherein the masking for exposure of the trenches is done by tacking the whole disc with a film or by spinning a resist on the disc. Method according to claim 11, wherein removal of the bar layer Ors by grinding or etching. 23 Z'6! J