SE513947C2 - Control method for ferroelectric liquid crystal display (FLCD), by simultaneous addressing of selection electrodes under control window with parallel selection pulse sequences - Google Patents

Abstract

Sequences of data pulses are supplied parallel to data electrodes in response to data to be written into pixels, selection pulse sequence is generated on cyclic basis for each selection electrode. Selection electrodes are addressed one at a time as sub-sets under control window. Each sub-set represents number (P) of selection electrodes greater than or equal to 2, so that all of P in given addressed sub-set are addressed simultaneously under associated control window via parallel application of P different selection pulse sequences. The selection pulse sequence comprises a selection pulse, an erasure pulse and a writing pulse. The selection pulses are located inside a control window for addressing the selection electrodes, with data pulses being applied to each data electrode under this window, resulting in each pixel associated with the selection electrode and a data electrode generating a control pulse in response to a voltage difference applied across the pixels under the control window. The erasure pulse is located in front of the control window and is used to drive all the pixels in the selection electrode in a direction towards a given first optical state in front of the control window. The writing pulse is at least partly located outside the control window, with the control pulse applied over a given pixel determining to what extent the already driven pixel will be shifted to a second optical state. An Independent claim is also included for the use of a decoupling control pulse for carrying out a time-multiplexed, rapid multi-line addressing of an FLCD, using this control method.

Description

crystalline materials and / or (ii) use faster addressing methods.

(LCD) in the prior art, control electrodes are normally arranged in a rectangular matrix or grid of intersecting lines (rows and columns) in a typical liquid crystal display. The areas where row and column electrodes intersect or overlap define a plurality of pixels, called pixels. All pixels in a given row thus have a row electrode in common. Similarly, all the pixels in a given column have one column electrode in common. The electric voltage or electric field generated across the liquid crystal material within a given pixel is equal to the voltage difference between the voltage signals applied to the two electrodes associated with the pixel. This electric voltage or field is the parameter which in turn controls the switching of the pixels between their different electro-optical states. The switching is more specifically controlled by (i) the duration of the applied voltage and (ii) the amplitude of the applied voltage.

The addressing of a ferroelectric liquid crystal display is traditionally performed by scanning the rows line by line using selection pulse sequences, while applying a flow of data pulse sequences in parallel to all columns. During a time window called a Control Window (CW), all the pixels in a selected row receive their data in the form of data pulses, which are included in said data pulse sequences.

The selection pulse sequences applied to the selection electrodes are mutually identical except for a phase layer which is equal to the length or width of the control window. The data pulse received during the control window, together with the selection pulse sequence, forms an electric control field applied over the pixel, which determines whether the final state of the pixel should be either light (ON) or dark (OFF). however, the process itself does not necessarily have to have the ferroelectric switching completed under the control window. The length or width of the control window is called the addressing time.

Fig. 1 schematically shows on the right a typical electrode array 10 of an LCD, comprising a plurality of row or selection electrodes 20 and M column or data electrodes 30. Fig. 1 also shows on the left the phase layer between the different control windows CW of selection pulse sequences 21 for providing a time-multiplexed addressing of a row 20 at a time, by applying the selection pulse sequences 21 to the selection electrodes 20. Thus, an image is created by scanning the selection electrodes 20 line by line by applying said selection pulse sequences while data pulse sequences 31 app The control window CW sequences 21, is licensed to all the data electrodes 30. for a given line 20 is defined as the period of time during which the data for all the pixels P in a given line 20 receives its data or its data pulses via the data electrodes 30.

An SSFLC cell exhibits bistability as well as a polar (ferroelectric) field. The threshold value for switching between the two electrical responses to an applied external electrically optical state is related to the surface of the voltage pulse. In the early addressing methods (around 1985), the write pulse and all required DC compensation were inside the CW control window. As a result, the line addressing time became several times longer than the liquid crystal cell's own switching time. It was soon realized that the control window could be shortened if you deleted the pixel to a state. Later, you also moved part of the actual writing pulse (for example OFF) before addressing it. outside the control window, whereby line addressing times in the same order of magnitude as the own switching time of the ferroelectric liquid crystal material were achieved.

Subsequently, further speed improvements for SSFLC displays were achieved through the introduction of so-called fast addressing modes, as described in, for example, Advances and 10 15 20 25 30 35 513 947 4 problems in the development of ferroelectric liquid crystal displays. ", Mol.

Pp. 57-72, 1992). addressing techniques based on the fact that even Cryst. Liq. Cryst., Volume 215, According to this document, if the primary or ferroelectric switching is controlled (-E), the ferroelectric domains within the ferroelectric of a ferroelectric moment acting on those material, then a dielectric moment (~ E2) can counteract the ferroelectric the switching in its initial phase and stabilize / accelerate this in its final stage. By controlling the ferroelectric torque at the dielectric moment, the RMS (root-mean-square) switching process that takes place during the write pulse can be varied, even if the magnitude of the write pulse itself is kept constant. In the fast addressing technique, therefore, the write pulse can be output from the control window, so that the line addressing time is reduced to only a fraction of the ferroelectric liquid crystal material's own switching time.

An example of an addressing technique or method that uses the above-described dielectric response of a (the so-called "Split Writing" method is PLC material in the initial phase of the switch "Hold Back" technique) (SW). This prior art is described in, for example, WO95 / 23402 (inventor P. Maltese).

Fig. 3A schematically shows a selection pulse sequence 21 for such a known "Split Writing" method using the "Hold Back" effect of a switching control pulse 22 (hereinafter the selection pulse 22 hereinafter) within the control window CW. A sufficiently long erasing pulse 23 with a first polarity (located in front of the control window CW, causes all the pixels of the row - through its ferrous - to a state (say OFF). This erasing operation is followed by a pause period 24, electrical response - "erased" so that one then follows the control window CW and a write pulse 25 with a polarity opposite to the polarity of the erasure pulse 23. The data sequences 31 applied under the control window to the data electrodes are not shown in Fig. 3A.

The selection pulse sequence 21 for erasing and writing causes a DC shift on the LC material. In order to avoid a long-term switching effect and thus a deterioration of the LC material, a DC compensation pulse 26 has been introduced before the erasing pulse 23. If this DC compensation pulse 26 is long enough, it can switch all the pixels in the associated row to ON the state before the erasing pulse 23 begins.

In accordance with the traditional addressing techniques described above, data pulse sequences are applied in parallel to the data electrodes below the control window CW.

More specifically, each data pulse sequence is constructed by using two different data pulses to control the pixels between the ON state and the OFF state.

(ON) and which are used in combination with the selection pulse 32-1 32-2 (OFF), selection pulse 22 which is included in the selection pulse sequence 21 in Fig. 3A. The first data pulse 32-1 is applied to switch the pixel to the ON state, while the second data pulse 32-2 is applied to switch the pixel to the OFF state. data pulses 32-1 and 32-2, each pixel has been erased to Before receiving either of these two OFF states of the erasure pulse 23 shown in Fig. 3A.

The two boxes at the bottom right of Fig. 3B show two different resulting control pulses 41-1 and 41-2, corresponding to the voltage difference applied across the pixel when it is driven to the ON state and the OFF state, respectively. It is important to note that the ON control pulse 41-1 has a relatively low RMS value, whereas the OFF control pulse 41-2 has a relatively high RMS value. According to Maltese, the low RMS value of the ON control pulse 41-1 will not counteract a switching of the pixel from the OFF state, and therefore the pixel will be switched to the ON state of the subsequent write pulse 25 (not shown in Figs. 3B). The high RMS value of the OFF control pulse 41-2 10 15 20 25 30 35 513 947 6, on the other hand, will counteract any switching of the subsequent write pulse 25, and therefore the pixel will be retained in the OFF state previously produced. - come with the erase pulse 23.

As shown in Figs. 3A and 3B, the selection pulse 22 in the control window CW has four time slots SL1-SL4, and the surface of the write pulse 25 (outside CW) is independent of the data. In this embodiment, the length of the write pulse is equal to four time slots.

Fig. 3C shows the electro-optical response of a pixel in a 768 line FLC display operated by the "Split Writing" method of Figs. 3A and 3B. The amplitude of the selection pulse 22 and the data pulses 32-1 and 32-2 were 17 V and 10 V, respectively, and the length of the time slots SL1-SL4 was 32 ps, corresponding to a line addressing time (the length of the control window) of 4 * 32 ps = 128 ps.

The DC compensation pulse 26 and the erasing pulse 23, and their electro-optical power, are shown in the diagram in Fig. 3C. The upper part of the diagram shows a pulse sequence 40 which represents an actual voltage potential which is applied across the pixel. Two opposite switching operations are superimposed in Fig. 3C: the thicker curve T1 corresponds to a switching OFF -9 ON in response to the control pulse 41-in Fig. 3B, while the thinner curve T2 corresponds to a switching ON - + OFF in response on the control pulse 41-2 in Fig. 3B. However, the pixel is always forced to the OFF state by the erase pulse 23 before the control window CW. In accordance with Fig. 3A, the control window CW is marked with two vertical, dashed lines and is shown on an enlarged scale in the middle of the diagram. In the latter, enlarged view, it is clear that the RMS value in the control pulse inside the control window CW is significantly higher for the pulse sequence leading to the OFF state than for the one leading to the ON state. SUMMARY OF THE INVENTION The main object of the invention is to provide a higher addressing speed for a ferroelectric liquid crystal display (FLCD), (SSFLCD).

A particular object of the invention is to provide in particular a surface-stabilized FLCD with a solution which makes it possible to achieve an even higher addressing speed for an FLCD than is possible with known fast-addressing techniques.

A particular object of the invention is to provide a solution which makes it possible to achieve a frame refresh rate for FLCD devices which is useful for video purposes, i.e. to achieve an average line addressing time of 64 us.

The present invention is based on the insight that the above-described specific fast addressing technique for FLC displays can be further improved by using multi-line addressing. Although multiline addressing is known per se from the art of twisted or super-twisted nematic liquid crystals (TN and STN), it is true that since an FLC material and a TN / STN liquid crystal material exhibit extremely different electro-optical responses, it would not normally be possible to "combine" different addressing principles for these two substantially different materials.

More particularly, the present invention is based on the insight that (i) FLC materials are known FLC addressing techniques, and (ii) a specific addressing technique for (fast addressing technique) among several a specific addressing technique for a TN / STN material (multi-line addressing technique) among several known TN addressing techniques have some common features, and as a result they can be used to achieve even faster addressing of FLC displays.

Before describing the features of the invention, reference is now made to Figs. 2, 4 and SA and SB for an illustration of what is known in the field of multiline addressing for TN and STN liquid crystal materials. Fig. 2 shows schematically at the top a pulse sequence 50 for effecting an ON switch of a pixel in a TN cell. In order not to expose the liquid crystal display to a DC voltage, all voltage polarities are inverted during every other sweep, as shown in Fig. 2. The resulting net DC voltage over a complete cycle is therefore 0 V. Fig. 2 also shows the response characteristic 51 of the pixel and a relaxation phenomenon 52 during a plurality of sweep periods T. A curve 59 shows the average transmission of the cell during several sweeps.

In contrast to FLC materials, twisted or super-twisted nematic liquid crystals are not ferroelectric. They are therefore only RMS sensitive. An RMS voltage is proportional to the effect that a voltage waveform across the pixel can give: 1 T _, / X EM = í; [Eurdfl 0 In other words, the electro-optical switching from the OFF state to the ON state is independent of the direction of the outer applied field, ie independent of the sign or polarity of the applied control pulses. This is a significant difference in relation to the ferroelectric liquid crystal material described above, which is strongly dependent on the polarity of the pulse. In the FLC case, a polarity change causes a change in the electro-optical state. Thus, the pulse sequences applied to the select electrodes of a TN / STN display do not exhibit any erasure pulse and no write pulse of the type shown in Fig. 3A. Furthermore, in contrast to SSFLC devices, the switching time of TN and STN devices is several tens of powers longer than the selection time, and therefore several scanning frames are required to completely complete a switch, as shown by line 59 in Fig. 2, since a certain amount of relaxation 52 occurs between two addresses as a result of the inherent instability of the electro-optical states of a TN / STN-LCD.

TN / STN-LCD devices, which are thus only RMS-dependent and not dependent on the direction of the applied control field, simultaneously. can be operated by selecting several rows As shown in Fig. 4, adjacent row or selection electrodes are arranged in pairs, two and two, each such pair being addressed simultaneously within a common control window CW using two different selection pulses 71-1 and 71- 2. As stated above, no erase or write pulse is required as in the TN / STN case.

However, the SSFLC devices that the switching time of TN / STN-LCD- as indicated above apply in contrast to devices are several tens of powers longer than the selection time. Therefore, even in the case of multi-line addressing, several sweeps are required to achieve a complete cover. Each pair of selection electrodes must therefore be addressed many times before any switching of a pixel in the row can be completed, ie a complete switching requires a plurality of control windows CW.

Thus, the RMS value over several pixels in a column is controlled simultaneously to high or low using a so-called multi-line addressing technique. The control of the RMS value of the voltage potential across different pixels within a common column is achieved using row waveforms, which are created from a set of orthogonal functions. The row waveforms are mutually orthogonal and are independent of the information to be displayed. The column or data waveforms, on the other hand, depend on the information to be displayed and are proportional to orthogonal transforms of the column data. Fig. 5A shows some typical pulse shapes within the control window of a dual line addressing technique of an RMS-controllable TN device. The control window consists of four time slots. Even if two time slots are sufficient if you only look at the drive, two more slots are used to invert the row and column pulse shapes for DC compensation purposes. Reference numerals 71-1 and 71-2 represent two different selection pulses, while reference numerals 72-1 to 72-4 represent four different data pulses to be combined with one of the two selection pulses 71-1 or 71-2. Consequently, you have access to four different combinations of the resulting control field over each pixel pair belonging to a given column and which are addressed simultaneously. During a control window, two such pixels in a pair will thus receive one of the following four possible pairs of control pulses, and therefore be driven to one of four possible state combinations: Pulses received by the resulting state of the pixel pair pixel pair Pulses 73-1 and 73-2 OFF OFF Pulses 73-3 and 73-4 OFF ON Pulses 73-5 and 73-6 ON OFF Pulses 73-7 and 73-8 ON ON To achieve the above objects of the invention, and based on the above described The realization that one can combine addressing techniques for two substantially different liquid crystal materials, according to the invention a method and a use as defined in the claims.

According to a first aspect, the invention provides a method of controlling a ferroelectric liquid crystal display, comprising a first set of electrodes, called selection electrodes, and a second set of electrodes, called data electrodes, the electrode overlap defining pixel area defining which are switchable between different optical states. The method according to the invention comprises the following steps: - to produce sequences of data pulses which are fed in parallel to the data electrodes, corresponding to data to be written into the pixels; providing, on a cyclic basis to each selection electrode, a selection pulse sequence having: (a) a selection pulse located within a control window for addressing the selection electrode, during which control window said data pulses are applied to each of the data electrodes belonging to each pixel of the selection electrode and to a data electrode a resulting control pulse is generated which corresponds to a voltage difference which is thereby applied across the pixel below the control window, (b) an erasing pulse located in front of the control window for driving all the pixels in the selection electrode towards a predetermined first optical before the control window, and (c) a write pulse located at least partially outside the control window, the resulting control pulse applied over a given pixel controlling whether said given pixel, which has previously been driven toward the first state of the erase pulse, is driven by the write pulse into the other o the optical state, separate from the first optical state; and - addressing the selection electrodes in the form of subsets once at said control window, each subset comprising a number of P 2 2 of said selection electrodes, so that all P selection electrodes in a currently addressed subset are addressed simultaneously under the associated control window by a parallel application of P different selection pulse sequences of the above kind. 5 15 20 25 30 35 513 947 12 A control window is defined here as a predetermined period of time during which data intended for a given pixel appears on the data electrode associated with this given pixel.

Furthermore, although the term "pulse" is sometimes defined in the art as having a constant amplitude over the duration of the pulse, in this context the term "pulse" may sometimes comprise a sequence of individual pulses. For example, the above-mentioned "selection pulse sequence" comprises a selection pulse, an erasure pulse and a write pulse. The "selection pulse" will normally comprise a number of individual pulses, while the erase pulse and the write pulse will each normally consist of a single pulse of constant amplitude.

Correspondingly, the above-mentioned "data pulse" will normally consist of a number of individual pulses.

According to the invention, a PLC display is thus operated on a time-multiplexed base, where more than one selection electrode or is addressed at a time, in combination with the use of a fast addressing technique, for controlling the ferroelectric switching of the liquid crystal material. The main part of the switching takes place during the write pulse. The switching can be completed during the duration of the write pulse, but in some cases it may be that the switching is completed only after the write pulse, under the influence of the applied AC field. However, it is the control pulse that determines whether the write pulse should drive the pixel into the second state.

The resulting control pulse applied over a given pixel controls according to the invention whether this given pixel, which has previously been driven in the direction of the first state of the erasing pulse, is to be driven by the write pulse into the second optical state, separate from the first optical state. The inventors have discovered that it is not necessarily the RMS value of the control pulse that determines whether or not a switch takes place during the write pulse. Other parameters of the control pulse shape 10 15 20 25 30 35 515 947 13 have also been shown to be important for whether a switching should take place or not during the write pulse.

In particular, according to a preferred embodiment, the method according to the invention comprises the step of selecting a predetermined writing polarity for the writing pulse, the step of controlling whether the writing pulse is to drive the pixel into the second optical state comprising the step of controlling how much of said control pulse has a polarity opposite said writing polarity below the control window. For example, suppose a positive polarity has been selected for the write pulse. If the control pulse then has a sufficiently large negative part, the presence of this negative part will result in a holding back effect ("Hold Back" effect) on the switching operation, i.e. no switching will take place during the write pulse. A positive part or a weak negative part will not suppress or block switching. If, on the other hand, a negative polarity is selected for the write pulse, a sufficiently large positive part of the control pulse will block the switching. In the following, such a sufficiently large switch-blocking portion with opposite polarity will be referred to as the "blocking portion" of the control pulse. This "blocking portion" can be divided into a number of "sub-portions" distributed over time within the control window.

The inventors have also discovered that the switching operation may also depend on the position in time of said portion with opposite polarity within the control window.

If the batch is located close to the write pulse, it will have a stronger blocking effect.

According to another embodiment, and in accordance with the principle described above by Maltese for the single line fast addressing technique, the step of controlling whether the write pulse should drive the pixel into the second optical state comprises the step of controlling the RMS value of the resulting control pulse. At present, the most preferred embodiment is considered to include a combination of the above two embodiments, i.e. to design the selection pulses and the data pulses in a manner that both (i) controls whether the control pulse has a "blocking portion" and ( ii) controls the RMS value of the control pulse. In this case, both a polar response and a dielectric response will be present, and the switching will depend on the effective force or the net force.

The technique according to the invention can be used to increase the refresh rate for a given matrix size, for example to achieve a refresh rate which is sufficiently high for video purposes. Thus, for the "Split Writing" technique described above, the frame refresh rate can be doubled without reducing the width of the control window.

However, the invention can also be used to increase a matrix size without reducing a given frame refresh rate. The invention can also be used to increase the width of the control window for a given matrix size.

ADagen's SSFLC displays are in themselves bistable devices, ie they have two substantially stable optical states. subset of selection electrodes includes P = 2 In a preferred embodiment, each member applies. In this case, the addressing according to the invention will comprise P = 2 different selection pulse sequences and 2P = 4 different data pulses, which results in four different possible state combinations (ON ON; ON OFF; OFF ON; OFF OFF) subset. However, it is possible to increase for each pixel pair in an addressed addressing rate further by (i) (P> 2), using any known or future FLC- selecting more than two select electrodes simultaneously and / or display exhibiting more than two stable electro-optical states .

There are several important differences between the (ii) known multiline addressing technique for TN / STN-LCD-513 947 15 devices and the multiline addressing technique according to the invention: 1. In the known multiline addressing, writing is performed on TN / STN material only by using the dielectric response to an RMS write pulse, whereas the invention provides a multiline addressing on a material in which the switching is essentially a consequence of a ferroelectric response to a write pulse.

As a consequence of the difference in liquid crystal material, in the known multiline addressing, writing will not be completed in a single sweep, but will require several sweeps to be completed. According to the invention, multiline addressing is performed in such a way that the pixels can be completely switched during each scan. Each addressed pixel in a subset of electrodes thus reaches its final state before the subset is addressed again during subsequent sweeps.

In the known multiline addressing, all writing takes place during a period when the pixel is addressed, ie inside the control window, while the actual writing in the invention takes place in principle outside the control window, since the main part of the writing or switching takes place during the writing pulse. In other words, the voltage difference arising from the selection pulse sequences and the data pulse sequences does not produce any writing per se, as in the TN case, but instead the voltage difference affects whether writing takes place or not, outside the control window. This combination of the applied pulses which makes multiline addressing of FLCD devices possible thus does not take place between data and write pulses, but instead between data pulses and control pulses, which control a writing procedure outside the control window. . This difference is of course important, since the control window can thereby be shortened so that the frame refresh rate can be increased, even for multi-line addressing.

In the known multiline addressing, the row or selection pulse sequences have pulses only inside the control window, whereas the selection pulse sequences according to the present invention also have pulses outside the control window, namely the erasing pulse, at least a part of the write pulse and possibly a DC compensation pulse.

In the known multiline addressing of TN / STN displays, different row or selection pulse sequences applied to an electrode subset are completely different from each other, whereas the selection pulse sequences according to the invention only need to be different inside the control window. In particular, the write pulse during which the main part of the actual ferroelectric writing takes place can preferably be the same for all selection pulse sequences, even if more than one selection electrode is addressed simultaneously.

In the case where the "Hold Back" technique is used, there is an important and noticeable difference between the known multiline addressing technology for TN / STN devices and the multiline and fast addressing technology according to the invention for FLC devices. In the prior art, a high RMS value of the electric field acting on the pixel will result in an ON state of the TN / STN device, whereas a low RMS value will result in an OFF state. ie a strong RMS value will rotate the TN molecules in the direction of the field. In the "Hold Back" technique for addressing an FLC device, the situation is the opposite. A high RMS value of the control pulse below the control window - in combination with the presence of a sufficiently long "blocking portion" of the control pulse - will instead result in (OFF). A low RMS value - in combination with the absence of a pixel remaining in the erased state long enough "blocking portion" - will initiate a switch to the ON state, ie will not block the switching power of the write pulse.

According to a preferred embodiment of the invention, the different selection pulse sequences, and the different data pulses and the resulting control pulses are such that each group of pixels associated with a given data electrode within a subset can be driven by the control pulses to any of the SP possible combinations. optical states, where S is the number of optical states and P is the number of selection electrodes in the subset. For example, in a situation where P = 3 and S = 2 (ie, a bistable SSFLC display addressed with three rows at a time), it is possible to drive each group of three pixels in a data electrode within an addressed subset to each of de 23 = 8 possible combination- (000, 001, OlO, ... lll) these pixels. This can preferably be achieved by creating the optical state states of the selection pulses of the different selection pulse sequences based on orthogonal functions.

In a preferred embodiment of the invention, the selection pulse of the selection pulse sequence has a DC shift below the control window. More specifically, the selection pulse may be DC ~ offset in the polarity direction of the write pulse.

Other preferred embodiments of the method according to the invention are defined in the appended claims.

The invention also relates to the use of a dual-purpose switching control pulse (fast addressing and multiline addressing) in accordance with the principles set forth above and as defined in claim 18.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows a known electrode-matrix arrangement in an LCD, as well as an associated time-multiplexed addressing with row selection electrodes.

Fig. 2 schematically shows an RMS response characteristic of a TN liquid crystal cell, and a relaxation phenomenon during several sweeps.

Fig. 3A shows a selection pulse sequence used in a known "Back Back" type fast addressing technique for an SSFLC display.

Fig. 3B shows selection, data and control pulses belonging to the known fast addressing technique in Fig. 3A.

Fig. 3C superficially shows the electro-optical responses of a PLC cell, using the fast addressing technique of Figs. 3A and 3B.

Fig. 4 schematically shows a known multiline addressing technique for a TN-LCD (Twisted Nematic).

Figures SA and 5B show selection, data and control pulses belonging to the known multiline addressing technique in Figure 4.

Figures 6A and 6B show a first embodiment of the present invention prior to a time division multiplexed multi-line addressing of an SSFLC display.

Figs. 7A and 7B show a second embodiment of the present invention.

Figures 8A and 8B show a third embodiment of the present invention. DESCRIPTION OF EMBODIMENTS OF THE INVENTION Certain preferred embodiments of the invention will now be described with reference to Figs. 6-8.

In general, in an electrode matrix with R rows, each row or selection electrode is combined, in terms of addressing, with at least one additional selection electrode, in order to form R / 2 non-coincident subsets of selection electrodes. Although a subset may consist of any arbitrarily selected rows, it is easier to form a subset from two adjacent rows, as shown in Fig. 4 of the prior art multi-line addressing technique. A frame is completed when all the R / 2 subsets of row or selection electrodes have been selected once. described below, each subset of I includes all embodiments of the invention as addressed selection electrodes N = 2 electrodes. However, it is also possible to use N> 2 to divide the electrodes into another number of subsets. Of course, depending on the total number of selection electrodes, it may turn out that a few subsets will have a different number of electrodes.

Referring now to the first embodiment of the present invention shown in Figures 6A-6D. Fig. 6A shows two different selection pulse sequences 51-1 and 51-2, which have a common control window CW and which differ from each other only inside this control window CV. The same selection pulse sequences are fed to each subset of selection electrodes, however with a phase shift preferably equal to the control window. The selection pulses are preferably constant in time, ie they are not affected by the data entered in the display.

In the same manner as in the fast addressing technique of Fig. 3A, each selection pulse sequence 51-1 and 51-2 includes a DC compensation pulse 56, an erase pulse 53, a pause period 54, a selection pulse 51-1 / 52-2 and Thus, the selection pulse sequences in Fig. 6A are to some extent similar to those of the "Split Writing" system.

The selection pulse sequences 51-1 and 51-2 in Fig. 6A and the associated data pulses 57-1 to 57-4 in Fig. 6B have been designed for multiplexing a matrix of 768 selection electrodes. The amplitude of the write pulse 55 was equal to half the amplitude of the selection pulses 52-1 and 52-2 in the control window CW, in order to avoid any interaction with data. In order to achieve a sufficiently large area below the write pulse, ie in order to achieve a write pulse which can effect the switching of the ferroelectric state, the width of the write pulse 55 has been doubled. The amplitudes of the erase pulse 53 and the compensation pulse 56 were both selected to be the same as the amplitude of the write pulse 55. The widths of these two pulses 53 and 56 were seven and four times the addressing time CW, respectively. The pause period 58 was selected to eight times the addressing time CW.

In order to obtain a system where all possible state combinations can be obtained with multi-line addressing, the selection pulses 52-1 and 52-2 were created in the control window CW based on orthogonal functions.

The add pulses 53 switch the pixels to a first state (eg OFF), while the write pulse 55 acts to switch the pixels to a second state (ON). The switching is normally completed during the write pulse, although in some cases the switching is not completed until after the write pulse under the influence of the applied AC field. According to the invention, the amplitude and width of the write pulse must be such that the pixels are driven to the desired state depending on the shape of the control window. Preferably, the width of the write pulse 55 is such that the effective area of the pulses over the pixels during the duration of the write pulse is independent of the data sequences fed to the data electrodes. The width of the write pulse is, for example, an integer multiple of two time slots, when two selection electrodes are addressed simultaneously. Thus, in this embodiment, the selection pulse sequences 51-1 and 51-2 for two rows or selection electrodes in a subset differ from each other only inside the control window. 52-2, the mutually different data pulses 57-1 to Fig. 6B show two selection pulses 52-1, four associated, 57-4, to 57-8. as shown in Fig. 5A, the selection pulses 52-1 and 52-2 and the shape of eight resulting control pulses 57-1 are in contrast to the known multiline system of the selection pulse sequences 51-1 and 51-2 in this embodiment both offset upwards towards the positive side. , which gives a DC offset (compensated with the pulses 56). The four data pulses 57-1 to 57-4 are obtained from orthogonal transforms of the applied data, and the resulting voltage differences in the form of the eight control pulses 58-1 to 58-8 are used to force each pixel pair into one of four possible state combinations ( ON ON; ON OFF; OFF ON; OFF OFF). If, for example, two pixels belonging to a given data electrode are addressed simultaneously and are to be switched to the state combination "OFF oN", this data electrode below the control window. As a result, the first pixel will be exposed to the control pulse 58-5 representing both a high RMS value and a negative blocking portion. The first pixel will therefore be kept in the OFF state. The second pixel will be subjected to the control pulse 58-6 representing a low RMS value and no negative blocking portion. This pixel will therefore be switched by the subsequent write pulse 55 to the ON state.

As can be seen from a comparison between Figs. 5A and 6A, the logic effect of the resulting control pulses acting on the liquid crystal material inside the control window in this embodiment of the invention is opposite to the logic effect in the RMS response devices, since a high RMS value inside the control window The CW will block each switch during the write pulse 55. In addition, the possible presence of a blocking portion of opposite polarity to the write pulse will affect the switching operation.

The amplitude of the data pulses is less critical compared to that in the multiline technology for driving RMS-controllable TN / STN-LCD devices. The amplitude of the data pulses should be high enough to suppress any switching of the pixels that have been controlled to the OFF state. The amplitude should also be high enough to provide AC stabilization of the switched states. However, an excessive amplitude of the data pulses can have a certain effect on the state of the pixel outside the control window CW.

The SSFLC cells used to obtain the results in Figures 6C and 6D were prepared by polishing ITO plates coated with PI-2610 polyimide. The measurements were performed using a cell with a cell gap of 1.9 μm with the cell filled with a Hoechst-FLC mixture Felix 16/000. The switching time of the cell was about 115 ps when applying a square wave with amplitudes ¿16 V and a period time of 800 us.

The electro-optical response of the pixels in two rows was observed using a single pixel cell, by a modification of the selection pulse sequence as follows. Frames corresponding to row 1 and row 2 were merged to form a single selection pulse sequence. The data for the pixels in both rows was selected to be the same.

The data pulse sequences were thus made identical in both frames. The selection pulse sequences were obtained from an 8-channel waveform generator (FLC Electronics) controlled by a Macintosh computer. The cell was placed under a polarizing microscope (Olympus), and its optical response was measured using a high-speed photodetector (PLC Electronics) and recorded on a digital oscilloscope (HP54810A).

The data collection was performed using software from Labview. 10 15 20 25 30 35 515 947 23 The resulting voltage difference across the cell together with the electro-optical response is shown in Fig. 6C.

The data pulses were such that the pixel in line 1 is OFF and the pixel in line 2 is ON. An expanded view of the switching of a pixel in row 1 to the OFF state is given in Fig. 6D. After a first switch, the data pulse sequence was inverted in the control window, in order to show a switch to the ON state of the same pixel. The two curves have been superimposed for comparison purposes. The thicker curve shows the switch to the ON state, while the thinner curve shows the switch to the OFF state. The data pulse sequences were changed randomly, thereby verifying that the pixel was indeed switched to the expected state regardless of the adjacent data. In this experiment, the time slot was selected to 32 ps, which gave a control window of 128 ps. Since two lines were addressed simultaneously, the line address time averaged 64 us, which means that the display can be operated at video speed.

Reference is now made to a second embodiment in Figs. 7A and 7B, which in many respects corresponds to the first embodiment in Figs. 6A and 6B. As shown in Fig. 7A, each selection pulse sequence 61-1 and 61-2 includes a compensation pulse 66, an erase pulse 63, a pause period 64, a selection pulse 62-1 and 62-2 within the control window CW, and a write pulse 65. This second embodiment is preferred over the embodiment of Fig. 6 because it is more compatible with existing display drives and easier to generate. In Fig. 6, the data pulses 57-1 to 57-4 are data pulses with three levels, ie three different voltage levels are used to build up each data pulse. As shown in Fig. 7B, only two voltage levels are used to generate the data pulses 67-1 to 67-4 in this embodiment.

In addition, the selection pulses 61-1 and 62-1 are both negative and positive and have voltage sequences + U + U -U + U and + U -U + U + U, while the sequences in the first embodiment are + U + UOO and + U 0 In Fig. 7B 10 15 20 25 513 947 24 it should be noted that all the control pulses 68-1 to 68-8 have a negative portion, but only those with a sufficiently large negative portion (= a "blocking portion"). will lead to an OFF state.

The embodiment shown in Figs. 8A and 8B is today considered to be the most preferred embodiment. As shown in Fig. 8A, each selection pulse sequence 81-1 and 81-2 includes a compensation pulse 86, an erase pulse 83, a pause period 84, a selection pulse 82-1 and 82-2 within the control window CW, and a write pulse 85. Fig. 8B shows the data pulses 87-1 to 87-4, and the resulting control pulses 88-1 to 88-8. Low operating voltages are preferred in terms of power consumption when operating the display, simple manufacture of driving circuits. In addition, it is preferable to keep the number of voltage levels to a minimum. This reduces the complexity of the drive circuit hardware. The waveforms of the selection pulse sequences 81-1 and 81-2 in this embodiment are optimized so that the -U). The number of voltage levels in the waveforms of the data pulses 87-1 to there are only three voltage levels (+ U, 0, 87-4 are only two. The drive circuit is therefore simple, and drive circuits available for STN-LCD devices can be used. Compared to the known "Split In the Writ "technique), it is thus possible with the embodiment in Figs. 8A and 8B to drive twice as many lines without any significant increase in the driving voltages.

Claims (18)

lO 15 20 25 30 35 513 947 25 PATENT REQUIREMENTS A method of controlling a ferroelectric liquid crystal display, comprising a first set of electrodes, called selection electrodes (20), and a second set of electrodes, called data electrodes (30), the electrode overlap areas defining pixels that are switchable between different optical states; which method comprises the following steps: - to produce sequences of data pulses (57; 67; (30), corresponding to data to be written into the pixels; 87) which are fed in parallel to the data electrodes - to provide, on a cyclic basis to each selection electrode ( 20), a selection pulse sequence (51; 61; 81) having: (52; 62; control window (CW) for addressing selection (a) a selection pulse 82) located within an electrode (20), below which control window (CW) said data pulses (57; 67; 87) are applied to each of the data electrodes, whereby at each pixel belonging to the selection electrode (20) and to a data electrode (30) a resulting control pulse (58; 68; 88) is generated, which corresponds to a voltage difference thereby applied across the pixel below the control window (CW), (b) an erasing pulse (53; 63; 83) located in front of the control window (CW) for driving all the pixels in the selection electrode (20) towards a predetermined determined first optical state before control window et (CW), (c) a write pulse and (55; 65; 85), partly outside the control window located at least (CW), controlling pulse (58; 68; 88), the result applied over a given pixel controlling whether the given pixel, which has previously been driven in the direction of the first ), the writing pulse (55; 65; 85) into the second optical state of the erasing pulse (53; 63; driven by the state, separate from the first optical state; and - addressing the selection electrodes (20) in the form of subsets one at a time under said control window (CW), each subset comprising a number P ¿2 of said selection electrodes (20), so that all P (20) in a currently addressed subset are addressed simultaneously during the selection electrodes belonging to the control window (CW) by a parallel application of P different selection pulse sequences (51-1, 51-2; 61-1, 61-2; 81-1, 81-2) A method according to claim 1, of the above kind. comprising the step of selecting as said ferroelectric liquid crystal display a display in which the pixels are switchable between S different optical states, and wherein the step of producing (51-1, 51-2; 61-1, 61-2; 81-1, 81-2 ) comprises the step of producing at least SP sequences with data pulses different data pulses (57-1 to 57-4; 67-1 to 67-4; 87-1 to 87-4). The method of claim 2, wherein said P has different selection pulse sequences (51-1, 51-2; 61-1, 61-2; 81-1, 81-2), said at least SP different data pulses (57-1 to 57-4; 67-1 to 67-4; 87-1 to 87-4) the control pulses (53; 63; 83) are such that each group of P pixels belonging to a given data electrode (20) within one and the resulting subsets can be driven by the resulting control pulses combinations of optical states for said P pixels. A method according to any one of the preceding claims, wherein the selection pulses (51-1, 51-2; 61-1, 61-2; 81-1, 81-2) of said P are different selection pulse sequences (51-1, 51-2 ; 61-1, 61-2; 81-1, 81-2) are obtained from orthogonal functions. The method of any of the preceding claims, further comprising the step of selecting a predetermined write polarity for said write pulse (55; 65; 85), and the step of controlling whether the write pulse (55; 65; 85) 513 947 27 is to drive the pixel into the second optical state comprising the step of controlling how much portion of said (53; 63; 83) said writing polarity below the control window has a polarity opposite (CW). A method according to any one of the preceding claims, wherein the control pulse at the step of controlling whether the write pulse (5S; 65; 85) is to drive the pixel into the second optical state comprises the step of controlling the RMS value of the (53; 63; 83) ). A method according to any one of the preceding claims, wherein the control pulse at the control pulses (53; 63; 83) generated by the selector (52; 62; 82) 87) has a DC offset within the control window (CW). A method according to any one of the preceding claims, the pulse pulses and the data pulses (57; 67; at said given pixel, if driven by the second optical state of the write pulse (55; 65; 85) before said pixel is addressed into said second optical state , achieve the said again. A method according to any one of the preceding claims, wherein the amplitude of the selection pulse (52; 62; 82) within the control window (CW) is higher than the amplitude of the write (55; 65; 85) (CW). Method according to any one of the preceding claims, the warp pulse outside the control window at one and the same set of said P different selection pulse sequences (51-1, 51-2; 61-1, 61-2; 81-1, 81- 2) is applied to each of said subsets of selection electrodes (20), but with a phase shift equal (CW). A method according to any one of the preceding claims, wherein the length of the control window at said different optical states are substantially stable optical states. A method according to any one of the preceding claims, comprising the step of selecting as said ferroelectric liquid crystal display a surface stabilized ferroelectric liquid crystal display (SSFLC). 10 15 20 25 513 947 28 A method according to any one of the preceding claims, wherein each of said different selection sequences (51; 61; 81) is constant A method according to any one of the preceding claims, wherein- (55; 65; 85) (51; 61; 81) A method according to any one of the preceding claims, wherein- (5l; 61; 81) differs from each other only in its select- 82). Method according to any one of the preceding claims, each time. at the write pulses of said different selection pulse sequences are mutually identical. at said different selection pulse sequences ring pulse (52; 62; at the addressing is of the "Hold Back" type with the control window (CW) of each selection pulse sequence (51; 61; 81) located at the beginning of the write pulse (55; 65; 85). A method according to any one of claims 1-15, wherein the addressing is of the "Hold On" type with the control window (CW) of each selection pulse (51; 61; 81) (55; 65; 85). Use of a dual control pulse located at the end of the write pulse (58; 68; 88) for performing a time-multiplexed, fast multiline addressing of a ferroelectric liquid crystal display, which control pulse is (CW) providing the multiline addressing (below the control window); CW). operation performed with a write pulse (CW). present inside a control window and used for and also for controlling a ferroelectric switch (55; 65; 85) located outside the control window