SE502435C2 - Method and apparatus in a semiconductor circuit - Google Patents

Abstract

The present invention relates to the activation and deactivation of a transistor (Q1) in a final stage (10), for instance a push-pull final stage. The final stage is included in a voltage alternating drive system connected to a load. A current driving buffer circuit (24) in the drive system is connected to the transistor (Q1) and functions to activate and deactivate the transistor, i.e. to switch the transistor on and off, in a manner such as to generate only a low power loss in the transistor, even when the load is inductive. The current driving buffer circuit (24) includes a first inverting circuit (Q3, Q4), a second inverting circuit (Q5, Q6), a current generating circuit (Q7, Q8), and a semiconductor element (Q9). The inverting circuits coact with the current generating circuit (Q7, Q8) to switch off the transistor (Q1), wherein the current generating circuit generates a deactivation current (IDIS) which charges capacitances (CGSQ1, CGDQ1) in the transistor (Q1) very rapidly, so that the voltage (OUTLSB) on an input of the transistor (Q1) will increase to a deactivation level (VCCH). The inverting circuits coact with the semiconductor element (Q9) to activate or switch on the transistor (Q1), wherewith the semiconductor element generates an activation current (ICON) which charges the capacitances (CGSQ1, CGDQ1) in the transistor (Q1), so that the voltage (OUTLSB) on an input of the transistor (Q1) falls to an activation level (VREG).

Description

It is also known in a voltage switching drive system to use a receiving output stage to supply voltage to an inductive load.

The receiving output stage a driving and a lowering transistor which is connected to the driving transistor when switched on connects the load to a high voltage while the lowering transistor when switched on connects the load to a low voltage. According to the Swedish patent SE 464 002, it is known to use a so-called bistable circuit for quickly charging and discharging its capacitors when connecting or disconnecting the driving transistor. The bistable circuit comprises a plurality of field effect transistors as well as two two-pole fast-charging interconnects comprising alternating wherein the control voltage circuits which are arranged to the capacitances of the driving transistor in switching on and off the loss effects in the driving transistor. of this in order to reduce the disadvantage of the latter voltage-switching drive system which comprises a receiving output stage is that said capacitances are not charged fast enough, which causes the loss effects to be too high. The problem which the invention intends to solve is that when disconnecting a power transistor in an output stage with inductive load, the switching is carried out quickly and the loss power is minimized.

This problem is related to the fact that a voltage-switching drive system, comprising an output stage with a transistor of the PMOS power transistor type, supplies a voltage of an inductive nature. switched on and depending on a control signal, switched on mode voltage feeds the inductive load. When the power transistor is switched off, the inductance appears as one which leads to the power transistor. The power transistor is disconnected, the power transistor being switched to a constant current generator, followed by a charge redistribution in which the charge redistribution causes the switched-off transistor 10 to become non-conductive. The current which, due to the inductive load, is inadvertently conducted through the transistor is bad because it generates loss effects which become particularly noticeable in high-voltage circuits.

An object of the present invention is therefore to provide a method and a device for switching on and off a power transistor in an output stage without generating unmanageable loss effects.

A further object is to provide a method and a device for ensuring that the disconnection of a power transistor in an output stage takes place quickly and safely without the risk of the power transistor being inadvertently switched on and conducting current.

A further object is that when disconnecting a power transistor in an output stage, it generates a sufficiently large current to the disconnected power transistor that its gate-source capacitance is quickly discharged, which leads to fast and safe disconnection.

Thus present an electrical voltage switching drive device connected to a load which is, for example, inductive. The drive device can be designed in different ways. In all embodiments, however, it includes an output stage with a power transistor connected to the load and an electrical control circuit connected to the output stage which connects and disconnects the power transistor so that the output stage supplies the load with a high power transistor connected.

The connection and disconnection are controlled by a control signal. An invention relates to voltage when in the invention is a current driving buffer circuit which is included in the control circuit which is the power transistor and arranged to switch on and off the power transistor depending on the control signal in such a way that only a low loss power develops in it even though the final stage may also contain bipolar connected to the load is inductive. 10 15 20 25 30 502 435 4 transistors but the driving buffer circuit is optimized for field effect transistors. first circuit and a The driving buffer circuit comprises an inverting circuit, a second inverting darling tone circuit. During disconnection, the inverting circuits cooperate in such a way that the darling tone circuit generates a disconnection current to the power transistor, which disconnection current quickly discharges the gate-source capacitance in the power transistor so the power transistor is prevented from inadvertently conducting current when disconnected.

The current driving buffer circuit also comprises a semiconductor element which, depending on the controlling signal, switches on the power transistor by generating a switching current which charges the power transistor is switched on. The invention also relates to a method for switching on and off the power transistor in a voltage-switching drive device of the type described. The method includes a first and a second inverting of a control signal, outputting the inverted signals to a current generating circuit and generating and disconnecting current to the input of the power transistor to charge capacitances in the power transistor outputting a so that the voltage level of the power transistor is converted to an input level. The disconnection thus takes place quickly and safely.

The method also comprises that the power transistor is switched on by generating a switching current and charging capacitances in the power transistor, so that the voltage at the input of the power transistor is switched on, whereby the power transistor is switched on.

The invention thus solves the described problem which may arise in connection with the disconnection of a power transistor. The advantage of the solution is that the disconnection is carried out so quickly and safely that the drive device can operate with high switching frequencies and still keep the loss effects low.

An additional advantage as a result of the low loss effects in the final stage is that the capsule which is to enclose the final stage can be of a simple and inexpensive kind, since it does not have to be adapted to be able to dissipate large amounts of heat.

The invention will now be described in more detail by means of a preferred embodiment and with reference to the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a block diagram of a voltage switching drive device according to the invention comprising a receiving output stage connected to an inductive load.

Figure 2a shows a detailed circuit diagram of a current driving buffer circuit in the drive device, which buffer circuit is connected to a power transistor in the receiving output stage and to the inductive load. The figure also shows the currents that the circuit conducts in connection with the disconnection of the power transistor.

Figure 2b shows the same circuit diagram as in figure 2a with the currents that the circuit conducts in connection with connection of the power transistor.

Figure 3 shows a flow chart of a method according to the invention.

Figure 4 diagrammatically illustrates signals appearing in the device according to the invention.

Figure 5 shows a block diagram of a further embodiment of a voltage-switching drive device according to the invention comprising a simple output stage connected to an inductive load.

Figure 6 shows a block diagram of a third embodiment of a voltage-switching drive device according to the invention comprising a receiving output stage connected to an inductive load.

Figure 7 illustrates diagrammatically signals appearing in the voltage-switching drive device according to Figure 6. Figure 15 shows a block diagram of an electric voltage-switching drive device connected to a load which is inductive in nature. The drive device comprises a high voltage output terminal 10 connected to the inductive load 12 and an electrical control circuit 14 connected to the output terminal 10. The output stage 10 comprises a driving transistor Q1 connected to a lowering transistor Q2, which transistors are connected between a positive pole and a negative pole of a first voltage generator V1. The positive pole has a high supply voltage VCCH and the negative pole has earth potential.

The high supply voltage can be, for example, 300 V. The connection between the transistors constitutes an output 16 at the output stage.

The load 12 is connected to the output 16 of the output stage and to a connection 18 between two 'equal capacitors Clär connected between the positive pole and the negative pole capacitors CP of the first voltage generator' V1. Capacitor C, between terminal 18 and ground, can be considered as a first voltage source that emits half the high supply voltage VCCH. The inductive load 12 can, for example, be used together with an electronically driven fluorescent lamp and thereby be connected in series with this.

The control circuit 14 is on and off the driving and lowering transistors so as to be arranged that alternating load 12, at the output stage 16, is alternately supplied with the voltage VCCH at the positive terminal of the first voltage generator and alternating with the voltage 0V at the negative voltage of the voltage generator.

The voltage at the output 16, the output voltage OUT, thus switches between a high level which is equal to the voltage at the positive pole when the driving transistor Q1 is connected and conducts current, and one which is equal to the voltage at the negative pole when the low level is switched on. Q2 is and conducts power.

The transistors conduct current in the opposite direction through the inductive load L. The receiving output stage corresponding to a control input of the driving transistor, on which a buffer output signal OUTLSB is received for switching on and off the driving transistor Q1. The output stage 10 also has a first input G1, a second input G2, corresponding to a control input on the lowering transistor Q2 for receiving a switching signal OUTBUFF for switching on and off the lowering transistor Q2.

The control circuit 14 comprises a clock circuit 20, a level shifting circuit 22, a current driving buffer circuit 24 according to the invention connected to the driving transistor Q1 and a simpler buffer circuit 26 connected to the lowering transistor Q2.

The clock circuit 20 (CL) is arranged to generate a control signal IN1, which is used to control the connection and disconnection of the transistors in the receiving output stage. According to the example, the control signal IN1 consists of a clock signal with periodically recurring, equally long, clock pulses. One clock pulse edge is used to control the disconnection of the driving lowering transistor while the other clock edge is used to control the disconnection of the lowering transistor and the connection of the driving transistor. The control signal IN1 can also have shorter or longer pulses. The clock circuit 20 is supplied with voltage from a second voltage generator V2 which emits a logic voltage VLS of, for example, 9 V. The control signal IN1, which switches between the logic voltage VLS and 0 V, is emitted from an output 28 of the clock circuit 20. The transistor and the connection of the level switching circuit 22 (LS) has an input 30 connected to the output 28 of the clock circuit for receiving the control signal IN1. The level switching circuit 22 is voltage supplied by the first voltage generator V1, by a second voltage generator V2 and by a third third supply voltage VREG, slightly lower than the high supply voltage VCCH, for example 288 V. At an output 32 the level changing circuit 22 emits a level shifted control signal OUTLS which is synchronous voltage generator V3 which emits one with the controlling signal IN1 but the pulses switch between the high supply voltage VCCH and the lower supply voltage VREG. The level-shifted control signal OUTLS has in the level-switching circuit 22 obtained voltage levels which are current-driven somewhat adapted to the voltage levels in that buffer circuit 24. The current-driving buffer circuit 24 has an input 34 connected to the output circuit 32 of the level shift. 22 to receive the level-shifted control signal OUTLS. Since the level-shifted control signal OUTLS constitutes an input signal to the driving buffer circuit 24, it is also referred to in the description as a buffer input signal INLSB. The current buffer circuit 24 is connected to the positive poles of the first voltage generator V1 and of the third voltage generator V3. At an output 36, the circuit 24 outputs a buffer output signal OUTLSB, which is connected to the input G1 of the driving transistor Q1. The buffer output signal OUTLSB switches between a high level supply voltage and a low level corresponding to the third supply voltage for switching on and off the driving transistor Q1, depending on the control signal IN1, in a manner corresponding to the high invention according to the invention.

The simpler buffer circuit 26 has an input 38 connected to the clock circuit 20 for receiving the control signal IN1. At an output 40, the simpler buffer circuit outputs said switching signal OUTBUFF which is coupled to the input G2 of the lowering transistor Q2 to control the switching on and off thereof.

The receiving output stage 10 comprises, as previously mentioned, a driving transistor Q1 and a lowering transistor Q2. The driving transistor may, for example, be a p-channel FET transistor and the lowering transistor may be, for example, an n-channel FET transistor. It is also possible to use bipolar transistors, but the design is optimized for power transistors. The driving transistor Q1 is connected with its S-terminal S1 (SOURCE) to the positive pole of the first voltage generator V1 with the supply voltage VCCH as according to (high voltage) and with its D- connection (DRAIN) connected to the output output stage 16 and with its G connection G1 (GATE) connected to the output 36 on the current buffer circuit 24 OUTLSB. Depending on the example for receiving the buffer output signal, 300 V '10 15 20 25 30 35 9 502 435 the voltage level of the buffer output signal, the driving transistor Q1 is throttled or conductive. When the buffer output signal is equal to the high supply voltage VCCH, the drive transistor is throttled, but when the voltage is lowered to the slightly lower supply voltage VREG, the drive transistor is switched on and supplies the load with the high supply voltage. When the drive transistor is connected, it conducts an inductive current IL from the transistor to the inductive load 12. In parallel with the driving transistor Q1, a first so-called freewheel diode D1 is connected, which is usually built into the drive transistor Q1.

The lowering transistor Q2 is connected with its S-terminal S2 (SOURCE) to the voltage 0 V (ground) and with its D-terminal (DRAIN) connected to the output 16 of the output stage and with its G-terminal G2 (GATE) connected to the simpler the buffer stage 26 for receiving the switching signal OUTBUFF. The switching signal OUTBUFF switches between high and low level, whereby high level corresponds to the logic voltage VLS and low level corresponds to voltage 0'V. Depending on the OUTBUFF voltage of the switching signal, the lowering transistor is throttled or conductive. When the OUTBUFF voltage is 0 V, the lowering transistor is throttled, but when the OUTBUFF voltage increases to 9 V (VLS), the lowering transistor is switched on and supplies the load 12 with the low voltage OV. When the lowering transistor Q2 is connected, it conducts an inductive current IL, in the load 12 In parallel with the lowering transistor Q2, a second so-called freewheel diode D2 is built into the lowering transistor Q2. the direction from to the transistor. switched on, which is usually The two transistors Q1 and Q2, which are complementary, together form an inverting receiving output stage which functions in a simplified manner in the following manner. When the input signals 0UTLSB, 0UTBUFF to the receiving output stage have a high level, only the lowering transistor Q2 conducts, whereby the output voltage OUT of the output stage is obtained low (ov). In the voltage drop across the lowering transistor when it conducts, which voltage drop is about 1 V. When the input signals OUTLSB, OUTBUFF, on the other hand, have a low level, the driving transistor conducts instead, level this simplified description is disregarded. output voltage OUT reaches high level (VCCH). The voltage drop of approx. 1 V across the conductive drive transistor is ignored. The two transistors conduct alternating current in the opposite direction through the inductive load 12.

Since the output 16 of the output stage is connected to an inductive load 12 and since the current through the load changes direction in connection with switching of the transistors Q1 and Q2, the inductive load drives the output voltage level OUT to change from high to low level when the driving transistor Q1 is disconnected. Correspondingly, the output voltage level OUT changes from low to high level when the lowering transistor Q2 is switched off.

Figures 2a and 2b show a detailed circuit diagram of the driving buffer circuit 24 of Figure 1. The figures also show how the driving buffer circuit is connected to the driving transistor, represented by two capacitors, and to the inductive load 12. The driving transistor Q1 is illustrated by two capacitances to facilitate the invention. The figures differ only in that in Figure 2a the currents which occur in connection with disconnection of the understanding of the driving transistor are plotted, while in Figure 2b the currents which occur in connection. with the connection of the driving transistor drawn.

In connection with Figures 1, 2a and 2b, the problem which the invention intends to solve is also described in more detail. To describe the problem, it is convenient to consider the driving transistor as two capacitors in accordance with Figures 2a and 2b. The first capacitance consists of a gate-source capacitance Can, between the input G1 of the drive transistor and the high supply voltage VCCH. The second capacitance consists of a gate-drain capacitance Cømn between the drive transistor input G1 and the output 16. When the buffer output signal OUTLSB is low, the voltage level VREG, the driving transistor Q1 is switched on, ie on and supplies the high supply voltage VCCH to the output 16.

This ignores the voltage drop, which is only a few volts, across the driving transistor as it conducts. At the same time, the transistor Q1 drives an inductive current IL through the inductive load 12. The driving transistor is theoretically disconnected by increasing the voltage at the input G1 of the drive transistor to the supply voltage VCCH. However, this theoretical disconnection method, to only increase the input of the drive transistor, is not sufficient because the driving transistor can be considered as two capacitances according to Figures 2. The inductive load acts as a current generator at the moment of shutdown and continues to conduct the inductive load current despite the disconnection procedure.

As a result of the inductive load current continuing to be conducted through the load 12, the voltage OUT at the output 16 drops very rapidly so that the inductive load current IL can be conducted through the freewheel diode D2 in the lowering transistor Q2 until the energy of the inductive load has been discharged.

The voltage OUT at the output drops to approx. minus 1 volt for the second diode D2 to be able to conduct the discharge current. The rapid voltage drop at output 16 is transmitted by the gate input G1 of the driving voltage of the drain capacitance Cmn, to the transistor Q1, whereby also the voltage of the input G1 drops, which entails a risk that the driving transistor becomes conductive again even though it is "disconnected". The amount of current that is inadvertently passed through the driving transistor in this way after it has been disconnected depends on the inductive load current and on how good the transistor has.

The unintentional current causes loss effects which becomes a particularly concise summary of the problem is that when the drive transistor is disconnected, the voltage at its input can inadvertently drop, causing the disconnected transistor to conduct current. the amplitude of the noticeable in high voltage circuits. The current driving buffer circuit 24 is designed to solve the problem described above and for this purpose comprises a first inverting circuit Q3, Q4, a second inverting circuit Q5, Q6 and a current generating circuit which according to the exemplary embodiment consists of a darling tone circuit Q7, Q8. In addition, the current driving buffer circuit 24 comprises a semiconductor element Q9 for switching on the driving transistor Q1. The current driving buffer circuit 24 is arranged to disconnect the driving transistor Q1 without the described problem occurring. It is also arranged to connect the driving transistor.

The first inverting circuit Q3, Q4 has an input 42 connected to the buffer circuit receiving the buffer input signal INLSB and an output 44 on which a first inverted signal N1, corresponding to the buffer output signal OUTLSB is output.

The output 44 of the first inverting circuit Q3, Q4 is thus connected to the output 36 of the current buffer circuit 36. Input 34 for the second inverting circuit Q5, Q6 has an input 46 connected to the input circuit 34 of the buffer input signal INLSB and an output 48 on which a second receiving of inverted signal N2 is emitted. The output 48 of the second inverted circuit Q5, Q6 is connected to an input 50 of the darling tone circuit Q7, Q8 and to an input 52 of the semiconductor element Q9.

The Darlington circuit Q7, Q8 has an output 54 connected to the output 36 of the current buffer circuit. The semiconductor element Q9 also has an output 56 connected to the output of the buffer circuit. The current 36 of the current buffer circuit is as to the transistor as in output 36. previously described the connected control input G1 (G connection) on the driving figure is represented by the two capacitances CGSQHCODQP In the figure the inductive load 12 is also shown.

The first inverting circuit Q3, Q4 comprises a third FET transistor Q3 and a fourth FET transistor Q4. The third n-channel type FET transistor Q3 is connected with the G-terminal G3 to the input of the first inverter 42. The D-terminal D3 is connected to the output 44 of the first inverter and the S-terminal S3 is connected to the positive pole of the third voltage generator V3 for receiving the potential VREG. The fourth p-channel type FET transistor Q4 is connected with the G-terminal G4 to the input 42 of the first inverter.

The D-terminal D4 is connected to the output 44 of the first inverter and the S-terminal S4 is connected to the positive pole of the first voltage generator V1 for receiving the potential VCCH.

The voltage N1 at the output 44 of the first inverting circuit Q3, Q4 thus alternates between the high level VCCH and the low level VREG.

The second inverting circuit Q5, Q6 comprises a fifth FET transistor Q5 and a sixth FET transistor Q6. The fifth n-channel type FET transistor QS is connected with the G-terminal G5 to the input of the second inverter 46. The D-terminal D5 is connected to the output 48 of the second inverter and the S-terminal S5 is connected to the positive pole of the third voltage generator V3 for receiving the potential VREG. The sixth p-channel FET transistor Q6 is connected with the G-terminal G6 to the input 46 of the second inverter.

The D-terminal D6 is connected to the output 48 of the second inverter and the S-terminal S6 is connected to the positive pole of the first voltage generator V1 for receiving the potential VCCH.

The voltage N2 at the output 48 of the second inverting circuit Q5, Q6 thus alternates between the high level VCCH and the low level VREG. comprises a seventh transistor Q7 connected to an eighth transistor Q7 constituted by an NPN bipolar transistor. Base terminal S0 of the NPN transistor Q7 constitutes the input of the darling tone circuit and is connected to the output 48 of the second inverting circuit Q5, Q6.

The collector connection C7 of the NPN transistor Q7 is connected to the positive pole of the first voltage generator V1 for receiving the potential VCCH. The emitter terminal E7 of the NPN transistor is connected via a first resistor R1 to the output 54 of the darling tone circuit. The eighth also has an NPN bipolar transistor. Its connected to transistor Q7.

Darlington circuit Q7, Q8 transistor Q8. The seventh transistor Q8 is the base terminal B8, the emitter terminal E7 of the seventh collector terminal.C8 is connected to the positive terminal of the first voltage generator V1 while the emitter terminal is connected to the output of the darling tone stage 54. The semiconductor element Q9 is a nion transistor of the type P-channel FET. The G9 terminal G9 of the ninth transistor constitutes its input '52 while the S-terminal S9 constitutes its output 56. The D-terminal D9 is connected to the positive pole of the third voltage generator V3 for receiving the potential VREG.

A zener diode Z is connected between the output 36 of the driving buffer circuit 24 and the positive pole of the first voltage generator V1. The function of the zener diode is to protect the transistors in the darling tone stage and the fourth FET transistor from being destroyed when the lowering is switched off. zener diodes. The zener diode blocks the voltage OUTLSB at the input G1 from becoming the transistor Q1. If the zener diode did not exist, the voltage on the transistor Q2. A possible current is instead passed through too high at the disconnection of the input of the driving transistor Q1, could rise to twice the supply voltage VCCH, whereby a current could be conducted in the wrong direction through the darlington transistors.

Figure 3 shows a flow chart of a method according to the invention and figure 4 illustrates signals appearing in the device according to the invention. The operation of the device driving the current buffer circuit in connection with disconnection of the driving transistor is described below with reference to Figure 2a, while the function of the buffer circuit in connection with the connection is described with reference to Figures 3 and 4. It is described with reference to Figure 2b. At the top of the signal diagram in Figure 4, the controlling signal IN1 is shown, with its recurring pulses. The time t1 in the signaling scheme can be regarded as a starting point for the description of the method according to the invention. In the output position 58 in Fig. 3, the driving transistor Q1 is switched on, which in the signal diagram is illustrated by the buffer input signal INLSB having the high level VCCH and the buffer output signal OUTLSB having the low level VREG with Q1 supplying the output 16 with the power transistor high voltage level C. The output voltage OUT thus has the high voltage level VCCH. The driving transistor Q1 conducts a load current IL IL through the inductive load 12. at time t, a first changeover A of the control signal IN1 takes place, its voltage level changing from the high voltage level VLS to the low level OV. This event is indicated in a block 60 in the flow chart in Figure 3. The corresponding switching E takes place in the level-shifting circuit LS so that the buffer input signal INLSB is switched from the high voltage level VCCH to the low voltage level * VREG to influence. the current buffer circuit 24 to convert the buffer output signal OUTLSB to a disconnection level VCCH. The buffer input signal INLSB is inverted in the first inverting circuit Q3, Q4 and in the second inverting circuit Q5, Q6, the first inverting signal N1 and the second inverting signal N2 being converted to the high level VCCH (Not shown in Fig. 4). However, the conversion of the inverted signals N1, N2 does not take place momentarily or simultaneously. The second inverting signal is converted faster to the high VCCH, which causes the darling tone stage to obtain sufficient base voltage to generate the level of a main disconnect current Imns which charges the capacitors CGSQ,, Cem, in the power transistor Q1 so that the buffer output signal OUTLSB rises to a limit level disconnection, whereby the power transistor Q1 is disconnected.

Due to the first switching A of the control signal IN1 at time t, the buffer circuit a disconnect current IDE consisting of said main disconnect current Iqum and an additional disconnect current IQ "according to a block 64 in the flow chart. The main disconnect current Iam" is generated in Q7, Q8 when circuit Q5, Q6 outputs a base current Im to the input 50 generated in the current driving darling tone circuit second on the darling tone circuit, which base current Im is generated in the sixth inverting signal N2 on is converted to the high voltage level VCCH.I-Iuvud cut-off current 107m6 which reaches the second transistor The input inductive load current IL i of the darling tone circuit 50 is equal to the moment of disconnection, of the total current generated in the transistors Q?, Q8 of the darling tone circuit.

The main disconnect current 101m is supplied to the input G1 of the driving transistor Q1 to rapidly discharge the first capacitance Com, so that the voltage OUTLSB at the input G1 rises to a sufficiently high level for the transistor Q1 to be disconnected, as in the flow chart.

The I-Iuud disconnection current is so large that the voltage OUTLSB at the input G1 rises above a limit level DISh. above the DISM limit, the driving transistor Q1 is safely disconnected. Due to the charge which the main disconnection current IQ-m supplies to the first capacitance C080, the voltage at the input G1 increases to a disconnection interval DISMSOUTLSBSVCCH in which the power transistor Q1 is safely disconnected.

The main disconnect current Ioma supplies the input G1 with charge until the output voltage OUT has dropped to OV.

The main disconnect current also charges the second capacitance specified in box 66 of the CGDQ, to the voltage VCCI-I.

In order for the darling tone circuit Q7, Q8 to conduct the main disconnection current, it must have sufficient base voltage Um + Um ß 1.6V. When the voltage OUTLSB has risen above the high supply voltage minus the base voltage to conduct so that the base voltage Um + Um is lower is 1.6V, the darling tone circuit Q7, Q8 ceases to conduct current. Further discharge of the first capacitance COW, so that the voltage OUTLSB at the input G1 rises all the way to the disconnection level VCCH, takes place with the additional disconnection current IQ, which is generated in the fourth transistor Q4 in the first inverting circuit when the buffer input signal INLSB has the low level VG.

In summary, the darling tone circuit Q7, Q8 need both said base current Im and said base voltage Um + Um to generate the main disconnect current. According to the previous description, it is an interaction between the two inverting circuits that creates the base voltage that the darlington circuit needs to generate current.

Collaboration is achieved by adjusting the inverting circuits with a certain time offset. 10 15 20 25 30 35 17 502 435 In the signal diagram, the total disconnection current Ims is illustrated by a current spike at the time point tz. The process, with discharge of the first capacitance Cm, and charging of the second capacitance Com ', is thus very fast for the voltage OUTLSB to disconnect the driving transistor Q1 in a stable manner. The described method of charging the capacitances of the power transistor Q1 with the disconnection current Im, is included in box 66 of the flow chart.

When the disconnection process is completed and the power transistor Q1, which is the driving transistor in the receiving output stage, is thus disconnected, the lowering transistor Q2 is switched on by switching the switching signal OUTBUFF to the logic voltage level VLS.

The generation of the switching signal OUTBUFF takes place in the simpler buffer circuit BUFF. By delaying the switching signal OUTBUFF, the changeover to the logic voltage VLS is generated at time th, shortly after the switching off of the drive transistor Q1.

When the lowering transistor Q2 is switched on, it supplies the load 12 with the low supply voltage OV, so that the output voltage OUT has a low level, OV. The inductive load current IL is conducted through the lowering transistor Q2 in the direction from the load 12 to the transistor Q2.

The current driving buffer circuit 24 is also designed for connecting the driving transistor Q1. However, just before switching on the driving transistor Q1, the lowering transistor Q2 is disconnected by switching the buffer output signal OUTBUFF to the low voltage level OV at time t1. When the lowering transistor Q2 is switched off, the inductive load O drives the very fast voltage OUT. change level to the high supply voltage VCCH so that the energy in the load L can be discharged via the first diode D1 in the driving transistor Q1. During the discharge process, the voltage OUT rises at the output up to and including a few volts above the high level VCCH so that the first diode can then conduct current. previously OUTBUFF is switched according to the Buffer output signal 10 15 20 25 30 35 502 435 1 ”the description at times th and t, in order for the switching of the lowering transistor Q2 to take place after the driving transistor Q1 has been switched off and for the driving to be switched on. the lowering transistor has been disconnected. How delay of the connection can be achieved in practice is described in detail in the transistor Q1 after this connection to Figures 6 and 7.

When the disconnection of the lowering transistor Q2 is completed and the output voltage OUT has the high level VCCH, a procedure is started for switching on the driving transistor Q1.

The switching method is initiated by a second switch B, at time t1, of the control signal INI, 68 in the flow chart.

Thereby, in the level shifting circuit 22 corresponding to the first conversion F of the buffer input signal INLSB is generated to the high level VCCH, the first inverted signal N1 and the second inverted signal NZ being converted to the low level VREG.

However, the conversion of the inverted signals N1, N2 also does not occur. The input capacitance of the ninth transistor Q9 is charged faster than the input capacitance of the first transistor Q1. The first transistor Q1 has much larger input capacitance than the instantaneous one and not at the same time as the ninth transistor Q9. By the input capacitance is meant both the capacitance between the G and D connection and between the G and S connection on the respective transistor. The faster charging of the capacitance of the ninth transistor Q9 causes a voltage difference between the G-terminal G9 of the ninth transistor and the S-terminal S9. The voltage difference becomes large enough for the ninth transistor Q9 to generate and conduct a main coupling current IQ, which charges the first capacitor COSQ, and the second capacitor Com, in the driving transistor Q1, until the voltage OUTLSB at its input G1 drops below a CONM at driving transistor Q1 limit level to which it is connected. The main switching current IQ, ceases when the voltage - OUTLSB at the output 56 of the ninth transistor drops so low that it is within a switching interval VREGSOUTLSB5CONM of the driving transistor Q1. The driving transistor Q1 is in this position switched on and conducts the inductive load current IL through the load 12. During the switching procedure, the buffer input signal INLSB has the high voltage level VCCH, the third transistor Q3 in the first inverting circuit generating and conducting an additional switching current switching current Iæ is used to further charge the capacitances of the driving transistor Q1 so that the voltage level OUTLSB at the input G1 drops all the way down to a switching level. VREG for the driving transistor. The voltage level OUTLSB is stabilized at the switching level'VREG until the next time the driving transistor Q1 is switched off.

IQ3. The eXtra In total, a connection current Iam is thus generated which consists of the main connection current IQ, and the additional connection current LW according to box 70 in the flow chart.

The connection current Iam charges, as previously mentioned, the capacitances of the driving transistor Q1 so that the voltage at its input G1 drops to the connection level VREG, whereby the transistor is switched on according to box 72 in the flow chart in Figure 3.

In the signal diagram in Fig. 4, the switching current is Iom. which charges the capacitances of the driving transistor Qi illustrated.

The method described above shows how the current driving buffer circuit 24 disconnects and turns on the driving transistor Q1 in dependence on the control signal IN1.

Figure 5 shows a block diagram of a second embodiment of a voltage-switching drive device according to the invention.

The drive device comprises a simple output stage 74 connected to the inductive load 12 and a second control circuit 76 connected to the output stage.

The simple output stage 74 comprises only one transistor, the driving transistor Q1. Instead of the lowering transistor in the 2 ° reception output stage in Fig. 1, a third diode D3 is connected in the simple output stage 74. The driving transistor Q1 is connected in the simple output stage in the same way as in the receiving output stage. The third diode D3 is connected between the ground terminal and the D terminal transistor Q1. The output 16 of the single output stage is connected to the D-terminal of the driving transistor Q1. The third diode D3 is connected to conduct current in the direction from ground to the output stage 16. on the driving The control circuit 76 in Figure 5 corresponds to the control circuit in Figure 1, except that it contains only those circuits CL, LS, LSB which are connected to the driving transistor Q1. The clock circuit CL, the level shifting circuit LS and the current driving buffer circuit LSB function in the same manner as previously described.

The disconnection of the driving transistor Q1 in the single output stage takes place in the same way as the disconnection of the driving transistor in the receiving output stage. The current-carrying buffer circuit operates in an identical manner, the disconnection method described earlier with reference to the signaling diagram in Figure 4 also applying to the simple output stage.

Upon disconnection of the driving transistor Q1, the output voltage OUT drops very rapidly below OV so that the third diode D3 can start conducting the inductive current L_for discharging the energy stored in the inductive load 12. When the energy is discharged, the third diode D3 ceases. to conduct current and the output voltage OUT is OV. When it is time to turn on the driving transistor at the next time t, in the signaling diagram in Fig. 4, the driving transistor Q1 must "pull" the output 16 high. In the simple output stage 74, it is thus the connection of the driving transistor Q1 which converts the voltage OUT at the output 16 to the high level VCCH. (In the receiving output stage, the disconnection of the lowering connection of the driving transistor Q1 was reversed once, at already at Q2.) In the simple voltage OUT transistor 10 15 20 25 30 21 502 435 the receiving output stage 74, the current driving buffer circuit 24 operates almost exactly on the same methods previously described. However, the switching current Iam performs a large discharge of the second capacitance Com, since the potential at the output 16 must be changed from 0V to VCCH when the driving transistor Q1 through the driving is switched on. The load current transistor Q1 also helps to change the voltage at the output.

The following is a brief summary of the procedure according to the flow chart in Figure 3. The starting position is according to box 58 that the control signal IN1 has the high voltage level VLS and the buffer output signal OUTLSB has the low voltage level VREG with the power transistor Q1 connected.

A first method step, described in box 60, is a first changeover A of the control signal IN1 so that it transitions to the low voltage level OV. This first switching A initiates the disconnection of the power transistor Q1.

A second method step, described in box 64, is to generate a disconnect current Ims for disconnecting the power transistor Q1. The disconnection current ïm consists of said main disconnection current IQIW and of the additional disconnection current Ia.

A third procedural step, in accordance with. with box 66, is that the disconnection current Im; is output to the power transistor Q1 and charges capacitances therein, the voltage OUTLSB at the input G1 of the power transistor rising to the high level VCCH whereby the power transistor Q1 is switched off.

Box 68 describes a fourth method step which involves a second switching B of the control signal IN1 so that its voltage level transitions to the high level VLS to initiate the connection of the power transistor Q1. fifth A fifth method step is described in box 70. The method step consists of generating a connection current LN "which consists of a main connection current IW and an additional connection current Im.

The last procedure step according to the flow chart is described in box 72. The procedure step the connection current Iam charges the power transistor Q1 so that the voltage OUTLSB at its input drops to the low level VREG whereby the power transistor Q1 last consists in switching on the capacitances in.

After the last procedure step, the procedure is repeated from the first procedure step in which the control signal is switched to the low level OV.

Figure 6 shows a third embodiment of how the current-carrying buffer circuit according to the invention can be used in an electric voltage-switching drive device with inductive load. The device in Figure 6 comprises the same receiving output stage 10 as in Figure 1. The inductive load 12 and the capacitors C, are the same as in Figure 1 and in the same way connected to the high supply voltage VCCH. The control circuit 78 in Figure 6, on the other hand, looks different but has the same overall function, to alternately switch on and off the lowering transistor so that the load 12 is supplied with the voltage VCCH and alternately with the voltage OV. The driving and alternating control circuit 78 includes, in addition to the current driving buffer circuit 24, a plurality of circuits for causing the driving transistor Q1 to be turned on shortly after the lowering transistor Q2 is turned off while the lowering transistor Q2 is turned on shortly after driving transistor Q1 has been disconnected. The device in Figure 6 is described below. It is available, apart from the driving buffer circuit 24, also described in the Swedish patent application SE 9301974-3.

The control circuit 78 includes a clock circuit 20 (CLOCK) for generating a control signal CL, which is used to control the disconnection of the transistors. According to the example, the control signal CL consists of a clock signal with periodically recurring, equally long, clock pulses. One clock pulse edge is used to control the disconnection of the driving transistor and the other clock edge is used to control the disconnection of the lowering transistor. When the respective transistor is switched off, the inductive load drives the output voltage OUT to change level, which is used in the control circuit. The control signal CL can also have shorter or longer pulses.

The control signal CL is supplied to a first input 80 of a non-overlapping circuit 82, which is arranged to generate a first clock signal CLD and a second clock signal CLU, which, however, are equal to the control signal CL when the device is operated continuously. The first clock signal CLD is output from a first output 84, while the second clock signal CLU is output from a second output 86. The non-overlapping circuit 82 is used to generate the first clock signal CLD and the second clock signal CLU offset from the start. controlling signal CL.

The clock circuit 20 in the control equipment 78 thus controls the disconnection of the transistors Q1, Q2 in the receiving output stage 10. To control the connection of the transistors, the control circuit includes a level sensing circuit 88. The function of the level sensing circuit 88 is to delay the connection of the transistors Q1, Q2 is switched on first when the level of the output voltage has changed to a high level after the lowering transistor Q2 has been switched off, the lowering transistor Q2 is only switched on when the level of the output voltage has changed to a low level after the driving transistor Q1 has been switched off. To control the connection of the OUT to and correspondingly the transistors, the output voltage is sensed to the level sensing circuit 88 in the control equipment 78.

The level sensing circuit 88 (SENSE) has an input 90 connected to the output of the output stage 16. The sensing circuit 88 has a first output 92 at which an OUT is sensed for sensing the output voltage. 10 15 20 25 30 835 502 435 24 low limit signal OUTL for controlling the switching on of the lowering transistor Q2. The sensing circuit 88 has a second output 94 on which a high limit signal OUTH is emitted to control the switching on of the driving transistor Q1. The limit signals OUTL, OUTH indicate when the output voltage OUT has reached a limit level at which the output voltage OUT is defined as high and dropped to a level at which the output voltage is defined as low. The level sensing circuit 88 is described in more detail in the Swedish patent application SE 9301975-0.

The control circuit 78 also includes a first switching circuit 96 (PULL DOWN) for switching the switching transistor Q2 on and off. The first switching circuit 96 receives at a first input 98 the low limit signal OUTL from the sensing circuit 88.

The voltage levels of the low limit signal OUTL are adapted to the voltage levels in the first switching circuit 96. At a clock pulse input 100, the first switching circuit 96 receives said first clock signal CLD. At a second input 102, the first control circuit 96 receives a disconnection signal TD to temporarily disconnect the influence of the low limit signal OUTL on the first control circuit 96 at the start of the control circuit 78. At start-up, the first clock signal CLD controls both switching on and off of the lowering transistor Q1. At an output 104 of the first switching circuit 96, a first switching signal DOWNOUT is applied to the input G2 of the lowering transistor in the receiving output stage 10 for switching the lowering transistor Q2 on and off.

The control circuit 78 includes a second switching circuit 106 (PULL UP) for controlling the connection and disconnection of the driving transistor Q1. The second switching circuit 106 receives at a first input 108 the high limit signal OUTH from the sensing circuit 88. The high levels of the high limit signal OUTH are matched to the voltage levels i. The second switching circuit 106. At a clock pulse input 110 the second control circuit CLUs 106 receives a second control circuit CL. At a second input 112, the second control circuit 106 receives a level-adjusted switch-off signal TD "to temporarily disconnect the effect of the high limit signal OUTH on the first switching circuit 30 when starting the control equipment 78 on the first switching circuit 30. The level-adapted signals are adapted to the voltages at which the second switching circuit 106 operates. At start-up, the level-adapted second clock signal CLUU thereby controls the on and off switching of the driving transistor Q1. At a output 114 of the second switching circuit 106, a second switching signal UPOUT is output, which is used to control the switching on and off of the driving transistor Q1.

For the connection and disconnection of the driving transistor Q1, said current driving buffer circuit 24 and an inverting circuit 116 are also included in the control circuit 78. The inverting circuit 116 is connected to the output 114 of the switching circuit 106 and the input 34 of the current driving buffer circuit 24. The buffer circuit 36 previously described manner connected to transistor Q1. between the second input G1 of the driver A first level change circuit 118 (LS) converts the voltage levels of the second clock signal CLU so that they are adapted to the voltage levels at which the second switching circuit 106 operates. The first level change circuit 118 outputs the level-matched second clock signal CLUw to the clock pulse input 110 of the second switching circuit 106.

The control equipment 78 also comprises a disconnect circuit 120 (TIMER DISABLE), which is used to during said start-up process both disconnect the effect of the sensing circuit 88 on the switching circuits 96, 106 and influence the non-overlapping circuit 82 to generate the first and the second clock signal CLD. , CLU offset relative to the control signal CL.

The disconnection circuit 120 outputs the aforementioned disconnection signal TD to the second input 102 of the first switching circuit 96. The disconnection signal TD is also output to a second level change circuit 122 (LS) which converts the disconnection signal voltage levels so that they are adapted to the second levels. 106 works with. The level-matched disconnect signal TD "is supplied to the second input 112 of the" second switching circuit 106 ".

Finally, the disconnection signal TD is also supplied to a second input 124 of the non-overlapping circuit 82 to activate it during the start-up process.

The operation in continuous operation of the drive device in Figure 6 with the current driving buffer circuit 24 according to the invention is described in more detail below with reference to the signaling diagram in Figure 7. The current driving buffer circuit 24 operates in exactly the manner described in connection with Figures 2, 3 and 4. this detailed description is not repeated here.

The functional description in connection with Figure 7, however, comprises the overall function of the buffer circuit 24 in the drive device in Figure 6.

The signal diagram in Figure 7 shows at the top the disconnection signal TD.

From the moment the device works in continuous operation CONT.

The disconnection signal TD then has a low level and the device works with feedback of the output voltage OUT to the control equipment 78, which switches on the transistors depending on the OUT level of the output voltage.

The first clock signal CLD and the second clock signal CLU are in continuous operation identical to the control signal CL, which is shown in the signal diagram in Figure 7. The control signal CL comprises continuously recurring pulses of high level corresponding to the logic voltage VLS. Between the pulses, the control signal has a low level corresponding to 0 V. At time tu the clock signal changes from low to high level, which is shown in the figure with a first edge M. At time tu it returns from high to low level, which is shown in the figure with a second edge N. The time between two consecutive first edges M corresponds to the control signal CL period T (20 us) and the pulses last for half the period time.

The signal diagram in Figure 4 also shows the output voltage OUT. Between the time t0 and the time tu, the lowering transistor Q2 is switched on and conducts current, the output voltage being low. At time tu, the lowering transistor Q2 is disconnected, the current-carrying load 12 driving the output voltage OUT to change from low to high level. The switch-off of the lowering transistor is controlled by the first flank M. of the clock pulse. At a time tu the driving transistor Q1 is switched on, which connection is controlled by the high limit signal OUTH from the sensing circuit 88. At the time tu the driving transistor Q1 is switched off. 12 drives the output voltage OUT to change from high to low level. The disconnection of the driving transistor is controlled by the second edge N of the clock pulse. At a time tu, the lowering transistor Q2 is finally switched on, which connection is controlled by the low limit signal OUTL from the sensing circuit 88.

The drive device is designed so that only one of the transistors in the receiving output stage leads at a time. To achieve this, the inductive load is used to drive the output voltage OUT to change the level when the respective transistor is switched off. The control equipment 78 controls the switching on of the transistors so that the driving transistor Q1 is switched on after the lowering Q2 has been switched off, when the output voltage has been changed from low to high level. Correspondingly, the lowering transistor Q2 is switched on after the driving transistor Q1 has been switched off, when the output voltage OUT has been changed from high to low level. Switching on of the driving transistor Q1 may take place at the earliest when the output voltage OUT has increased to a higher limit level H, the time tu in the signaling scheme for the output voltage OUT, after the lowering transistor Q2 has been switched off. Switching on of the lowering transistor Q2 may take place at the earliest when the output voltage OUT has dropped to a lower limit level L, the time tu in the signaling scheme for the output voltage OUT, after the driving transistor Q1 has been switched off. The connection of the two transistors is controlled by the output voltage OUT being fed back to the sensing circuit 88. The sensing circuit is arranged. to control, connection of the respective transistor so that the connection takes place when the output voltage OUT has fallen below the lower limit level L and when the output voltage has exceeded the higher limit level H in the manner previously described. The connection and disconnection of the driving transistor Q1 takes place under the influence of the driving buffer circuit 24 in the control circuit 78.

The signal diagram in Fig. 7 shows the low limit signal OUTL and the high limit signal OUTH from the sensing circuit 88, which signals are used to control the connection of the two transistors.

The limit signals OUTL, OUTH change level, from high to low at time tu, when the output voltage OUT reaches the higher limit level H after the lowering transistor Q2 has been switched off.

The limit signals OUTL, OUTH return to a high level, at time tu, when the output voltage OUT has dropped to the lower limit level L after the driving transistor Q1 has been disconnected.

The signal diagram in Figure 7 shows the first switching signal DOWNOUT, which is output from the first switching circuit 96 for switching the switching transistor Q2 on and off. The switching signal DOWNOUT is affected at time tu by the first edge M of the clock signal CL, so that the switching signal DOWNOUT changes to a low level, marked with J in the figure, whereby the lowering transistor Q2 is switched off. The fact that the low limit signal OUTL switches to low level at time tu does not affect the first switching signal DOWNOUT. At the time tu, when the output voltage OUT has dropped to a low level, a second level shift F is generated in the OUTL, which thereby influences the first switching signal DOWNOUT to lower the transistor Q2. The first switching signal DOWNOUT is affected by the low limit signal OUTL to change from low to high level, marked with I in the figure, whereby the lowering transistor Q2 is switched on. The connection of the lowering transistor Q2 has thereby been delayed until the output voltage level OUT has dropped to the lower limit level L, after the driving transistor Q1 the low limit signal to turn it on is switched off at the time tu.

The signal diagram in Figure 7 also shows the buffer input signal INLSB which comes from the second switching circuit 106 and is inverted in the inverter 116. The buffer input signal INLSB influences, in the manner previously described, the current driving buffer circuit 24 to switch on and off it. driving transistor Q1.

The buffer input signal INLSB is affected by the second edge N of the clock signal CL to change to low level at time t ”, marked with P in the figure. The buffer input signal INLSB from the inverting circuit 116 then transitions to the low level VREG, the current driving buffer circuit disconnecting the driving transistor Q1 in the manner previously described. The fact that the high limit signal OUTH at time t "changes to a high level does not affect the buffer input signal INLSB.

At the time tm when the output voltage OUT has increased to a high level, a first level shift E is generated in the high limit signal OUTI-I which affects the buffer input signal INLSB to be converted to the high level VCCH, marked with K in controlling the connection of the driving transistor. The buffer input signal INLSB is inverted according to the invention in the current driving buffer circuit 24, the decreasing output signal OUTLSB from the current driving buffer circuit 24 the transistor in the manner previously described. the connection of the driving transistor is thus, with the control device 78, delayed until the output voltage level OUT has reached the higher limit level H, after the lowering transistor Q2 has been switched off at the time tu. In the first embodiment shown in Figure 1, the control circuit 14 is simplified to make the description of the current buffer circuit 24 clear. The control circuit 78 according to Figure 6 is more complicated and practically feasible. The time designations used in Fig. 7 for the control circuit 78 in Fig. 6 do not fully correspond to the designations in Fig. 4 regarding the control circuit 14 in Fig. 1. In Fig. 4 the disconnection time of the driving transistor Q1 is denoted by tz, while the corresponding time in Fig. 7 is denoted t ”. In Fig. 4, the switch-on time of the driving transistor Q1 is denoted by t ", while the corresponding time in Fig. 7 is denoted by t".

In the signal diagram in figure 7 for the continuous operation CONT. 10 502 435 so it is thus shown that the switching off of the transistors is controlled by level changes in the control signal CL. The connection of the transistors is not controlled by the control signal but instead by the limit signals OUTL, OUTH in order to cause the connection of one transistor to be delayed, so that it does not take place at the same time as the disconnection of the other transistor in the final stage.

This eliminates the risk of simultaneous conduction of current through both transistors.

The invention is of course not limited to the embodiments described above and shown in the drawings, but can be modified within the scope of the appended claims.

Claims (34)

10 15 20 25 30 35 31 502 435 PÄTBNTKRAV A method in a voltage-switching drive device comprising a control circuit and an output stage with at least one transistor (Q1), for alternately switching on and off the transistor (Q1) with the control circuit, which output stage has an output (16) connected to an inductive load (12) , and which method comprises the method steps: - switching on the transistor (Q1), the output of the output stage (16) being connected to a high supply voltage (VCCH) and the transistor (Q1) conducting a load current (IL) inductive load (12); - disconnection of the transistor (Q1), the output of the output stage (16) being connected to a low supply voltage (earth), characterized in that the method comprises those through the further method steps: - initiating the disconnection of the transistor (Q1) by a first changeover ( A) of a control signal in the control circuit; a main disconnect current (Iam) in a current generating circuit (Q,, 0,) in which the main disconnection current corresponds to the load current (IL) through the inductive load (12), and - delivering the main disconnection current (IQ7_Q,) to a control input (G1) on the transistor ( Q1) so that a first capacitance (Ccsw) is discharged very quickly, whereby the voltage level (OUTLSB) at the input of the transistor (G1) is switched to a disconnection interval (DIShs0UTLSB5VCCI-I), whereby the transistor (Q1) is disconnected. - generation of the control circuit, in the transistor (Q1) Method according to claim 1, characterized in that said generation of the main disconnection current (IQ-ms) takes place by the following method steps: - generation of a base voltage (UWHJN) by interaction between a first and a second inverting circuit (Q3, Q4, Q5, Q6) at a first changeover (A) of a control signal in the control circuit; - generating a base current (Im) in the second inverting circuit (Q5, Q6) of the controller at said first switching (A) n signal, and - outputting said base voltage (Um + Uu), and said base current (Im) to the current generating circuit (Q7, Q8) thereby generating the main disconnect current (Imng. Method according to claim 1, characterized by the following method steps: - generating a main switching current (LW) in the control circuit, which generation is initiated by a second switching (B) of the control signal, and - charging the main switching current (Iæ) so that the voltage level (OUTLSB) on the control input (G1) of the transistor (Q1) is switched to a switching interval (VREG50UTLSB $ CONhQ, whereby the transistor (Q1) is switched on. the first capacitance (Cmng with Method according to claim 3, characterized by: - generating an additional disconnection current (IQQ to further discharge the first capacitance (CQQ in the transistor (Q1) so that (otrrLsB) on is stabilized at a disconnection level (VCCH), and - generation of an additional connection current (IQQ to further charge the first capacitance (Cmmg in the transistor (Q1) so that (OUTLSB) on is stabilized at a connection level (VREG). voltage level control input (G1) voltage level control input (G1) Method in a voltage-switching drive device comprising a control circuit and a receiving output stage with an output (16) connected to a live inductive load (12), for switching on and off with a control signal via the control circuit alternately a driving transistor (Q1) and a lowering transistor (Q2) in the receiving output stage so that the transistors (Q1, Q2) are alternately connected, which method comprises the method steps: - connecting the output output stage (16) to a high supply voltage (VCCH) by switching on the driving transistor, which in the switched-on position conducts a load current (IL) through the inductive load (12); 10 15 20 25 30 35 33 502 435 - connection of the output (16) of the receiving output stage to a low supply voltage (earth) by switching on the lowering transistor (Q2), - switching of the voltage level (OUTLSB) at an input (G1) to the driving the transistor (Q1) for connecting and disconnecting it, characterized by the further method steps: - initiating the disconnection of the driving transistor (Q1) by a first changeover (A) of the control signal; - generating a main disconnection current (lqun) in the control circuit, which main disconnection current corresponds to the load current (IL) through the inductive load (l2); outputting the main cut-off current (IQUN) to the control input (G1) on the driving transistor (Q1) so that a first capacitance (Cmng in the driving transistor (Q1) is discharged very quickly at the same time as a second capacitance (cmmg in the driving transistor (Q1) is charged very rapidly whereby the voltage level (OUTLSB) at the input of the driving transistor (G1) is switched to a disconnection interval (DI & hsOUTLSBsVCCH) whereby the driving transistor (Q1) is disconnected; - generation of a switching current (Iam) in the second circuit (LSB) switching (B) the control signal (IN1) and charging the first 'capacitance switching current (Iam) so that the voltage level (OUTLSB) on the control input of the driving transistor (G1) is switched to a switching interval (VREGs0UTLSB5CONJ, where the driving ) is connected (COSQI) with Method according to claim 5, characterized by: for further discharging the first capacitance (cmmg in the driving transistor so that the voltage level (OUTLSB) at the control input (G1) is stabilized at a disconnection level (VCCH), - generating an additional disconnection current ( IQQ Method according to claim 5, characterized by: - generating an additional switching current (IQQ to further charge the first capacitance (CQQQ in the driving transistor so that the voltage level (OUTLSB) on the control input ( G1) is stabilized at a connection level (VREG). An electrical voltage switching drive device comprising an output stage and an electrical control circuit, said output stage comprising a transistor (Q1) being connected to an inductive load (12) and to the control circuit, and which control circuit comprises a current driving buffer circuit (LSE) arranged depending on a control signal (INLSB) alternately switching on and off the transistor (Q1), the transistor (Q1) in the switched position connecting the output of the output stage (16) to a high supply voltage (VCCH), while the output (16) is connected to a low supply voltage (earth) when the transistor (Q1) is in the switched off position, which control signal (INLSB) with a first switch (E) controls the switch-off of the transistor (Q1) and with a second switch (F) controls the switching on of the transistor (Q1), k characterized in that said current buffer circuit (LSB) comprises: - an input (34) for receiving the control signal (INLSB); - an output (36) for outputting a buffer output signal (OUTLSB) to a control input (G1) on the transistor (Q1); - a first inverting circuit (Q3, Q4) which is connected to the input (34) and arranged to output a first inverted signal (N1) at an output (44); (Q5, Q6) connected to the input (34) and arranged to output at a output (48) a second - a second inverting circuit inverted signal (N2), and - a current generating circuit (Q7, Q8) connected to the output (36) on the current driving buffer circuit (LSB) and is further connected to the output (44) of the first inverting circuit and to the output (48) of the second inverting circuit, and said current generating circuit is arranged that in the first switching (E) of the control signal (INLSB) receives said inverted signals (N1, N2) and thereby generates a main disconnect current (IQHM) which is output to the output (36) whereby capacitances (Cmm, Cmng in the power transistor (Q1) are charged so that the buffer output signal (OUTLSB) increases 15 20 25 30 35 502 435 switch-off interval (DI & msOUTLSB5VCCH), whereby the power transistor (Q1) is switched off. Device according to claim 8, characterized in that said second inverting circuit (Q5, Q6) connected to the current generating circuit (Q7, Q8), is arranged to emit a base current (INLSB) during said first changeover (E) of the control signal (INLSB). IW) to the current generating circuit, to initiate the generation of said main disconnect current (lqux). Device according to claim 9, characterized in that said current driving buffer circuit (LSB) further comprises: - a semiconducting element (Q9), which is connected to the two outputs (44,48) of the inverting circuits, and arranged to said second switching (F) of the control signal (INLSB) receiving the inverted buffer inputs (N1, N2) and thereby generating a main switching current (LW) which charges the (CQQUCGNQ in the transistor (Q1) so that the buffer output signal (OUTLSB) is switched to a CON ¿0UTLSB2VREG) for switching on the transistor (Ql). 11. ll. Device according to claim 10, characterized in that the first inverting circuit (Q3, Q4) is also arranged to generate an additional disconnection current (Im) when the transistor (Q1) is switched off in order to further charge the capacitors (C0 "n, CGmm) in the transistor. so that the buffer output signal (OUTLSB) is stabilized at a disconnection level (VCCH). Device according to claim 10, characterized in that the first inverting circuit (Q3, Q4) is also arranged that when switching on the transistor (Q1) additional switching current (IQQ) to further charge the capacitors in the transistor so that the buffer output signal (OUTLSB) (Cosql f Canon) stabilized at a connection level (VREG) 10 15 20 25 30 502 435 26 Device according to claim 10, characterized in that the first inverting circuit (Q3, Q4) is a C-MOS inverter. Device according to claim 10, characterized in that it (Q3, Q4) is a C-MOS inverter. second inverting circuit Device according to claim 10, characterized in that the current generating circuit (Q7, Q8) comprises a first bipolar transistor (Q7) of NPN type connected to a second bipolar transistor (Q8) of NPN type. Device according to claim 10, characterized in that said semiconductor element (Q9) consists of a p-channel MOS transistor. Electrical current buffer circuit (LSB) for switching and disconnecting a driving transistor (Q1) in a receiving output stage (10) with an output (16) connected to a current-carrying inductive load, depending on a buffer input signal (INLSB), which receiving output stage is connected to a lowering transistor (Q2), the connection between the two transistors constituting said output (16), which transistors are alternately switched on and off, whereby when the driving transistor (Q1) is switched off an output voltage (OUT) on the output output stage (2) of the transistor is switched on and connected. the output of the receiving output stage comprises the driving transistor (Q1) decreasing, the lowering to a low supply voltage (earth), and when the lowering of the lowering transistor (Q2) the voltage at the output of the receiving output stage (15) connects the output of the receiving output stage to a high supply voltage (V) characterized in that said driving buffer circuit (LSB) comprises - an input (34) for receiving the buffer input signal (INLSB), which with a first switch (E) controls the disconnection of it increases, the driving transistor being switched on and the driving transistor (Q1) and with a second switch (F) controlling the switching on of the driving transistor (Q1); An output (36) for outputting a buffer output signal (OUTLSB) to an input (G1) of the driving transistor (Q1); - a first inverting circuit (Q3, Q4) which inverts the received buffer input signal (OUTLSB) and outputs a first inverted signal (N1); - a second inverting circuit (Q5, Q6), which receives the buffer input signal (INLSB) and outputs a second inverted signal (N2): - a current generating circuit (Q7, Q8) which is partly connected to the output (36) of the buffer circuit and partly connected to said inverting circuits for receiving the first and second inverting signals (N1, N2), which current generating circuit at said first switching (E) of the buffer input signal (INLSB) is arranged to supply a main disconnect current (Imm) to the output (36) for charge capacitances (C0 'n, CGmm) in the driving transistor (Q1) so that the buffer output signal (OUTLSB) increases to a disconnection interval (DI & h20UTLSB5VCCH), whereby the drive transistor is disconnected; a semiconductor element (Q9) connected to said first and second inverting circuit, which semiconductor element in the second switching (F) of the buffer input signal (INLSB) is arranged to supply a main connection current (IQ) to the output (36) for charging (CGSQUCGDQI). ) in the driving transistor (Q1) so that. the buffer output signal (OUTLSB) is switched to at least one limit level (CONM) for switching on the (Q1), said capacitances driving the transistor, the driving transistor being switched on. Device according to claim 17, characterized in that the first inverting circuit (Q3, Q4) is also arranged to generate an additional disconnection current (IW) for charging the capacitances (CQQUCQNQ in the driving transistor) when the driving transistor (Q1) is disconnected. that the buffer output signal (OUTLSB) is stabilized at a disconnection level (VCCH), that a further 10 15 20 25 30 502 435 38 Device according to claim 17, characterized in that the first inverting circuit (Q3, Q4) is also arranged to generate an additional switching current (103) when the driving transistor (Q1) is switched on in order to further charge the capacitors (CGSQHCGDQQ in the driving the transistor so that the buffer output signal (OUTLSB) is stabilized at a switching level (VREG). Device according to claim 17, characterized in that said second inverting circuit (Q5, Q6) connected to the current generating circuit (Q7, Q8) is arranged to emit a base current (ELSB) during said first changeover (E) of the control signal (INLSB). IW) to the current generating circuit, to initiate the generation of said main disconnect current (IQ-hm). 21. A device according to claim 17, characterized in that the current generating circuit (Q7, Q8) is constituted by a darling tone circuit. Device according to claim 17, characterized in that (Q7, Q8) NPN-type bipolar transistor (Q7) is connected to a second NPN-type bipolar transistor (Q8). that the current generating circuit comprises a first 23. A device according to claim 17, characterized in that said semiconductor element (Q9) consists of a p-channel MOS transistor. 24.. Electrical voltage-switching drive device with a live inductive load, which device comprises a receiving output stage (Q1, Q2) connected to the inductive load (12) and an electrical control circuit connected to the receiving output stage which is influenced by a controlling signal (IN1), which receiving output stage is characterized by comprises a driving transistor (Q1) connected to a lowering transistor (Q2), which transistors are connected between a positive pole and a negative pole of a first voltage generator (V1), the connection between the transistors constituting an output (16) of the receiving output stage, which inductive load (12) is connected between the output (16) of the output stage and a connection (18) of a voltage source (C1, V1) and which control circuit is connected to a first input (G1) of the receiving output stage and to a second input (G2) on the receiving output stage to alternately switch on and off the transistors (Q1, Q2) so that the output voltage (OUT) on the output of the output stage changes between the high voltage (VCCH) at the positive terminal of the voltage generator (V1) and the low voltage (ground) at the negative pole of the voltage generator, the voltage level being high (VCCH) when the driving transistor (Q1) is switched on and low (ground) when the lowering the transistor (Q2) is connected, which control circuit comprises a current driving buffer circuit (LSB) for switching on and off the driving transistor (Q1) and which control circuit is to generate a buffer input signal (INLSB) to the current driving buffer circuit (LSB) characterized said current buffer circuit (LSB) comprises: - an input (34) for receiving the buffer input signal (INLSB) which with a first switch (E) controls the disconnection of the driving transistor (Q1) and with a second switch (F) controls the switching of the driving transistor; - an output (36) for outputting a buffer output signal (OUTLSB) to an input (G1) of the driving transistor (Q1); - a first inverting circuit (Q3, Q4) which inverts the received buffer input signal (INLSB) and outputs a first inverted arranged signal (N1); a second inverting circuit (Q5, Q6), which receives the buffer input signal (INLSB) and outputs a second inverted signal (N2): - a current generating circuit (Q7, Q8) connected to said inverting circuits for receiving the first and the second inverting signal (N1, N2), which current generating circuit in said first switching (E) of the buffer input signal (INLSB) is arranged to generate a main disconnect current (IQMW) which charges capacitances (Cæm, Cmg in the driving transistor (Q1) so that the buffer output signal (OUTLSB) increases to a disconnection interval (DI & m20UTLSBsVCCH) the drive transistor is disconnected, and - a semiconductor element (Q9) connected to said first and thereby second inverting circuit, which semiconductor element at the second switch (F) of the buffer input signal (INLSB) is arranged to generate a main connection current (Im) for charging said capacitances (C¿ & v, C0mm) in the driving transistor (Q1) so that the buffer output signal (OUTLSB) is switched s at least to a limit level (CONÉ for switching on the driving transistor (Q1), whereby the driving transistor is switched on. Device according to claim 24, characterized in that the first inverting circuit (Q3, Q4) is also arranged to, when disconnecting the driving transistor (Q1), generate an additional disconnecting current (Im) for further charging the capacitances (CGQUCGNQ in the driving the transistor so that the buffer output signal (OUTLSB) is stabilized at a disconnection level (vccn). Device according to claim 24, characterized in that the first inverting circuit (Q3, Q4) is also arranged to generate a switching current (Iæ) for charging in the driving transistor when the driving transistor (Q1) is switched on. so that the additional capacitances (Cæm, CmnQ buffer output signal (OUTLSB) are further stabilized at a switching level (VREG). Device according to claim 24, characterized in that the first inverting circuit (Q3, Q4) is a C-MOS inverter. Device according to claim 24, characterized in that it (Q5, Q6) is a C-MOS inverter. second inverting circuit Device according to claim 24, characterized in that the current generating circuit (Q7, Q8) first NPN-type bipolar transistor (Q7) is connected to a second NPN-type bipolar transistor (Q8). includes a 10 15 20 25 30 35 41 502 455 Device according to claim 24, characterized in that said semiconductor element (Q9) consists of a p-channel MOS transistor. Electrical current buffer circuit (24) for switching and disconnecting a driving transistor (Q1) in a receiving output stage (10) connected to an inductive load (12), depending on a buffer input signal (INLSB), characterized by - an input (34 ) for receiving the buffer input signal (INLSB), which with a first switching (E) controls the disconnection of the driving transistor (Q1) and with a second switching (F) controls the switching on of the driving transistor (Q1); - an output (36) for outputting a buffer output signal (OUTLSB) to a control input (G1) on the driving transistor (Q1); - a first inverting circuit (Q3, Q4) which inverts the received buffer input signal (OUTLSB) and outputs at an output (44) a first inverted buffer input signal (N1); second (Q5, Q6), the buffer input signal (INLSB) and at an output (48) outputs a second inverted buffer input signal (N2); a current generating circuit (Q7, Q8) connected to the output (36) of the buffer circuit and connected to the outputs (44, 48) of said inverting circuits for receiving the first and the second inverting signal (N1, N2), which current generating circuit at said first switching (E) of the buffer input signal (INLSB) is arranged to generate a main disconnect current (IQUN) and output said main disconnection current to (36), the main disconnection current charging capacitances (Cbn, C0mn) in the driving transistor (Q1) so that the buffer output signal (OUT) to one (nïshzourLsßsvccn), the drive transistor is disconnected; a semiconductor element (Q9) connected to said first and second inverting circuit, said semiconductor element at it - an inverting circuit which receives the output disconnection interval, the second switching (F) of the buffer input signal (INLSB) being arranged to generate a main connection current (IQQ to charge said capacitances (qmm, CmQ in the driving transistor (Q1) so that the buffer output signal (OUTLSB) is switched to at least one limit level (CONJ for switching on the driving transistor (Q1) whereby the driving transistor is switched on. . 32. Electrical voltage-switching drive device characterized by: - an output stage with a transistor (Q1), which output stage has an output (16) connected to an inductive load (12) and which transistor is arranged to alternately be in the switched-on position and alternately in disconnected mode; a current driving buffer circuit (LSB) which driving buffer circuit is arranged to be connected to said output stage, alternately connecting and disconnecting the transistor (Q1) the transistor (Q1) in the connected position connects the output stage (16) to a high supply voltage while the output (VC) 16) is connected to a low supply voltage (ground) when the transistor (Q1) is switched off, the buffer circuit comprises: wherein in which current - an input (34) for receiving a buffer input signal (INLSB), which with a first switch (E) controls the disconnection of the driving transistor (Q1) and with a second changeover (F) controls the switching on of the driving transistor (Q1); - an output (36) for outputting a buffer output signal (OUTLSB) to a control input (G1) on the driving transistor (Q1); - a first inverting circuit (Q3, Q4) which inverts the received buffer input signal (OUTLSB) and outputs at an output (44) a first inverted buffer input signal (N1); "One (Q5, Q6), the buffer input signal (INLSB) and at an output (48) outputs a second second inverting circuit which receives inverted buffer input signal (N2); a current generating circuit (Q7, Q8) connected to the output (36) of the buffer circuit and connected to the outputs (44, 48) of said inverting circuits for receiving the first and the second inverting signal (N1, N2), which current generating circuit at said first switching (E) of the buffer input signal (INLSB) is arranged to generate a main disconnect current (IQHN) and output to the output (36), said main disconnection current 10 charging the main disconnection current charging capacitances (Cbmw, C0mnor) in the driving Q1) so that the buffer output (OUTLSB) increases to a disconnection interval (DI & hz0UTLSBsVCCH), whereby the drive transistor is disconnected; a semiconductor element (Q9) connected to said first and second inverting circuit, which semiconductor element in the second changeover (F) of the buffer input signal (INLSB) is arranged to generate a main connection current (1,29) for charging said capacitances (CQQHCQNQ in the driving transistor (Q1) so that the buffer output signal (OUTLSB) is switched to at least one limit level (CONHQ for switching on the driving transistor (Q1), whereby the driving transistor is switched on. 33. A method in a voltage-switching drive device, for switching and disconnecting with a control circuit alternately a transistor (Q1) in an output stage, which output stage has an output (16) connected to an inductive load (12), characterized by the method steps: - switching on the transistor (Q1), the output stage (16) being connected to a high supply voltage (VCCH) and the transistor (Q1) conducting the inductive load (12); a load current (IL) through it - disconnecting the transistor (Q1), the output of the output stage (16) being connected to a low supply voltage (earth); a first changeover (A) of a control signal (IN1) in the control circuit initiates the disconnection of the transistor (Q1); (Iqmg) in which main disconnect current (Q1fQs) 1 main disconnect current corresponds to the load current (I¿) through the inductive load (12), and - generating a current generating circuit control circuit, - outputting the main disconnecting current (IQMW) to a control input (G1) Q1) so that a first capacitance (cmnü voltage level (OUTLSB) at the input of the transistor (G1) is converted to a disconnection interval (DISMSOUTLSBSVCCH), whereby the transistor (Q1) is disconnected in the transistor (Q1) very quickly, whereby 44 50 Method according to claim 33, characterized by the following method steps: 4 - generating a main switching current (Im) in the control circuit by a second switching (B) of the control signal (IN1) and - charging the first capacitance (Cag with the main switching current ( Im) so that the voltage level (OUTLSB) control input (G1) is switched to a (VREGs0UTLSB $ CONmJ., Whereby the transistor on the switching interval of the transistor (Q1) is switched on.