JP2006187138A - High side drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high side drive circuit for driving a high side switch efficiently at a high speed through a relatively simple arrangement. <P>SOLUTION: Transistors Q7 and Q8, diodes D1 and D2, capacitors C1 and C2, and a transformer T1 constitute a trigger signal generating section for transforming a PWM signal into a trigger signal. A diode D3 and a capacitor C3 constitute a bootstrap section for turning an N channel transistor Q5 on/off at high speed as a high side power supply. Resistors R1 and R2, diodes D4-D8, transistors Q1 and Q2, and N channel transistors Q3 and Q4 constitute a high side driving signal generating section for transforming a trigger signal V3 into a driving signal of the N channel transistor Q5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a high-side drive circuit that drives a high-side switch to perform on / off control of a power supply.

  As a high-side drive circuit that drives a high-side switch based on a PWM signal, two drive circuits described below have been conventionally known.

The first is a high-side drive circuit (first conventional circuit) that drives the high-side switch by shifting the PWM signal from the low-side to the high-side by a dedicated high-side drive IC.
FIG. 4 is a block diagram of a conventionally known high-side drive circuit using a drive IC. In the high-side drive circuit shown in FIG. 4, the PWM signal that can be given from the PWM signal generation IC (PWM) that operates at 5V or 3.3V is level-shifted by the drive IC that operates at 12V, and serves as a high-side switch. N channel transistor Q5 is driven.

The second is a high-side drive circuit (second conventional circuit) that drives the high-side switch by level-shifting the PWM signal using a power drive transformer.
FIG. 5 is a block diagram of a conventionally known high-side drive circuit using a power drive transformer. In the high-side drive circuit shown in FIG. 5, the PWM signal (V1) is amplified by the power amplifier 22, and the power drive transformer T10 is level-shifted to a signal that can control the N-channel transistor Q5 as the high-side switch. .
An application example of such a high-side drive circuit is disclosed in Non-Patent Document 1 below.

Renesas website (http://www.renesas.com/), synchronous rectification type phase shift full bridge control IC, product number: data of HA16163T

  By the way, in the first conventional circuit described above, there is a limit to the capability of the level shift circuit that can be mounted in the driving IC, and the switching frequency and the level that can be output by the driving IC are limited. Some applications may not be applicable.

In the second conventional circuit described above, the power amplifier 22 is required to drive the power drive transformer T10. Further, since it is necessary to shift the PWM signal to a level at which the N-channel transistor Q5 can be driven, a relatively large transformer is required. Therefore, transformer excitation loss, copper loss, etc. cannot be ignored.
Also, since the peak current during switching is large, oscillation may occur due to the leakage inductance of the transformer, and it is practically difficult to drive the switching element at high speed.

  Accordingly, an object of the present invention is to provide a high-side drive circuit for driving a high-side switch at high speed and efficiently with a relatively simple configuration.

  In order to overcome the above problems, the present invention provides a first N-channel transistor as a high-side switch, a second N-channel transistor as a low-side switch, and a connection between a first node and a first power supply terminal. A first capacitor connected between the first node and the first node, a second capacitor connected between the first node and a reference terminal, an input terminal to which a PWM signal is applied, and the first node; The first and second capacitors invert and insulate and transmit the first trigger signal generated by alternately repeating charging and discharging according to the rise / fall of the PWM signal to the secondary winding. The second trigger signal is connected between the transformer, the first power supply terminal, and the second node having a negative potential among the nodes connected to the secondary winding, and the second N-channel transistor is on A third capacitor that is charged by the first power source when in the off state, and that supplies a drive voltage to the gate of the second N-channel transistor when in the off state; and a drain connected to the third capacitor; Is connected to the gate of the first N-channel transistor and the third node having a positive potential among the nodes connected to the secondary winding, and the drain is A fourth N-channel transistor connected to the gate of the first N-channel transistor to turn off the first N-channel transistor in the on state, and an electric signal from the first power supply terminal And a first switching element for controlling a conduction state between the first power supply terminal and the gate of the third N-channel transistor, The conduction state between the gate of the third N-channel transistor and the second node is controlled according to the polarity of the third node, and the operation threshold voltage is lower than that of the fourth N-channel transistor. And a second switching element.

  Preferably, the first and second switching elements are bipolar transistors, a collector of the second switching element is connected to a base and an emitter of the first switching element, and the second switching element is When in the on state, the first switching element is in the off state.

  Preferably, level shift means is provided between the third node and the base of the second switching element.

  Preferably, a control terminal is connected to the input terminal, and a third switching element in which a conduction state between the first power supply terminal and the fourth node is controlled according to a level of the control terminal, and a control A fourth switching element having a terminal connected to the input terminal, and a conduction state between the reference terminal and the fourth node controlled according to a level of the control terminal; Are connected to the third node via the primary winding.

  According to the present invention, since a small pulse transformer is used as the transformer, the first N-channel transistor as the high-side switch can be driven at high speed and efficiently.

Hereinafter, an embodiment of a high-side drive circuit according to the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram of a high-side drive circuit 1 according to the embodiment.

In the following description of the embodiments, the N-channel transistors Q5, Q6, Q3, and Q4 correspond to the first, second, third, and fourth N-channel transistors of the present invention, respectively.
The transformer T1 corresponds to the transformer of the present invention.
The transistors Q1 and Q2 correspond to first and second switching elements of the present invention, respectively.
Capacitors C1, C2, and C3 correspond to the first, second, and third capacitors of the present invention, respectively.
The node 101 corresponds to the first power supply terminal of the present invention. Nodes 103, 104, 105, and 111 correspond to the first, second, third, and fourth nodes of the present invention, respectively.

  The high-side drive circuit 1 drives an N-channel transistor Q5 as an output high-side power FET based on the PWM signal V1 applied to the input terminal 100, and a high voltage having the same duty ratio as the input PWM signal. This is a circuit for obtaining (for example, 100 V) from the output terminal 200. The N-channel transistor Q6 as a low-side switch can be controlled independently from the high-side side by a terminal 120.

  In FIG. 1, Vcc of about 12 V is applied to the terminal 101, for example. The terminal 102 is a ground terminal.

Hereinafter, the configuration of the high side drive circuit 1 will be described.

(1) Trigger Signal Generation Unit In FIG. 1, transistors Q7 and Q8, diodes D1 and D2, capacitors C1 and C2, and transformer T1 constitute a trigger signal generation unit.
Transistors Q7 and Q8 are transistors for current amplification of the PWM signal. The capacitors C1 and C2 are capacitors for charging and discharging with a small capacity of about several tens to several hundreds pF. The diodes D1 and D2 are diodes for resetting the transformer T1.

  Input terminal 100 is connected to the bases of transistors Q7 and Q8. The emitters of the transistors Q7 and Q8 are connected to each other through a node 111. The collector of transistor Q7 and terminal 101 are connected. The collector of transistor Q8 is connected to terminal 102.

The primary winding of the transformer T1 is connected to the nodes 111 and 103.
The capacitor C1 and the diode D1 are connected in parallel between the node 103 and the terminal 101. Capacitor C2 and diode D2 are connected in parallel between node 103 and terminal 102.

When the PWM signal V1 changes from the L level (low level) to the H level (high level), the NPN transistor Q7 is turned on and the PNP transistor Q8 is turned off. As a result, the capacitor C2 is charged and the capacitor C1 is discharged along the path of the primary winding of the terminal 101 → the transistor Q7 → the node 111 → the transformer T1.
Since the capacitance of the capacitors C1, C2 is small, after charge and discharge was completed within a very short time, and resetting the transformer T1 by the forward voltage V _F of the diode D1.

When the PWM signal V1 changes from the H level to the L level, the PNP transistor Q8 is turned on and the NPN transistor Q7 is turned off. As a result, the capacitor C1 is charged and the capacitor C2 is discharged along the path of the terminal 101 → the capacitor C1 → the node 103 → the primary winding of the transformer T1 → the transistor Q8.
Since the capacitance of the capacitors C1, C2 is small, after charge and discharge was completed within a very short time, and resetting the transformer T1 by the forward voltage V _F of the diode D2.

  With the above operation, a trigger signal is generated in which the voltage V2 applied to the primary winding of the transformer T1 is alternately inverted at the timing corresponding to the rising / falling of the input PWM signal.

The transformer T1 insulates and inverts the trigger signal generated in the primary winding and transmits it to the secondary winding side. As shown in FIG. 1, the secondary winding of transformer T <b> 1 is connected to nodes 104 and 105.
In the high side drive circuit of the present invention, the turns ratio of the transformer T1 can be freely set. However, in the high side drive circuit 1 according to the embodiment, the case of 1: 1 will be described as an example. Therefore, a voltage V3 obtained by inverting the voltage V2 as it is is generated in the secondary winding of the transformer T1.
A schematic waveform of the signal of voltage V3 is displayed in FIG.

In the high-side drive circuit 1, since the charging / discharging time of the capacitors C1 and C2 is very short, even when the inductance component of the primary winding of the transformer T1 is reduced, the exciting current of the transformer T1 accompanying the voltage V2 is almost none. Few. Therefore, since the core of the transformer T1 can be reduced, the loss in the transformer T1 can be reduced.
Therefore, it is possible to use a small pulse transformer as the transformer T1 and mount it on the substrate as an SMD.

(2) Bootstrap Unit In FIG. 1, the diode D3 and the capacitor C3 constitute a bootstrap unit.
The bootstrap unit functions as a high-side power source for quickly charging and discharging the gate charge of the N-channel transistor Q5 by the N-channel transistors Q3 and Q4, and turning the N-channel transistor Q5 on and off at high speed.
Capacitor C3 has an upper end connected to node 112 and the other end connected to node 104, which is one end of the secondary winding of transformer T1.

  The diode D3 is a diode for preventing a reverse leakage current from being generated from the capacitor C3 to the terminal 101 by the high-side voltage charged in the capacitor C3. Therefore, the diode D3 has an anode connected to the terminal 101 and a cathode connected to the node 112 that is one end of the capacitor C3.

When the low-side N-channel transistor Q6 is on, the capacitor C3 is charged from Vcc via the diode D3 → node 112 to generate a high-side power supply.
When the high-side N-channel transistor Q5 is turned on, the N-channel transistor Q3 is turned on, so that the charging voltage of the capacitor C3 is quickly applied to the gate of the N-channel transistor Q5.

(3) Drive Signal Generation Unit In FIG. 1, resistors R1 and R2, diodes D4 to D8, transistors Q1 and Q2, and N-channel transistors Q3 and Q4 constitute a high-side drive signal generation unit.
The drive signal generation unit is a circuit for converting the trigger signal V3 generated in the secondary winding of the transformer T1 into a drive signal for driving the N-channel transistor Q5.

The N-channel transistor Q3 is a control transistor that is turned on when the PWM signal is at the H level, charges the gate capacitance of the N-channel transistor Q5 with the voltage of the capacitor C3, and turns on the N-channel transistor Q5.
As shown in FIG. 1, the gate of N-channel transistor Q3 is connected to the emitter of transistor Q1. The drain is connected to the collector of the transistor Q1. The source is connected to the drain of N channel transistor Q4 via node 110 and to the gate of N channel transistor Q5.

The N-channel transistor Q4 is a control transistor that is turned on when the PWM signal is at L level, draws out the gate charge of the N-channel transistor Q5, and turns off the N-channel transistor Q5. When the PWM signal is at the H level, it is turned off and the gate voltage of the N channel transistor Q5 is maintained.
As shown in FIG. 1, the gate of the N-channel transistor Q4 is connected to a node 105 at one end of the secondary winding of the transformer T1. The drain is connected to the source of N channel transistor Q3 via node 110 and to the gate of N channel transistor Q5. The source is connected to node 104 at one end of the secondary winding of transformer T1.

The transistor Q1 is a control transistor for controlling the gate voltage of the N-channel transistor Q3.
As shown in FIG. 1, the base of the transistor Q1 is connected to the node 112 at one end of the capacitor C3 through the node 108 and the resistor R2, and is connected to the collector of the transistor Q2 through the diode D7. The collector is connected to the node 112 at one end of the capacitor C3. The emitter is connected to the collector of transistor Q2 via diode D8.
When the PWM signal becomes H level, the base current is supplied to the transistor Q1 according to the voltage of the capacitor C3 and the resistor R2 serving as the base resistance, and the transistor Q1 is turned on. As a result, the voltage of the capacitor C3 is supplied to the gate of the N-channel transistor Q3, and the N-channel transistor Q3 is turned on.

The transistor Q2 is a control transistor for controlling the gate voltage of the N channel transistor Q3.
The base of transistor Q2 is connected to node 105, which is one end of the secondary winding of transformer T1, via node 106 and diodes D5 and D6. The emitter is connected to a node 104 which is one end of the secondary winding of the transformer T1.
When the PWM signal becomes L level, the potential of the node 106 becomes a positive potential determined according to Vcc, the diode D3, and the resistor R1, and the transistor Q2 is turned on. As a result, equal forward voltages are generated in the diodes D7 and D8, and the base-emitter voltage of the transistor Q1 becomes almost zero, so that the transistor Q1 is turned off. Therefore, N channel transistor Q3 is turned off.
When the PWM signal becomes H level, the trigger signal voltage V3 becomes negative and the potential of the node 106 also becomes negative, so that the transistor Q2 is turned off. Thereby, the transistor Q1 is kept on, and the N-channel transistor Q3 is kept on.
Therefore, N channel transistor Q3 is controlled in accordance with the conduction state of transistor Q2.

Transistors Q1 and Q2 are bipolar transistors with respect to N-channel transistors Q3 and Q4. This is because a high-speed switching is possible as a control transistor.
Further, the operation threshold voltage (V _BE : usually about 0.7V) of the transistor Q2 is made lower than the operation threshold voltage (V _GS : 2.5V or more) of the N-channel transistor Q4, so that the N-channel transistor Q4 and the transistor Q2 This is also for shifting the switching timing.

  For example, when the PWM signal changes from the H level to the L level, the trigger signal voltage V3 increases, so that the transistor Q2 is turned on and the N-channel transistor Q4 is turned on. If the transistor Q4 is not turned on before the transistor Q4, the transistor Q1 and the N channel transistor Q3 cannot be turned off before the N channel transistor Q4 is turned on, and both the N channel transistors Q3 and Q4 are turned on. Will occur. When both N-channel transistors Q3 and Q4 are turned on, a through current is generated in a path of Vcc → Q3 → Q4 → ground level, the efficiency of the high side drive circuit 1 is deteriorated, and power loss is caused.

Immediately after the PWM signal changes from the H level to the L level, the transistor Q2 and the N channel transistor Q4 are turned on, and the transistor Q1 and the N channel transistor Q3 are turned off. Thereafter, when the trigger signal voltage V3 gradually decreases, if the transistor Q2 is turned off before the N-channel transistor Q4, a through current is generated in the path of Vcc → Q3 → Q4 → ground. As a result, the efficiency of the high-side drive circuit 1 deteriorates and power loss occurs. Therefore, in such a case, the N channel transistor Q4 is turned off before the transistor Q2, so that the V _GS of the N channel transistor Q5 is maintained at 0 V during the reset period of the transformer T1.

  As shown in FIG. 1, the drive signal generator includes diodes D5 and D6 between a node 105 that is one end of the secondary winding of the transformer T1 and a node 106 that has the same potential as the base of the transistor Q2. Is connected. The diodes D5 and D6 constitute a level shift circuit.

This level shift circuit is set to raise the base potential of the transistor Q2.
For example, immediately after the PWM signal changes from the H level to the L level, the trigger signal voltage V3 rises quickly, and then the voltage V3 gradually decreases due to the charging of the capacitor C1 and the discharging of C2, and the reset period of the transformer T1 However, during the reset period, the level is slightly negative due to the influence of the diode D2. For example, since the potential of the node 105 is about −1V, even in such a case, the level shift circuit is set to increase the base potential of the transistor Q2 so that the transistor Q1 and the N-channel transistor Q3 are not turned on during the reset period. Has been.

Operation of High Side Drive Circuit 1 Next, the operation of the high side drive circuit 1 will be described with reference to FIG.
FIG. 2 is a timing chart for explaining the operation of the high-side drive circuit 1, wherein (a) shows the PWM signal voltage V1, (b) shows the voltage at the node 111, (c) shows the trigger signal voltage V2 and V3, (d) shows the V _GS of the N-channel transistor Q3, and (e) shows the V _GS of the N-channel transistor Q5.

  FIG. 2 shows signal waveforms for a period from a certain time 92.7 μsec to a time 96.1 μsec when a PWM signal of about 9 V is applied.

(1) Time period from 92.7 μsec to 92.8 μsec In this period, in order to reset the transformer T1, | V3 | ≦ V _F + Vces ≦ 1.4V (Vces: collector-emitter saturation voltage of Q7, Q8) and It has become.
Since the trigger signal voltage V3 is the gate-source voltage of the N-channel transistor Q4, the N-channel transistor Q4 is off.
On the other hand, the base current is supplied to the transistor Q2 via Vcc → diode D3 → resistor R1, and the transistor Q2 is turned on. At that time, since both the diodes D7 and D8 are turned on, the base-emitter voltage of the transistor Q1 is almost 0, and the transistor Q1 is turned off.

As a result of turning on the transistor Q2 and the diode D8, the charge of the capacitor between the gate and the source of the N-channel transistor Q3 is discharged via the transistor Q2, so that the N-channel transistor Q3 is turned off.
Since the N-channel transistor Q4 is off, the gate charge of the N-channel transistor Q5, which is a high-side power FET, cannot be charged / discharged. As shown in FIG. The V _GS voltage is maintained at the H level.

(2) Time period from 92.8 μsec to 93.1 μsec As shown in FIG. 2A, when the PWM signal V1 falls from the H level to the L level, the capacitor C1 is charged and the capacitor C2 is discharged. As shown in FIG. 2C, the trigger signal voltage V2 suddenly drops, and the trigger signal voltage V3 obtained by inverting V2 by the transformer T1 rises rapidly.

The transistor Q2 and the N-channel transistor Q4 are turned on by the rapid rise of the trigger signal voltage V3. As a result, the gate charge between the gate and source of the N-channel transistor Q5 is rapidly discharged, and the V _GS voltage of the N-channel transistor Q5 rapidly decreases as shown in FIG. Turn off.

  As can be seen from the waveform of V3 in FIG. 2 (c), once the trigger signal voltage V3 suddenly rises, it depends on the inductance components of the capacitors C1 and C2 and the transformer T1 as the capacitor C1 is charged and discharged. The level of V3 gradually decreases due to the attenuation curve determined.

When the trigger signal voltage V3 further decreases to about 2 V or less (near time 93.1 μsec), the N-channel transistor Q4 is turned off before the transistor Q2. Since N-channel transistor Q3 is still off, the V _GS voltage of N-channel transistor Q5 does not change. Therefore, the N-channel transistor Q5 maintains the state of V _GS = 0V until the PWM signal is switched to the H level again after being turned off at time 92.9 μsec.

(3) Time period from 93.1 μsec to 94.0 μsec Further, the trigger signal voltage V3 further decreases and the transformer T1 is reset, so that | V3 | ≦ V _F + Vces ≦ 1.4V. During this reset period, V _GS of N-channel transistor Q5 is maintained at 0V.

(4) Period from Time 94.0 μsec to 94.1 μsec At time 94.0 μsec, the PWM signal V1 changes from L level to H level as shown in FIG. As a result, the capacitor C1 is discharged and the capacitor C2 is charged. As a result, as shown in FIG. 2C, the trigger signal voltage V2 rapidly rises, and the trigger signal voltage V3 obtained by inverting the V2 by the transformer T1 suddenly drops. To do.

When the forward voltage of the diode D5 is V _{F and} the breakdown voltage of the diode D6 is V _Z , the node 106 is maintained at a potential higher than the node 105 by (V _F + V _Z ), while the diode D4 is turned on. to the base potential of the transistor Q2 is clamped to -V _F. Therefore, the trigger signal voltage V3 is clamped to − (2V _F + V _Z ).

  As a result, since the transistor Q2 is turned off, the diodes D7 and D8 are also turned off. The transistor Q1 is turned on by a base current whose resistance is the resistor R2. As soon as the transistor Q1 is turned on, the N-channel transistor Q3 is rapidly turned on to charge the gate capacitor of the N-channel transistor Q5, and the N-channel transistor Q5 is quickly turned on as shown in FIG.

(5) Time period from 94.1 μsec to 94.9 μsec Next, as the capacitor C1 is discharged, the negative width of the trigger signal voltage V3 becomes smaller and is raised by (V _F + V _Z ) with respect to V3. The base voltage of the transistor Q2 is gradually increased. When the base voltage of the transistor Q2 is higher than the positive V _F, the transistor Q2 is turned on again.
At this time, since the transistor Q2 is configured to be turned on before the N-channel transistor Q4, the transistor Q1 is turned off while the N-channel transistor Q4 is turned off. As a result, both N-channel transistors Q3 and Q4 are turned off, and the timing at which the PWM signal falls next (94.9 μsec), that is, N-channel transistor Q5 is kept on until a positive trigger signal voltage is generated. To do.

As described above, the configuration and operation of the high-side drive circuit according to the present embodiment can be achieved by using a pulse transformer without using a power drive transformer when transmitting a PWM signal (drive signal) to the high side. Since the width of the transmission signal (trigger signal) is short, the power (excitation power, etc.) required for driving the transformer is very small, and a high-efficiency high-side drive circuit can be realized.
That is, since the capacitors C1 and C2 have a small capacity and a very short charge / discharge time, even when the inductance of the primary winding of the transformer T1 is reduced, the exciting current of the transformer T1 due to the input voltage is almost small. Therefore, the core of the transformer T1 can be made very small and there is almost no loss in the transformer T1.

  According to the high-side drive circuit according to the present embodiment, less power is required to drive the transformer, so that the transformer can be made into a small SMD type, and thus the drive circuit can be downsized as a whole.

  According to the high side drive circuit according to the present embodiment, since the drive power supply is generated by the bootstrap method, an independent power supply is not required when driving the high side switch. Therefore, power supply noise caused by the high-side drive power supply is not generated.

  According to the high-side drive circuit according to the present embodiment, since the time width of the trigger signal is extremely small, it is possible to deal with PWM waveforms having a wide range of duty ratios and quick response time. Therefore, it can be applied to a switching power supply with a high frequency of 500 kHz or more.

The present invention can be applied by making various modifications without being limited to the contents of the above-described embodiment.
For example, as described above, in the high-side drive circuit 1 shown in FIG. 1, paying attention to the fact that the drive power for converting the PWM signal into the trigger signal can be very small, the high-side drive shown in FIG. The circuit 1 may be simplified.

FIG. 3 shows an improved example of the high-side drive circuit 1.
The high side drive circuit shown in FIG. 3 is different from the high side drive circuit 1 shown in FIG. 1 in that the transistors Q7 and Q8 in the input section are omitted. As shown in FIG. 3, the transformer T1 may be directly driven by a PWM signal. As a result, the high-side drive circuit 1 can be further reduced in cost and size.

It is an example which shows the circuit structure of the high side drive circuit which concerns on embodiment. 6 is a timing chart showing the operation of the high-side drive circuit according to the embodiment. It is an example which shows the circuit structure of the high side drive circuit which concerns on embodiment. It is an example which shows the circuit structure of the conventional high side drive circuit. It is an example which shows the circuit structure of the conventional high side drive circuit.

Explanation of symbols

  T1 ... Transformer, D1-D8 ... Diode, R1-R2 ... Resistance, C1-C3 ... Capacitor, Q1-Q2, Q7-Q8 ... Transistor, Q3-Q6 ... N-channel transistor.

Claims (4)

A first N-channel transistor as a high-side switch;
A second N-channel transistor as a low-side switch;
A first capacitor connected between a first node and a first power supply terminal; a second capacitor connected between the first node and a reference terminal;
A primary winding is connected between an input terminal to which a PWM signal is applied and the first node, and the first and second capacitors alternately repeat charging and discharging according to the rise / fall of the PWM signal. A transformer that inverts and insulates the generated first trigger signal and transmits it to the secondary winding to generate a second trigger signal;
The first power supply terminal is connected between the second node having a negative potential among the nodes connected to the secondary winding, and the first N-channel transistor is in an ON state. A third capacitor that is charged by the power source of the second power source and supplies a driving voltage to the gate of the second N-channel transistor when the power source is off.
A third N-channel transistor having a drain connected to the third capacitor and a source connected to the gate of the first N-channel transistor;
Of the nodes connected to the secondary winding, a gate is connected to a third node having a positive potential, a drain is connected to a gate of the first N-channel transistor, and in an on state, the first A fourth N-channel transistor for turning off the N-channel transistor;
A first switching element for controlling a conduction state between the first power supply terminal and the gate of the third N-channel transistor in response to an electrical signal from the first power supply terminal;
The conduction state between the gate of the third N-channel transistor and the second node is controlled according to the polarity of the third node, and the operation threshold voltage is higher than that of the fourth N-channel transistor. A low second switching element;
A high-side drive circuit comprising: The first and second switching elements are bipolar transistors;
A collector of the second switching element and a base and an emitter of the first switching element are respectively connected;
The high-side drive circuit according to claim 1, wherein the first switching element is turned off when the second switching element is turned on. The high-side drive circuit according to claim 1, wherein level shift means is provided between the third node and a base of the second switching element. A third switching element, wherein a control terminal is connected to the input terminal, and a conduction state between the first power supply terminal and the fourth node is controlled according to a level of the control terminal;
A control terminal connected to the input terminal, and a fourth switching element in which a conduction state between the reference terminal and the fourth node is controlled according to a level of the control terminal;
The high side drive circuit according to claim 1, wherein the fourth node is connected to the third node via the primary winding.

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