SE470392B - Method and device for writing and reading data in a memory, method and device for the transfer of data from a synchronous digital hierarchical system to a plesiochronous digital hierarchical system and method and device for adjusting the rate of reading of data from a FIFO register - Google Patents

Abstract

This invention concerns the technical field of digital telecommunications. In particular the invention concerns synchronous and plesiochronous digital hierarchical systems and a method and device for transferring information between such systems. The device according to the invention consists of an asynchronous buffer which separates the SDH system from the PDH system. The data signal entering the buffer DATAin can contain a so-called bit adjustment. In bit adjustment the incoming data signal is contained in a frame with one bit more than nominal or one bit less than nominal. The rate of writing into the buffer varies depending upon whether bit adjustment takes place or not. In order to regulate the rate of reading from the buffer so that it follows the rate of writing, the device comprises a FIFO register in which writing and reading of the data information takes place. For writing write addresses WADR are generated and for reading read addresses RADR are generated. The device comprises an average value calculator 38 which generates average value addresses AVADR around which the write addresses WADR oscillate. If the write addresses WADR as a result of the bit adjustment deviate too much from the average value addresses AVADR then the generation of average value addresses AVADR is hastened or delayed in stages so that the write addresses again oscillate within permitted limits around the average value addresses. The generated average value addresses are used in order to adjust the reading rate. If the read address deviates too much from the average value address then the reading speed out of the buffer is too high, whereupon the reading is stopped temporarily so that the rate of reading becomes the same as the rate of writing. The device comprises a first phase detector 33 for controlling the average value calculator 38 and a second phase detector 40 for regulating the speed of reading from the FIFO register. <IMAGE>

Description

15 20 25 30 .r -, 2 4/0 ó 9 2 can, for example, be realized so that the read clock always runs too fast, whereby the phase error signal indicates that the lock clock is to be stopped by one clock pulse. In the prior art, it is realized so that the phase error signal has a fairly regular pattern.

Such a circuit is described in U.S. Pat. No. 4,941,156. In this circuit, the read clock is synchronized with the write clock through a phase-locked circuit. The read clock is generated by a crystal-controlled oscillator in the phase-locked circuit. The crystal controlled oscillator is in turn controlled by coupled capacitors which are switched step by step to change the frequency of the read clock, depending on the difference between the two counters.

THE INVENTION In new types of digital transmission systems including SDH (Synchronous Digital Hierarchy) systems and PDH (Plesiochron Digital Hierarchy) systems, the rate difference between several signals incoming to the SDH system is evened out so that these incoming signals can be switched within SDH. system. The rate differences are due to the fact that the rate of the incoming signals is generated by different oscillators and these can never be tuned so that they operate at exactly the same frequency. A small deviation from a nominal frequency associated with the systems always occurs. For the PDH system, a maximum permissible deviation from the nominal frequency is specified. The equalization of the rate difference was achieved by so-called bit adjustments whereby an extra bit is inserted into a frame or a bit is subtracted from the frame. After the equalization of the rate difference by bit adjustments, the incoming signals are completely synchronous and can be switched in, for example, a cross-coupling matrix in the SDH system. When the signals are switched in the SDH system, they are delivered to an asynchronous buffer at the output of the SDK system, at the transition from the SDH system to the PDH system. As a result of said bit adjustment, a bit more or less than normal is added to the asynchronous buffer per frame. It is also entered a bit more or less than normal per frame. In the buffer, therefore, the readout rate must be regulated so that it corresponds to the write-in rate. After reading from the buffer, the signals for continued transmission are multiplexed.

Such bit adjustments occur relatively rarely. If a device according to the prior art is used to regulate the readout rate in systems where the bit adjustments described above occur, the following happens. As long as there is no bit adjustment on the signal incoming to the buffer, the phase error signal in the prior art device has a fairly regular, even pattern, but when a bit adjustment is present, the phase detector detects a phase error in the data register and there is a jump in the phase error signal pattern. These jumps on the phase error signal cause jerk: at the readout rate, which in turn causes problematic jitter on the buffer output. The problem with jitter arises because the time between two bit adjustments is much greater than the time constant in the phase-locked circuit in an ordinary digital demultiplexer.

The invention solves the jitter problem, which arises as a result of the bit adjustments described above, by a so-called bit leakage method and a device for performing the bit leakage.

The device which consists of an asynchronous buffer comprises, as in the prior art, a FIFO register with associated write counters and read counters for generating write addresses and read addresses.

According to the invention, the asynchronous buffer further comprises a mean value counter and a first and a second phase detector, respectively. The averaging counter generates averaging addresses around which the generated writing addresses oscillate. The write addresses correspond on average to the average addresses. However, due to the bit adjustments, the generated write addresses will deviate more than allowed from the average addresses. The write addresses are allowed to vary within certain limits, but if the write address assumes a limit value, according to the invention a regulation of the average value counter takes place. In that phase detector, write addresses and averaging addresses are detected. There, the detected write address is also compared with a front and rear address limit value calculated in relation to the simultaneously detected average address. The averaging counter is gradually controlled by an averaging address if the writing address assumes one of these limit values so that the averaging counter on average follows the writing counter and continuously generates addresses which constitute averaging of the writing addresses. The previously mentioned bit leakage corresponds to the stepwise control of the average value counter as a result of bit adjustments. In the second phase detector, generated read addresses and mean value addresses are detected. In the second phase detector, the detected read address is also compared with a stuff limit value calculated in relation to the simultaneously detected value address. If the read address assumes said stuff limit value, the second phase detector emits a phase error signal which indicates that the reading rate from the buffer is too high, whereby the reading is stopped during a read clock pulse. The reading rate is thus regulated in relation to the enrollment rate so that the reading rate is on average as high as the enrollment rate.

The idea of the invention is to regulate the rate of the reading by comparing the reading address with an average value address instead of, as in the prior art, directly comparing the reading address with the writing address.

The average address addresses follow the write addresses and their rate variations, but sudden rate changes, as a result of bit adjustments, are transmitted to the average value counter in several small steps so that the change in the generation of average value addresses has a "smoother" course than the change in generating write addresses. When the reading address is then compared with the average value address for regulating the reading rate, it is advantageous that there are not very sudden changes in the average value addresses.

The changes that still occur when the generation of average addresses is accelerated or delayed in small steps do indeed cause jitter, but it is within the permitted limit and does not cause problems. With the device according to the invention, the readout rate from the buffer is regulated without troublesome jitter occurring. This is achieved by using the average value counter in such a way that the phase error signal from the other phase detector has a relatively even pattern without excessive jumps. As a result, the jerks in the reading rate become so small that the jitter that these jerks cause is within the permitted limits. The invention will now be described in more detail by means of a preferred embodiment and with reference to the accompanying drawing.

DESCRIPTION OF THE FIGURES Figure 1 shows two parts of a plesiochronous digital hierarchical system cooperating with a synchronous digital hierarchical system.

Figure 2 shows information divided into frames in the systems.

Figure 3 illustrates prior art for writing and reading information in a memory.

Figure 4 shows a device according to the invention.

Figure 5 illustrates a cyclical sequence of write addresses.

Figure 6 illustrates a cyclical sequence of read addresses.

Figure 7 illustrates in a diagram generated write addresses and average addresses.

Figure 8 illustrates the relationship between mean addresses, write addresses and front and back limits.

Figure 9 illustrates in two diagrams accelerated generation of mean-value addresses and delayed generation of dis-addresses.

Figure 10 shows a more detailed view of the first phase detector in the device according to the invention.

Figure 11 illustrates in three diagrams average address addresses, read addresses and stuff limit values.

Preferred embodiment Figure 1 shows a so-called digital cross connect system (DCC system) which includes two parts of a digital plesiochronous digital hierarchical system (PDH system) that cooperates with a synchronous digital hierarchical system (SDH system). The DCC system comprises a first synchronizing unit SU1 connected to an input of a cross-switching unit SW in which switching of signals takes place and a second synchronizing unit SU2 connected to an output of the DCC unit. The first synchronization unit SU1 receives data DATAIN on a transmission line with a transmission speed of 140 Mb / s. Incoming data DATAIN arrives at the synchronization unit in the PDH system. Incoming data is demultiplexed in several steps (a demultiplexer DEMUX is shown in the figure) until it has a bit rate of approx. 2 Hb / s. These demultiplexed signals are in the figure denoted DS1. The rate of the demultiplexed signals may differ from a bit rate of 2 Mb within the telephony. The nominal bit rate is 2,048 Mb / s. When the signals are to be switched in the crossover unit SW, they must be completely synchronous. In order to even out the rate differences between these demultiplexed signals DS1 so that they become synchronous, so-called bit adjustment in a first buffer BUFF1. (There are 64 buffers connected in parallel, but only one is shown in the figure.) For each frame of data information received by the buffer, there is room for a bit adjustment where an extra bit is added or a bit subtracted if bit adjustment is performed. For a certain signal D51, a possible rate deviation is normally always in the same direction. An oscillator that generates the beat always goes a little too fast or a little too slow (within specified limits). Thus, for one signal, bit additions are always generated and for another, bit removals are always generated. The buffers BUFF1 in the first synchronizing unit SU1 form a boundary between the PDH system and the SDH system. The bit-adjusted signals from the 64 parallel-connected buffers are multiplexed in a multiplexer MUX and then output to the cross-switching unit for switching. After the switching, the switched signals are delivered to the second synchronizing unit SU2 in which they are first demultiplexed in a demultiplexer DEMUX so that they have the bit rate of 2Mb / s. These signals are denoted in the figure DATAh. The demultiplexer emits 64 parallel lines on which the said 2 Mb signals DATAh are delivered. Each line is connected to a separate second buffer BUFF2 for transmitting the switched signals to the PDH system. (Only one buffer BUFF2 is shown in the figure.) The device according to the invention consists of the second buffer BUFF2 in the second synchronizing unit. The other buffers BUFF2 form the boundary between the SDH system and the PDH system. From the other buffers BUFF2, output signals DATA ”are emitted, which are then multiplexed in several steps in MUX multiplexers. Finally, an output data signal DATAUT with a bit rate of 140 Mb / s is output from the second synchronizing unit SU2. Figure 2 shows the buffer BUFF2 from Figure 1 and the data incoming data DATAÜ and the data outgoing from the buffer DATA ”.

The figure also shows that the buffer forms a boundary between an SDH system and a PDH system. To the buffer BUFF2 incoming data DATAi, is divided into frames. Each frame comprises a first part which nominally contains 256 (two hundred and fifty-six) pieces of data information DATAINFO and a second part which nominally contains 32 (thirty-two) pieces of control information CONTROLINFO intended for transmission messages such as frame reading words and control pieces of various kinds. The 256 bits of data information DATAINFO are entered into the buffer. The incoming data signal can contain a bit adjustment JUST which can be performed in two different ways. In the first case, the data information to be written into the buffer contains a bit more than nominal, ie an addition of an adjustment bit JUST so that 257 bits instead of 256 bits are written into the buffer, which in the figure is illustrated with the left dashed line showing a bit of extra data information in the frame.

The second part of the frame in this case comprises a bit smaller than nominal, ie 31 bits instead of 32 bits. In the second case, the data information contains a bit less than nominal, ie a deletion of a bit so that 255 bits instead of 256 bits write into the buffer, which is illustrated in the figure with the right dashed line indicating that the frame contains a bit less data information but instead an adjustment bit JUST. The second part of the frame CONTROLINFO then comprises a bit more than nominal, ie 33 bits instead of 32 bits.

Outgoing data information DATAM has a different frame format to fit into the PDH system. Each frame comprises a first part which nominally contains 206 (two hundred and six) bits of data information DATAINFO which is read out from the buffer BUFF2 and a second part which nominally contains 6 (six) pieces of control information CONTROLINFO intended for transmission messages etc. To make it possible to control the readout rate from the buffer BUFF2, the readout can be temporarily stopped, whereby outgoing data DATAW, in the first part of the frame, contains a bit less data information than usual. This is illustrated in the figure with a dashed line showing that the data information part contains 205 bits instead of 206 bits. The bit that is not read from the FIFO register when regulating the readout rate constitutes a so-called stuffbit STUFF.

Figure 3 shows an addressable memory, FIFO, as well as the use of known technology for writing and reading data in the memory. The memory has an input 1 for incoming data IN, an output 2 for output data OUT, a write address input 3 and a read address input 4. A write address generator comprising a write clock oscillator WCLPOSC and a write counter 5 are connected to the memory write address input 3. A read address generator comprising a read clock oscillator - RCLPOSC lator and a read counter 6 are connected to the read address input of the memory 4. The write counter 5 is counted up with write clock pulses WCLP from the write clock oscillator WCLPOSC. and delivers to memory FIFO a cyclic sequence of write addresses WADR corresponding to its arithmetic content. The read counter 6 is connected via a control circuit 7 to the read oscillator RCLPOSC and is counted up with read clock pulses RCLP which the control circuit transmits from the read clock oscillator.

The read counter 6 delivers to the memory a cyclic sequence of read addresses RAUR corresponding to its count contents. The cyclic sequence of read addresses includes the same addresses in the same order as the addresses in the cyclic sequence of the write addresses.

An address comparison means in the form of a phase detector 8 is connected for receiving the cyclic consequences of addresses. The phase detector compares the instantaneous addresses in the sequence of write addresses WADR with the simultaneous instantaneous addresses in the sequence of read addresses RADR. It is desirable that the simultaneous addresses of the phase detector 9, 10 inputs differ significantly from each other. In the ideal state, the cyclic consequences of addresses are phase shifted by half a cycle. The phase detector 8 measures the difference between the current write address and the current read address of the memory. If the difference between read address and write address is not large enough, the phase detector sends an error signal PE to the control circuit 8 for controlling the count of read clock pulses RCLP of the reading counter 6 from the read clock oscillator RCLPOSC. The read clock oscillator can, for example, be set so that it always has a slightly too high frequency, whereby a phase error signal PE indicates that the control circuit is to stop a read clock pulse. The generation of read addresses is stopped in this way 10 15 20 25 30 ° 47ß 392 repeatedly so that the read rate is temporarily reduced in order to keep a steady pace with the writing.

Figure 3 also illustrates a multiplexer, MUX. The multiplexer has a data input 11 connected to the memory output 2, an information input 12 connected to an information output 13 of the control circuit 7, a control input 14 connected to a control output 15 of the control circuit 7, and an output 16 connected to an output line 17.

A signal CONTROL from the control circuit 7 to the multiplexer MUX controls the multiplexer to receive data information from the FIFO register when readout takes place therefrom and to otherwise receive information bits INFO from the control circuit.

For the aforementioned reasons, a device according to the prior art cannot be used as a buffer at the transition from an SDH system to a PDH system. Instead, a device according to the invention is used.

Figure 4 illustrates an embodiment of an apparatus and method for transferring information from an SDH system to a PDH system according to the invention. Slightly simplified, what is illustrated in Figure 4 can be said to correspond to one of the other buffers BUFFZ in the second synchronizing unit SU2 in Figure 1 and the asynchronous buffer in Figure 2.

The device in Figure 4 comprises an addressable memory, a write address generator, a read address generator, a mean value address generator, first address comparison means, second address comparison means, means for detecting frames and changes in frames in the SDR system and multiplexing means.

The memory, FIFO, has eighty one-bit registers or memory positions, each with a separate address from zero to seventy-nine. Data can be written to the memory in the memory position specified by a write address WADR at the write address input 20 of the memory.

Data can be read from the memory position indicated by a read address RADR on the memory read address input 21. The memory also has a 10 15 20 25 30 35 4 7.6 3 9 2 1 ° write control input 22. The signal on the write control input 22 indicates whether or not to write.

The write address generator comprises a write clock, WCL, which generates write clock pulses, WCLP, in the form of an equidistant pulse train with a write clock frequency, f clw. The write address generator also includes a write counter 23 designed as a modulo-SO counter which in gray code counts from zero to seventy-nine and then starts again at zero. The write counter is connected to the writing clock for counting writing clock pulses WCLP and connected to the writing address input of the memory 20 for generating a cyclic sequence of writing addresses WADR to the memory in accordance with its calculation content. The write counter has a control input 24 connected to a detection means DU for receiving a write control signal DV which indicates whether its counting content is to change in step with incoming write clock pulses WCLP or whether its counting content is to remain unchanged independent of incoming write clock pulses WCLP.

The read address generator comprises an read clock RCL, a frame generator 28 and a read counter 29. The read clock generates read clock pulses, RCLPCL, in the form of an equidistant pulse train with a read clock frequency, fclr SO counter which cyclically counts from zero to seventy nine and then starts again from zero. The reading counter has an output 27. The read counter is designed as a 7-bit gray-coded module connected to the read address input 21 of the memory for generating a cyclic sequence of read addresses RADR to the memory in accordance with its count contents. The read counter 29 is connected via the frame generator 28 to the read clock RCL for receiving and counting the writing clock pulses RCLP which the frame generator transmits from the writing clock.

The unit value address generator comprises a high frequency clock HCL, which generates high clock pulses HCLP, in the form of an equidistant pulse train with a high clock frequency few. The unit value address generator also includes an average value counter 38. The average value counter includes a four-bit binary-coded modulo-0 counter and a seven-bit gray-coded modulo-80 counter. The averaging counter has a pulse input 30 connected to the high frequency clock HCL for receiving high clock pulses HCLP and an averaging address output 31 for generating a cyclic sequence of averaging addresses AVADR according to the counting content of the modulo-80 counter.

The averaging counter also has a control input 32 for receiving counting acceleration or counting delay control signals REG.

When a count accelerating signal is applied to the control input, the modulo-10 counter calculates two steps for a received high clock pulse.

When a count delay signal is applied to the control input, the modulo-10 counter does not count any step upon receipt of a high clock pulse. When neither counting acceleration nor counting delay signal is present on the control input of the mean value counter, the modulo-counter calculates one step for each received high clock pulse. The modulo-80 counter is connected to the modulo-10 counter in such a way that for each time the modulo-10 counter has calculated one revolution, ie ten steps, the counting content of the modulo-80 counter is incremented by one step.

The first address comparison means comprises> one. first phase detector 33 with a first address input 34, a second address input 35, a control input 36 and a control output 37. The first address input 34 is connected to the write output of the write counter while the second address input 35 is connected to the average output of the phase counter 31. 36 is connected to the detection means DU for receiving information, INF, about changing frames in the synchronous system due to bit adjustment.

The phase output 37 of the phase detector is connected to the control input 32 of the averaging counter.

The first address comparison means is designed to compare the addresses of its address inputs 34,35 and certain address limits. When instantaneous addresses in the cyclic sequence of addresses on the first address input are so much behind, i.e. are so much smaller than, simultaneous addresses in the cyclic sequence of addresses on the second address input that the difference at least corresponds to a lower, i.e. rear, address limit value so the first address comparing means emits a delay signal JMPB on its control output 37. When instantaneous addresses in the cyclic sequence of addresses on the first address input are so much 10 * 20 20 25 30 35 392 1 * before, i.e. the addresses are so much larger than, simultaneous addresses in the cyclic sequence of addresses at the second address input - that the difference at least corresponds to a front, i.e. upper, address limit value, the first address comparator emits an acceleration signal .TMPF at its control output. The first address comparison means is thus designed and coupled to the write counter and the mean value counter that it strives to keep the difference between the instantaneous simultaneous addresses, i.e. the phase positions of the cyclic sequences of write addresses and mean value addresses, within the address limit values.

The second address comparison means comprises a second phase detector 40 with a first address input 41, a second address input 42 and a control output 43. The first address input 41 is connected to the address output 27 of the lock counter while the second address input is connected to the address output 31 of the averaging counter. .

The control output 43 of the phase detector is connected to an input 44 of the frame generator 28 of the read address generator.

The second address comparison means is designed to compare the instantaneous simultaneous addresses of its address inputs 41,42 and a specific read address limit value, a so-called stuff limit value. When the instantaneous addresses in the cyclic sequence of addresses on the first address input are so much ahead, are so much larger than, the simultaneous instantaneous addresses in the cyclic sequence of addresses on the second address input that the difference at least corresponds to a so-called stuff limit value, it emits the second address comparator means a phase error signal consisting of a delay signal PE on its control output 43. The delay signal acts on the frame generator so as to prevent a read clock pulse from the read clock from reaching the reading counter, thereby delaying the generation of subsequent read addresses.

Figure 4 also illustrates a multiplexer, MUX. The multiplexer has an information input 52 connected to an information output 53 of the frame generator 28, a control input 54 connected to a control output 55 of the frame generator 28, and an output 56 connected to an output line 57. 1.0 15 20 25 35 * 3 470 392 A signal CONTROL from the frame generator 28 to the multiplexer MUX controls the multiplexer to receive control information bits CONTROLINFO and stuff bits STUFF from the frame generator when no readout takes place from the addressable memory FIFO.

The devices illustrated in Figure 4 operate in the following manner.

The entry of data in the FIFO register takes place serially, ie the first bit in memory position zero, the second in memory position one, and so on. When a piece has been written in memory position seventy-nine, the whole procedure starts again with writing in memory position zero.

Therefore, the entire FIFO register can be seen as a circular loop, which is illustrated in Figure 5. It can be compared with reading addresses RADR writing addresses WADR and average addresses AVADR are generated cyclically.

Data DATAà incoming to the FIFO register 1 is divided into frames in accordance with Figure 2 and the associated description. The first part of the frame, containing data information DATAINFO is entered in the FIFO register at a data input 25. When entering data information in the EÉFO register, the write address WADR is entered at the output of the write counter 23. A write control signal DV is connected to the write counter and to the FIFO register. is high when data information is received by the FIFO register and low when transmission messages are received. (These should never be entered in the FIFO register.) The DV duty cycle of the write control signal thus follows the incoming data signal DATAh with any additions or deletions of adjustment bits. The write control signal DV (Data Valid) is thus high when data is available for writing while it is otherwise low. The write control signal DV is used to cause the write counter to temporarily stop calculating write addresses when the signal is low. Incoming data DATAÉ is, as previously mentioned, divided into frames. The write counter counts an address for each write clock pulse WCLP during the first part of the frame when the write control signal DV is high, whereby data information is entered in the FIFO register. During the second part of the frame, on the other hand, when the write control signal DV is low, the write counter 23 is stopped so that the information contained in the second part of the frame is not entered in the FIFO register.

During the first part of the frame when the entry of data information is to take place, the write counter is switched on by means of the write control signal DV, while during the second part here the entry is not to be made is disconnected. The write control signal DV is also connected to an input 'on the FIFO register' to cause writing to take place only at a high control signal. No enrollment at low control signal. The WCLP write clock pulses from the WCL write clock are connected to a clock pulse input 26 for synchronizing the entry in the FIFO register with the generation of write addresses WADR. The write clock's write frequency (fclw) nmn in the system, since writing only frequency fclw is higher than a nominal takes place 'during a first part of' each frame. The enrollment rate, distributed over the entire frame, however, corresponds to the system's nominal clock speed (fclw) nom. The nominal frequency of the system means the nominal frequency within the telephony for 2 Mb signals.

The write control signal DV is generated in a detection unit DU through which the incoming data signal DATA¿nj passes. The detection unit reads from the incoming data signal whether bit adjustment occurs or not and emits a high write control signal DV when the incoming data DATA consists of information to be entered in the FIFO register and was otherwise low.

The FIFO register forms a boundary between the aforementioned Synchronous Digital Hierarchy (SDH) system and the Plesiochronous Digital Hierarchy (PDH) system so that the addition and deletion of bits, as previously described, are detected in the SDH system, on the FIFO register. writing page, while the subsequent adjustment of the lock-out rate is performed in the PDH system.

Outgoing data DATAout is read out serially and bitwise from the FIFO register. Outgoing data DATA ° out is read out frame by frame to the PDH system.

Outgoing data has, as previously described, a different frame format than incoming data DATAin. Namely, each frame comprises 212 (two hundred and twelve) bits, of which 206 (two hundred and six) consist of data information DATAINFO which is read out from the FIFO register on a data output 58. The remaining six bits consist of control information and control bits which never pass the FIFO register. The control signal CONTROL controls the multiplexer MUX to receive data information from the FIFO register on a data input 59. At the readout, the locking address RADR is indicated on the output 27 of the read counter 29 which output is connected to the FIFO register. Read clock pulses RCLPCL is generated with a read clock frequency fclr that is slightly higher than the nominal write clock frequency (f¿lw) nOm. This means that the reading must be stopped repeatedly a reading clock pulse in order for it to keep a steady pace with the writing. The frame generator 28 can therefore temporarily stop the generation of read clock pulses to the read counter so that there is a pause in the read clock pulses RCLP, whereby the read counter does not generate a new address for reading during the pause. The frame generator thus emits read clock pulses RCLP with intermittent pauses to stop the reading.

The frame generator also creates a pause in the read clock pulses RCLP during the 6 bits in the frame when information is not read out from the FIFO register. The read counter counts in the same way as the write counter from zero to seventy-nine and then the counter starts again from zero again.

The read addresses RADR are thus generated in cyclical order, which is illustrated in Figure 6. Entry into and reading from the FIFO register thus takes place in series, but entry and reading must take place in different memory positions at one and the same time to avoid errors.

The read clock pulses RCLPCL from the read clock RCL are connected to a clock pulse input 70 for synchronizing the readout from the FIFO register with the generation of read addresses RADR.

In order to avoid jitter on the output of the FIFO register during clock adjustments on the PDH side as a result of incoming data DATAÜ1 containing bit additions or bit deletions, according to the invention, the average value counter 38 which is calculated by high-frequency pulses HCLP generated in a high-frequency clock HCL is used. which operates with a frequency fclh which is n times higher than the nominal frequency (fclw) nmn of the write clock. In the preferred embodiment, 11 is equal to ten (n = 10). The averaging counter generates averaging addresses that are averages of the writing addresses. An object of the invention is to use the average value counter in the rate adjustment on the PDH side to avoid problems with jitter on the PDH side. 10 15 20 25 30 35 47Ü 592 16 At its address output 31, the mean value counter 38 generates mean value addresses AVADR which on average correspond to the write addresses WADR. This is because the modulo-80 counter in the average value counter is continuously counted in step with the nominal clock speed, while the typewriter, which pauses for each frame, is only averaged in step with the nominal clock frequency. The generated write addresses WADR thus oscillate around the generated mean value addresses AVADR since the writing is stopped under a second part in each frame. Figures 7 and 8 show diagrams with generated write addresses WADR and mean value addresses AVADR to illustrate how the write addresses oscillate around the mean value addresses. In the diagram, the vertical axis indicates generated addresses ADR and the horizontal axis indicates time t._ The writing addresses WADR are illustrated with a solid line. Each new address generated is not shown separately but the address transitions are illustrated as analog. The time between the times zero and e corresponds to a frame of incoming data DATAh. Between time 0 and a, which correspond to eighty write clock pulses WCLP, the addresses zero to seventy-nine are generated. This is repeated cyclically between time a and b and between time b and c. At time d, 256 write clock pulses WCLP have been delivered to the write counter 23 which has calculated new addresses in eighty cycles and the generated write address WADR is fifteen. Between times d and e, no new write addresses are generated as no data information is received in the FIFO register. The figure also illustrates the dashed averaged addresses AVADR. These are generated more slowly but instead continuously. Therefore, as previously described, the write addresses oscillate around the mean value addresses and the write addresses correspond on average to the mean value addresses. The figure shows write addresses generated when bit adjustment is not available. To illustrate this more clearly, Figure 8 shows the relationship between write addresses and averaging addresses over a period of time corresponding to several frames of incoming data. In addition, the diagram is drawn so that the curves showing the generated addresses do not contain discontinuities.

The vertical axis therefore shows several consecutive cycles of ADR addresses. The horizontal axis shows time t and 10 15 20 25 30 35 17 4:70 392 it has a different scale than the time axis in figure 7. The write addresses WADR are illustrated with the solid line and the mean values' AVADR with the dashed line. The time between the times o and q corresponds to a frame of incoming data and the time between the times q and s also corresponds to a frame. Between the times o and p writing addresses are generated, but between the times p and q no writing addresses are generated. During the next frame, write addresses are generated between the times q and r while there is a pause in the generation between the times r and s. The figure shows that the write addresses WADR oscillate around the mean value address AVADR. The figure only shows write addresses generated when bit adjustment does not occur.

Figures 7 and 8 show that the generated write addresses WADR deviate in a oscillating manner from the generated average value addresses AVADR. However, the deviation is limited as long as no bit adjustment occurs, ie the deviation is within an upper and a lower limit FL, BL. However, if bit adjustments occur, the generated write addresses will deviate from the average address outside these limits. In the method according to the invention, the mean value addresses must always constitute mean values of the write addresses and if the write addresses deviate too much from the mean value addresses due to bit adjustments, the mean value counter must be adjusted so that the write addresses oscillate again around the mean value addresses within the upper and lower limits. In order to be able to check whether the write addresses are within the upper and lower limits, a front and a rear address limit value are calculated for each average value address. These are then used for comparison with generated writing addresses. For address limit values and write addresses mentioned comparison of, the device according to the invention comprises said first phase detector 33 in which a check is performed to ascertain whether a generated write address is within permissible limits in relation to the simultaneously generated average value address.

In the first phase detector 33, for each averaging address generated by the averaging counter, a front address limit value FL and a rear address limit value BL are stored, which limit values constitute limits for the generated write address. An anterior address limit value and a rear address limit value are thus linked to the respective average value address. When the averaging counter 38 generates the averaging address zero, the front address limit value for the write address is twenty-one, while the rear address limit value is fifty-seven. When calculating the rear and front address limit values, the operating cycle of the incoming data signal DATAÜ is assumed. Since the write counter for a period of time corresponding to thirty-two bits does not generate any write addresses, while the mean value counter continuously generates mean value addresses, the generated write addresses will vary around the mean value addresses about thirty-two addresses, but on average the write addresses correspond to the generated mean value addresses. about sixteen addresses in each direction from the mean address seen.

P.g.a. addition or removal of adjustment bits on the synchronous side (SDK side) further deviate from the generated mean value addresses.

The limit for how much the write address is allowed to deviate from the average address can be set slightly above the said sixteen addresses, the generated write addresses will without risk of writing and reading colliding in a memory position in the FIFO register. For example, the deviation can be allowed every twenty-one positions for the front limit and twenty-three for the rear. For the average address zero (0) the front address limit value is calculated to twenty-one (21) and the rear address limit value to fifty-seven (57), for the average address one (1) the front address limit value is calculated to twenty-two (22) and the rear to fifty-eight (58) etc.

In Figure 8, these limit values are illustrated with dotted lines.

The 'front limit values are denoted FL (Front Limit) and the rear ones are denoted BL (Back Limit).

The first phase detector 33 has the first input 34 connected to the output of the write counter 23 for detecting generated write addresses WADR, and a second input 35 connected to the output 31 of the average value counter for detecting generated average addresses AVADR. The first phase detector 33 also has a control output 37 connected to a second input 32 on the averaging counter 38 for controlling the averaging counter if the generated write address assumes one of the limit values in the comparison in the first phase detector 5. When controlling the average value counter, a control signal REG is emitted from the first phase detector, which may consist of a forward control signal JHPF or of a reverse control signal JMPB.

In the first phase detector, the detected write address is compared with the front and rear limit values calculated at the simultaneously detected average address. If the write address is equal to the front limit value, then the control signal REG consists of a forward control signal (acceleration signal) JMPF. This forward control signal indicates that the averaging counter must be calculated step by step, during n steps, an extra averaging address extra. This is done by speeding up the generation of averaging addresses in the modulo-80 counter in the averaging counter. This acceleration in the generation of a new average value address takes place in ten steps (n = 10), whereby for each step the modulo-10 counter in the average value counter calculates two positions during a high clock pulse HCLP instead of one which normally when no control signal is present on the first the phase detector output. If, in said comparison, the detected write address is instead equal to the rear limit value, then the control signal REG consists of a reverse control signal (delay signal) JMPB. The reverse control signal indicates that the average value counter during ten steps must calculate an average value address less than, when no control signal occurs. This "hacking" takes place in ten steps, whereby for each step the modulo-10 counter stops a high clock pulse HCLP, ie the modulo-10 calculator calculates zero (0) positions during the n steps. The control of the mean value counter in n steps is spread out for as long as possible. Under normal conditions, when no control signal is present, the modulo-10 calculator calculates one (1) step for each high clock pulse HCLP.

Figure 9 illustrates how the generation of mean value addresses AVADR is accelerated when the control signal REG consists of a forward control signal. Figure 9 also illustrates how the generation of mean value addresses is delayed when the control signal REG consists of a 2 ° reverse control signal. The upper diagram shows how the generation of averaging addresses is accelerated. The horizontal axis of the chart shows time t and the vertical axis of the chart shows generated addresses ADR. Generated mean value addresses AVADR are illustrated with dashed lines and the write addresses WADR are illustrated with solid lines. Front and rear limit values FL, BL are illustrated with dotted lines. The time between times A and B, B and C and between C and D is constant and corresponds to eighty write clock pulses. During this time, the averaging counter generates eighty averaging addresses. Between times A and D, the generated write addresses vary within the front and back address limit values FL, BL, but at time X, in the next time interval between times D and E, the write address is equal to the front address limit value (WADR = FL) as a consequence of a bit adjustment. As previously described, the average value counter then produces an extra average value address, which takes place in 10 steps. In the same diagram. such a tenth control of the generation of the AVADR averaging addresses is shown. The time interval between times F and G corresponds to eighty write clock pulses as well. the other intervals. in the diagram. At time Y, it is illustrated that the average value counter generates the next average value address in a shorter time than normal, since the modulo-10 counter then momentarily calculates two positions instead of one. This accelerates the generation of the next average address. Thus, at time Y, the generation of the next average address is accelerated in a first step. Thereafter, a further nine accelerations are performed over a period of time which depends on how often bit adjustments occur. These additional nine accelerations are not shown in averaging addresses Since the generation of so is generated the averaging address seventy-nine (79) diagram. accelerated earlier than if acceleration is not performed. The diagram shows that the mean value address seventy-nine (79), as a result of a step in the acceleration, is generated at the previous time Z instead of at time G. The diagram is not correct regarding the scale. The adjustment of the mean value address AVADR at time Y is excessively large in order for it to be visible. The diagram also shows the front and rear limit values FL, BL and how these vary with the average address AVADR. The lower diagram in Figure 9 illustrates a delay in the generation of average addresses. The delay is performed as a result of a. previously performed. bit adjustment 'which consists of a bit remover. This diagram does not show generated addresses in the intervals before the time interval D-E. In the time interval between times D and E at time R, it is shown that the generated write address is equal to the rear address limit value (WADR = BL).

In a later time interval. between ^ times F and G 'at time S, the subsequent control is performed by the mean value counter. At time S, one tenth of the entire adjustment takes place by the average value counter. The control consists of a delay of the calculation: in the modulo-10 counter. The delay means that the modulo-10 counter is stopped during a high clock pulse HCLP so that it takes a high clock pulse HCLP longer for the mean counter to generate the next address. This is illustrated in the diagram as the line for the average addresses becoming horizontal at time S when no calculation takes place in the modulo-10 counter. As a result of the delay, the average address seventy-nine (79) is generated at the later time T instead of at the time G as in normal cases when there is no control of the average counter.

Through the adjustments of the average value counter described in connection with Figure 9, it is achieved that the generation of average value addresses is delayed or accelerated in order for them to follow the changes in the generation of write addresses as a result of bit adjustments.

Figure 10 shows a more detailed view of the first phase detector 33. The phase detector comprises a memory and comparator unit 60 which is connected to the first and second inputs 34,35 for detecting said write address WADR and mean value address AVADR. In the memory and comparator unit 60 the front and rear address limit values are stored and there the detected write address is compared with the front and rear address limit value which applies to the simultaneously detected average value address. If the write address WADR is equal to the forward address limit value FL, then the memory and comparator unit 60 outputs a first signal jrqf (jump request forward) to a control unit 61 in the phase detector, but if the write address is equal to the rear address limit value BL, the memory and comparator unit 60 instead emits a second signal jrqb (jump request backward) to the control unit 61. In order to reduce as much as possible jitter that can be caused by said adjustment bits on the writing side, the described stepwise control is performed with such large distances as possible between the steps, ie the time interval between each stepwise adjustment of the mean value counter shall be as large as possible. This is accomplished by providing information on the addition or removal of an adjustment bit when entering data in the FIFO register from the detection unit DU (see Figure 2) to the control unit 61 in the first phase detector 33. The information takes the form of a pulse INF on the control input 36 when adding or removing an adjustment bit. In the control unit 61, the time between the two most recent pulses INF and from the measured time is measured in the control unit, the time which is to elapse between each step in the control of the average value counter. The time between each step is calculated to 1 / n - part, which according to the example corresponds to one tenth, of the time between the last two adjustment bits. When the control unit receives a first signal jrgf for requesting forward control of the average value counter or a second signal jrqb for requesting reverse control, the time between the steps in the control is calculated in the manner described. A counter unit 62, connected to the control unit 61, is set, in accordance with the calculated time, to control the time between the steps in the stepwise control of the average value counter. The control unit 61 outputs said forward control signal JMPF to the average value counter if this is to be regulated forward. The forward control signal comprises ten pulses emitted at intervals controlled by said counter unit. The control unit emits the said reverse control signal JMPB in a corresponding manner to control reverse. The forward and reverse control signals JMPF, JMPB are output at the output of the first phase detector 33 37. the average value counter To finally synchronize the read rate with the write rate, as previously mentioned the read clock pulses RCLPa_ (see figure 4) generated in the read clock RCL read read sk stuffing. For controlling said stuffings, the device according to the invention comprises, in addition to the average value counter and the first phase detector, also said second phase detector 40 with a first input 41 connected to the reading counter. output for detecting read addresses RADR, - and a second input 42 connected to the output of the average value counter for detecting average addresses AVADR and with an output 43 connected to said frame generator 28 for performing said stuffing.

To determine when stuffing is to take place, a so-called stuff limit value or read address limit value. which is stored in a memory and comparator unit in the second phase detector. The stuff limit value is an address in the FIFO register from which reading may not take place. This is because the reading rate is too high and there is a risk that reading and writing are performed at the same address in the FIFO register.

When calculating stuff limit values, it is assumed that reading from the FIFO register shall take place at a memory position which is located as far as possible from the memory position in which writing takes place. The mean counter generates an address that is an average of the address that the write counter generates. Since reading should take place as far from writing as possible and since the FIFO register includes eighty memory positions, the risk of writing and reading in the same position is avoided if the stuff limit value is calculated to the mean address plus forty-one (41). For the mean value address zero (0) the stuff limit value is calculated to forty-one (41), for the mean value address one (1) the stuff limit value is calculated to forty-two (42) and so on. The stuff value can possibly be moved forward one or two more addresses without the risk of writing and reading taking place in the same memory position in the FIFO register. To determine whether stuffing is to take place, in the second phase detector the detected read address RADR is compared with the stuff limit value which is linked to the simultaneously detected average value address AVADR. If the read address in the comparison is equal to the stuff limit value, then the readout rate is too high, whereby the second phase detector emits a phase error signal PE at its output.

The phase error signal PE consists of a pulse which is sent to the frame generator. In each frame outgoing data DATA ”it is possible to perform stuffing at a specific time (see figure 2). When the frame generator receives a phase error signal PE, stuffing is performed at the first possible time. In the frame generator, during stuffing, a read clock pulse RCLP is stopped from the read clock RCL, whereby the read counter is not counted up, but stands still for the time corresponding to a read clock pulse. The phase error signal PE can also be called a delay signal because the reading of data information DATAINFO from the FIFO register is delayed by stopping the reading a clock pulse. Instead, the frame generator 28 outputs a stuffbit STUFF which is delivered via the multiplexer MUX from the buffer together with the outgoing data DATAm. From the frame generator, a control signal CONTROL is emitted to the multiplexer for controlling it. By stopping the reading from the FIFO register in the manner described above and instead adding a piece of stuff to the outgoing data flow, the reading rate from the FIFO register is reduced.

Outgoing data DATA ”includes, as previously mentioned, six bits per frame that are not read from the FIFO register. This means that the frame generator does not generate read clock pulses RCLP during these pauses in the readout. The pauses correspond to six bits, which means that the read addresses also move relative to the average value addresses. During pauses, the frame generator 10 outputs information bits INFO which are delivered via multiplexer MUX from the buffer together with outgoing data DATAW. These pieces of information can be, for example, frame lock words and control pieces for stuffing. To control the multiplexer MUX, the frame generator 10 outputs a control signal CONTROL to the multiplexer HUX.

From the multiplexer MUX, data data DATAINFO from the FIFO register as well as stuff bits STUFF and control information bits CONTROLINFO from the frame generator 28 are output on the output line 57.

Figure 11 illustrates in three diagrams the relationship between generated mean value addresses, stuff limit values and generated read addresses. The horizontal axes show time t and the vertical axes show addresses ADR. The time interval between the times 0 and! respectively between M and N corresponds to the time it takes to generate 800 high clock pulses HCLP (which corresponds to the time of the generation of 80 average addresses when no control of the average counter is performed). The dashed lines show mean value addresses AVADR, the solid lines show read addresses RADR and the dotted lines show stuff limit values SL. In the upper diagram, there is no adjustment of the average value counter, whereby the average value addresses AVADR are generated continuously. In the first part of the diagram, between the times 0 and M, the so-called stuffing. At time I, the generated read address is equal to the stuff limit value (RADR = SL) and a phase error signal PE is output to the frame generator (see figure 4). No new read addresses are generated between times J and K because the frame generator instead provides control information CONTROLINFO (see figure 2). Due to the phase error signal PE at time I, a stuff bit STUFF is generated in the frame generator at time K so that no generation of a new read address takes place between times K and L which corresponds to a read clock pulse RCLP. S.k. stuffing is performed. In the diagram, the STUFF bit is illustrated slightly submerged.

The frequency of the read clock pulses is such that stuffing is performed approximately once every other frame when no bit adjustment causes control of the mean value counter. The generated read addresses RADR thus vary slightly below the stuff limit value and approximately once every two frames of outgoing data DATA ”the read address is equal to the stuff limit value. The second part of the diagram (between the times M and N) illustrates the relationship between the different lines when no adjustment of the mean value counter takes place. At time Q, the distance between the generated read address RADR and the STUFF limit value SL is equal to qi addresses ADR.

The middle diagram illustrates a forward control of the averaging counter, ie an acceleration of the generation of averaging addresses. Up to time M, the diagram is the same as the upper one with a STUFF bit inserted between times K and L. At time 0, an acceleration is performed in the generation of average addresses AVADR, the lines for average addresses AVADR and stuff limit values SL being shifted upwards in the diagram. A cycle of average addresses (eighty) is then generated in a shorter time than when no acceleration occurs, which has been described in connection with Figure 9. At time Q, the distance between generated 15 15 addresses is RADR and stuff limit value SL equal to gz addresses ADR. The distance q, is due to the acceleration greater than the distance gl, which illustrates that it will take longer until the next stuffing needs to be performed compared to the time until the next stuffing in the upper diagram. The figure shows that the generated read addresses RADR will approach the stuff limit value SL more slowly than in the upper diagram.

Stuffing thus occurs less frequently in connection with acceleration in the generation of mean value addresses.

The lower diagram illustrates a reverse control of averaging counters, ie the generation of averaging addresses is delayed. Up to the time M, the diagram is the same as the upper one with a STUFF bit inserted between the times K and L. At the time P, a delay is generated in the averaging addresses AVADR, whereby the lines for the averaging addresses AVADR and stuff limit values SL are shifted down in the diagram. A cycle of mean value addresses (eighty) is then generated in a longer time than when no delay occurs, which has been described in connection with Figure 9. At time Q, the distance between generated read addresses RADR and the stuff limit value SL is equal to qs addresses ADR. The distance q; is due to the delay less than the distance q, which illustrates that it will take less time until the next stuffing must be performed compared to the time until the next stuffing in the upper diagram. The figure shows that the generated read addresses RADR will approach the stuff limit value SL faster than in the upper diagram. Stuffing thus occurs more often in connection with a delay in the generation of mean value addresses. a The writing counter 2, the reading counter 3 and the average value counter 4 are all built with modulo-SO counters that use gray code when calculating. Gray code is used to change only one bit at each calculation, thereby reducing the risk of errors in the calculation. It is also conceivable to use other types of codes, for example. regular binary code. 10 15 20 2 ”L 470 392 In practice, the gray code is used only for the mean value counter, so that when comparing addresses generated in two counters, at least one uses the gray code. In the preferred exemplary embodiment, there is no direct comparison between, for example, the mean value address and the read address. The comparison takes place between each average value address stored in the memory of the phase detector and the detected average value address and between a stuff limit value associated with each stored average value address and detected reading address.

It is also conceivable to compare the detected mean value address with the detected reading address and calculate the difference between them. If the difference exceeds a predetermined value, stuffing is performed. In the same way, the difference between detected mean value addresses and write addresses can be calculated and based on the calculated difference, it can be determined whether acceleration or delay must be performed.

It can be added here that in the exemplary embodiment, bit adjustments occur, which are usually eighty frames. Bit adjustments may also occur less frequently or not at all if the frequency of incoming data corresponds to the nominal frequency of the system. Maximum allowable frequency deviation according to specifications for a signal in the described system causes bit adjustment every eighty frames.

A step-by-step delay or an acceleration of the average value calculator then takes place, which was usually every eighth frame.

Claims (16)

10 15 20 25 30 35 28 479 E92 PATEHTKRAV 1. Procedure for enrollment and. reading data in an addressable memory (FIFO), in which process a cyclic sequence of write addresses (WADR) is successively generated, the data (DATAin) being written into memory positions in the memory specified by the write addresses, a cyclic sequence of read addresses (RADR) are generated, in which sequence of read addresses includes the same memory addresses and in the same order as: the memory addresses included in the cyclic sequence of write addresses, whereby information (DATA ° out) is output from memory positions in the memory specified by the read addresses, k ä characterized by the formation of a cyclic sequence of averaging addresses (AVADR), which sequence of averaging addresses includes the same memory addresses in the same order as the write addresses and the lock addresses, that front and rear write address limits (FL, BL) for acceptable difference between a written address and a simultaneous average value address is determined, that the write addresses are momentarily compared with the simultaneous average value addresses or with addresses obtained from the mean value addresses by means of the write address limit values, that if an instantaneous write address differs from a simultaneous mean value address at least so much as to correspond to a fixed write value limit, the generation of subsequent mean value addresses is accelerated or delayed so that the difference between the simultaneous averaging addresses are reduced, the acceleration or delay is divided into a number of steps by shortening or lengthening the time between the generation of a few pairs of successive averaging addresses, a read address limit value (SL) is determined, the read addresses are momentarily compared with the simultaneous averaging addresses or with addresses obtained from the mean value addresses by means of the read address limit value, that if an instantaneous read address differs from a simultaneous mean value address at least so much as to correspond to the determined read address limit value, the generation of a read address is delayed, e.g. t that a cycle of read addresses is generated for a shorter time than a cycle of read addresses when there is no delay in the generation of the read addresses. 10 15 20 25 30 35 'J 4 7 392 A method for transferring data from a synchronous digital hierarchical system (SDH) to a plesiochronous digital hierarchical system (PDH), the method comprising writing data (DATAin) from the synchronous system into an addressable memory (FIFO) and reading of data (DATAOut) to the plesiochronous system from the addressable memory, in which process a cyclic sequence of write addresses (WADR) is successively generated, the data (DATAin) from the synchronous system being written into memory positions in the memory specified by the write addresses, generating a cyclic sequence of read addresses (RADR), in which sequence of read addresses the same memory addresses are included and in the same order as the memory addresses included in the cyclic sequence of write addresses, whereby information (DATAOut) is read out to the plesiochronous system from memory positions in the memory specified by the read addresses, characterized in that a cyclic sequence of mean values (AVADR) is generated, which sequence of average addresses include the same memory addresses in the same order as the write addresses and read addresses, that front and rear write address limits (FL, BL) for acceptable difference between a write address and a simultaneous average address are determined, that the write addresses are momentarily compared with the simultaneous average addresses or with addresses obtained from the averaging addresses by means of the written address limit values, that if an instantaneous writing address differs from a simultaneous average value address at least so much as to correspond to a fixed write address limit value, the generation of subsequent average value addresses is accelerated or delayed so that the difference between the simultaneous averaging addresses are reduced, that the acceleration or delay is divided into a number of steps by shortening or lengthening the generation between a few pairs of successive averaging addresses, that a read address limit value (SL) is determined, that the locking address a is momentarily compared with the simultaneous average values or with addresses obtained from the average addresses by means of the read address limit value, that if an instantaneous reading address differs from a simultaneous average address at least so much that it corresponds to the established reading limit value, the generation of subsequent read addresses is delayed. a cycle of read addresses 10 15 20 25 30 30 47Û 592 is generated in a shorter time than a cycle of write addresses when there is no delay in the generation of the read addresses. Method according to claim 1 or 2, characterized in that the write addresses (WADR) are generated by intermittent counting in a write counter of write clock pulses (WCLP) with a (fclw) f (RADR) by intermittent counting in a read counter of read clock pulses write clock frequency that the read addresses generated (RCLP) with a read clock frequency (fdr), that the average addresses (AVADR) are generated by counting in an average value of high clock pulses (HCLP) with a high clock frequency (fclh) higher than the write clock frequency and the read clock frequency of the average step is divided depends on the ratio between the average value clock frequency and the write clock frequency, and that the magnitude of said delay of the read addresses corresponds to the time between two successive read clock pulses. 4. A method according to claim 3, characterized in that the time between two successive mean value addresses is shortened, if applicable, by double counting of a high clock pulse, and that the time between two successive mean value addresses is extended by not counting an average clock pulse. Method according to claim 1, 2, 3 or 4, wherein data is received distributed on frames whose size changes intermittently, characterized in that the time between the last two times when the size of the frames is changed is determined, and that the steps when the generation of the mean address is delayed or accelerated are spread. out substantially evenly over a time corresponding to said time between the last two times. Method according to one of Claims 1, 2, 3, 4 or 5, characterized in that when accelerating or delaying the generation of the averaging addresses, the time between certain pairs of successive averaging addresses is neither shortened nor extended. 10 15 20 25 30 35 31 4 7 Ü 3 9 2 Device for writing and reading data in an addressable memory (FIFO), write address generator and a read address generator, which write address generator is arranged to generate a cyclic sequence of write addresses (WADR), the data (DATA¿n) being written into the memory po - memories in the memory specified by the write addresses, which read address generator is arranged to generate a cyclic sequence of read addresses (RADR), in which sequence of read addresses the same memory addresses are included and in the same order as the memory addresses included in the cyclic sequence of write addresses, whereby information (new mt ymt) is read out from memory positions in the memory indicated by a mean value which device comprises a read addresses, characterized by address generator for generating a cyclic sequence of mean value addresses (AVADR), sequence of mean value addresses comprises the same memory addresses in the same order as the write addresses and read addresses, by the first address comparison means for instantaneous equal between the write addresses and the simultaneous average value addresses or with addresses obtained from which the average value addresses by means of determined write address limit values (FL, BL) which first address comparison means are arranged to influence the average value address generator to accelerate or delay the generation of the average value addresses. instantaneous write address differs from a simultaneous average value address at least to the extent that it corresponds to a fixed write address limit value whereby the difference between the write addresses and the simultaneous average value addresses is reduced, that the average value generator is arranged to divide the acceleration or delay into a number of steps. of successive averaging addresses is abbreviated or extended, by a second address comparison means for instantaneous comparison of the read addresses with the simultaneous averaging addresses or with addresses obtained from the averaging address by means of a read address limit value (SL), which other address comparison means is arranged to influence the read address generator to cause a delay in the generation of the read addresses if, an instantaneous read address differs from a simultaneous average value address at least so much as to correspond to the read address limit value. the read address generator is arranged to generate a cycle of lock addresses for a shorter time than the write address generator generates a cycle of lock addresses in the event that there is no delay in the generation of the lock addresses. Device comprising a synchronous digital hierarchical system (SDH), a plesiochronous digital hierarchical system (PDH) and an addressable memory (FIFO) for transferring data from the synchronous system to the plesiochronous system, which device comprises a write address generator and a read address generator, which write address generator is arranged to generate a cyclic sequence of write addresses (WADR), wherein data from the synchronous system (DATAin) is written into memory positions in the memory specified by the write addresses, which read address generator is arranged to generate a cyclic sequence of lock addresses ( RADR), in which sequence of read addresses contains the same memory addresses and in the same order as the memory addresses included in the cyclic sequence of write addresses, information (DATAout) being output to the plesiochronous system from memory positions in the memory specified by the read addresses, characterized by a average address generator for generating a cyclic sequence d of mean values (AVADR), which sequence of mean addresses includes the same memory addresses in the same order as the write addresses and read addresses, by first address comparison means for instantaneous comparison between the write addresses and the simultaneous mean value addresses or with addresses obtained from the mean values by writing address limit (FL, BL) influence the mean value address generator so that which first address comparison means is arranged to cause an acceleration or delay of the generation of the mean value addresses if an instantaneous write address differs from a simultaneous mean value address at least so much as to correspond to a fixed write address limit value. and the simultaneous averaging addresses shall be reduced, that the averaging address generator is arranged to divide the acceleration or delay into a number of steps by increasing the time between the generation of a few pairs of successive averaging addresses are shortened or lengthened by other address implementation means for instantaneous comparison of the lock addresses with the simultaneous average addresses or with addresses obtained from the average addresses by means of a read address limit value (SL), which other address comparison means is arranged to actuate the read address generator to cause a delay in the generation of the read addresses by one. instantaneous read address differs from a simultaneous mean value address at least in that it corresponds to the read address limit value, and that the read address generator is arranged to generate a cycle of read addresses for a shorter time than the write address generator generates a cycle of read addresses in case there is no delay in generating the read addresses. 9. Apparatus according to claim 7 or 8, characterized in that the write address generator comprises a write clock for generating write clock pulses (WCLP) with a write clock frequency (fchg and a write counter connected to the writing clock for intermittent counting writing pulse pulses, that the read address generator comprises a read address generator for generating read clock pulses (RCLP) with a read clock frequency (flr) and a read counter connected to the read clock for intermittent counting of read clock pulses, which read clock frequency differs from the write clock frequency, that the average address generator comprises a high frequency clock clock (HC). fclh) which is higher than the write clock frequency and the lock clock frequency, that the mean value address generator comprises an average value counter coupled to the mean value clock for counting mean value clock pulses, that the mean value address generator is arranged to divide the adjustment of the mean value addresses into a number of steps which depend on the relationship between the average value clock frequency and the write clock frequency, and that the read address generator is arranged to, if necessary, delay the generation of the read addresses by a time corresponding to the time between two successive read clock pulses. 10. Device according to claim 9, characterized in that the averaging address generator is arranged to shorten the time between two successive averaging addresses by double counting and that the averaging address generator is arranged to extend an averaging clock pulse, where appropriate, an average time clock, 10 15 20 25 30 35 34 479 392 between the generation of two successive averaging addresses by not counting a high clock pulse. Device according to claim 8, 9 or 10, in which data is received distributed on frames whose size changes intermittently - drawn means (DU) for determining the time between the two most recent times when the size of the frames has changed, and that the mean value address generator is arranged to spread the steps substantially evenly over a time corresponding to said time between the last two times. Device according to claim 7, 8, 9, 10 or 11, characterized in that the mean value address generator is arranged to neither shorten nor prolong the generation between certain pairs of successive mean value addresses when accelerating or delaying the generation of the mean value addresses. 13. A method for correspondingly adjusting the rate of reading of data from the FIFO register when adding or removing an adjustment bit when entering data in a FIFO register without causing too much jitter on the output of the FIFO register , which incoming data is received by the FIFO register divided into frames which comprise a first part with bit-divided data information which may comprise an added or deleted adjustment bit and a second part without data information wherein - incoming data information (DATAin) is sequentially written bitwise in said FIFO register , comprising a number of memory positions each with a separate address, - when entering data information, the write address is entered by a write counter which is counted in time with a write clock (WCL) which operates at a write clock frequency (fclwh - outgoing data (DATAOut) is read out sequentially and bitwise from the FIFO register, whereby when reading data information, the reading address is specified by a reading counter which is counted up p in time with a reading clock (RCL); said method further characterized in that - an averaging counter is counted at the rate of a high frequency clock (HCL) with a clock frequency which is n times higher than the nominal frequency ((fclw) n ° of the clock). m) and, the averaging counter generates averaging addresses which constitute averaging of the writing addresses; - for each address in the FIFO register which: the mean value counter generates, a front address limit value (FL) and a rear address limit value (BL) are calculated for the write address; - in a first phase detector (33) the generated write addresses and the generated mean value addresses are detected; in the first phase detector the write address is compared with the address limit values calculated for the simultaneously detected value address and if the write address is equal to the front limit value then the average value counter is gradually adjusted a mean value address forward in n steps and if the write address is equal to the rear address limit value the averaging counter is step-by-step averaging address backwards during n steps; - the read clock (RCL) is assigned a read clock frequency (fclr) which is higher than the nominal write clock frequency (fchgn ° m); ) the generated read addresses and the generated mean value addresses are detected; - in the second phase detector the read address is compared with the simultaneously detected stuff limit value and if the read address is equal to the stuff limit value then the second phase detector emits a phase error signal PE read clock pulse is stopped, whereby the reading of outgoing data (Dk fi blank) from the FIFO register is stopped during a read clock pulse. A method according to claim 13, characterized in that - information on the addition or removal of adjustment bits when entering incoming data (DATAin) in the FIFO register is continuously supplied to the first phase detector; the time interval between the last two additions or deletions of adjustment bits is calculated; the time between each step in controlling the averaging counter an averaging address is 1 / n of the calculated time interval. 10 15 20 25 30 35 36 470 392 Device for adjusting the rate of readout in a corresponding manner when adding or removing an adjustment bit when entering data in a FIFO register, without causing too much jitter on the output of the FIFO register, which incoming data is received by the FIFO register. the register divided into frames which comprise a first part with bit-divided data information which may comprise an added or a deleted adjustment bit and a second part without data information, said FIFO register comprises a number of memory positions each with a separate address, in which memory positions incoming data information DATAin sequentially entered bitwise, and connected to said FIFO register - a writing counter for generating writing addresses indicating where in the FIFO register (DATAin) is to be entered, said writing counter having an output connected to incoming data information the FIFO register on which output the generated write addresses are output to the FIFO register and said write counter has an input k charged to a writing clock (WCL) that operates with a writing clock frequency (fclw) whereby the writing counter calculates writing addresses in step with the writing clock: - a reading counter with an output connected to the FIFO register, which reading counter at the output gives addresses in the FIFO register which outgoing data (DATAout) is to be read from and said reading counter has an input connected to a reading clock (RCL), the reading counter calculating reading addresses in step with the reading clock: characterized in that said device further comprises - an average care counter with a first input connected to a high frequency clock (HCL) operating at a frequency n times higher than the nominal frequency of the write clock (fclw) n ° m), the mean value counter generating a new average value address after n calculations, and said average value counter having an output at which the generated average value addresses are output; a first phase detector (33) having a first input connected to the output of the write counter for detecting generated write addresses and a second input connected to the output of the averaging counter for detecting generated average addresses and an output connected to a second input of said averaging counter for 10 15 20 25 30 37 470 592 controlling the averaging counter wherein the averaging counter gradually steps a mean value address forward if the write address assumes a front limit value in relation to the average value address while the average value counter gradually steps a mean value address backwards if the write address assumes a rear limit value; a second phase detector 'with a first input connected to the output of the read counter for detecting generated read addresses and with a second input connected to the output of the average value counter for detecting generated average addresses and with an output connected to a frame generator for controlling the output, the second phase detector emitting a phase error signal PE to the frame generator if the read address assumes a stuff limit value in relation to the detected average value address and upon receipt of said phase error signal, the frame generator stops the reading during a read clock pulse. Device according to claim 15, characterized in that - a detection unit (DU) the data signal (DATAin) for detecting adjustment bits (JUST); the detection unit (DU) is coupled to a control unit (61) in the first phase detector (33) for outputting to said control unit an information signal (INF) upon detection of an adjustment bit - in the control unit (61) the time between each step in the control is calculated. the ringing of the averaging counter based on the time interval between them is connected to the incoming two last information signals (INF); - a counter unit (62), coupled to said control unit (61), is set to control the control unit (61) so that it controls the averaging counter step by step with the time between each step in accordance with calculations in the control unit.