SE438044B - SET FOR CHANGING A INCOMING BINED DATA WORD AND A PARALLEL DOUBLE-DIRECT SHIFT CIRCUM FOR IMPLEMENTATION OF THE SET - Google Patents

Description

7806M14) 2 tion is constant for all shift sizes. This device has been found to be completely suitable for its intended purpose, namely to shift the relative positions of the bits in a binary word, but it is not well suited for performing other logical functions.

An object of the present invention is to provide a parallel bidirectional shifter and data processor which exhibits advantages over prior art circuits. An essential feature of the invention is that the circuit can be used to effectively isolate a field of data in an incoming binary word, the field being adjusted to the right, i.e. an outgoing binary word comprises only the isolated bits which are located at the least significant edge the positions in the word. A feature of the circuit according to the invention is also that it can be achieved by utilizing a minimum number of components of the kind which are commercially available as stock. A further feature of the invention is that each function of the circuit can be performed in minimal real time and wherein the time to complete each operation is constant.

In accordance with the invention, there is provided a method of shifting a binary word with N bits each number up to N -1 positions to the left or right, a shift network being used to shift an incoming binary word a predetermined number of positions in a in advance stock direction. The circuit comprises a register which is logically connected to the shift network for storing the mirror image of the binary word appearing at the output of said network. A shift control circuit satisfies under the control of a data processor that certain parts of the shifting network obtain the desired shifting size and the input binary word is circulated twice through the shifting network and the accumulator register for each operation.

Since the circuit performs the shift functions using microinstructions, the second is performed on the mirror image of the data obtained from the first instruction, whereby the function with data field isolation (masking) can take place efficiently using the same circuit and in a minimum of 7806741-0 real time.

These and other effects of the invention will become more apparent from the following description of an exemplary embodiment of the invention and with reference to the drawings.

Fig. 1 is a block diagram of a parallel bidirectional shift circuit in accordance with the invention.

Fig. 2 is a schematic block diagram of the circuit shown in Fig. 1.

Fig. 3 is a schematic diagram of one of the gates illustrated in Fig. 2 together with the associated truth table.

Fig. 4 is a synchronization diagram illustrating the operation of the circuit of Fig. 2.

Figs. 5-7 illustrate binary words appearing at different points in the circuit of Fig. 2 for different functions.

The following embodiment shown as an example of the invention constitutes a circuit arranged to work on a binarized word with 16 bits, 0-15. It will be appreciated that a bidirectional shift and data processing circuit utilizing the invention may be adapted to operate on binary words of any desired length.

Figure 1 shows a shift network 20 with four levels identified as SH-1 or SH-0, Slk2 or SH-0, SH-4 or SH-0 and SH-8 or SH-0. These are logically connected as will be described below and each level is arranged to shift an incoming data word a predetermined number of positions or no position. A shift control circuit 21 receives clock signals and a 4-bit data field from a microprocessor register (not shown) to provide the activation signals, ZU, 21, 22 and 23, for corresponding levels in the shift network 20. An accumulator register 22 has a selective gate input for receiving data from an incoming data bus or from the shift network 20. The register 22 is controlled by a selector control signal from the microprocessor and by clock signals. The parallel output lines 0-15 from the network 20 are cross-connected to 16 inputs, 15-0, of the register 22, so that the register 22 stores the mirror image of the binary word appearing at the output of the network 20. The outputs from the register 22 are connected to a bus 23, which serves as the output data bus for the device and as a circulation bus for feeding output data from the register 22 back to the input of the network 20.

Figure 2 is a schematic diagram of the circuit of Figure 1. The shift control circuit 21 is not shown in more detail than in Figure 1, since it may simply be a register controlled by the clock signals to provide four activation signals S1, S2, S4 and S8. , corresponding to the four levels of the shift gates in the network 20.

Each shift level in the network 20 comprises 16 gates AO-A15, BO-B15, CO-C15 and DO-D15. Each of these gates has a pair of inputs, each of which can be selected by a control signal, S1, S2, S4 and S8.

Figure 3 illustrates such a gate together with a truth table showing the function of the gate. When the selector or activation line is not activated, the gate G allows data on the input line A to appear on the output line C and when the selector line is activated, the gate G allows data on the input line B to appear on the output line C.

This type of gate is commercially available as a stock item and is commonly known as a dual-input data select gate.

The gates in each level of the shift network are logically connected to the gates in the previous level for shifting the binary word a predetermined number of positions to the left. For example, each of the gates A0-A15 in the first level is connected to two lines of the bus 23: If the line S1 is not activated, the gates A0-A15 have no effect on the data word appearing on the bus 23 other than to allow it to appear at their outcome. However, if the line S1 is activated, the gates A0-A15 will effectively shift data appearing on the bus 23 one position to the left.

Similarly, gates BO-B15 at the second level are arranged not to shift (line S2 not activated) or 78Û67lr1 ~ 0 to shift (line S2 activated) data appearing at the output of the first level gates A0-A15 2 positions to the left. The gates in the third and fourth levels are similarly arranged not to shift or to shift to the left 4 and 8 positions, respectively. Thus, by allowing a binary word with N bits to propagate through the four levels of the shift network 20 and by selectively activating these levels, the binary word appearing at the exit of the shift network can represent a shift to the left of any number of positions up to N-1. .

The register 22 comprises 16 flip-flops, RO-R15, each with selective gates with two inputs of the type previously described. These elements are also commercially available as stock items. A first set of inputs to the elements RO-R15 is connected to the respective wires of an input data bus. A binary data word appearing on said bus can be stored in register 22 at a clock signal and by activating the selector line. This signal is normally generated in the microprocessor, not shown, in the system. A second set of inputs, RO-R15, to the elements R0-R15 in the register 22 is cross-connected to the outputs DO-D15 of the network 20. These cross-connections are represented by the crossing arrows 24.

The output DO is effectively connected to the input R15, D1 to R14, D2 to R13, D3 to R12, D4 to R11 ... and D15 to RO. The register 22 thus stores the mirror image of the binary data word appearing at the output of the network 20.

The outputs of the elements RO-R15 in the register 22 are connected to a bus 23, which serves as the output data bus for the device and also to feed back to the input of the shift network 22 the binary data word which appears at the output of the register 22. ' that the input data bus is only connected to the input of the register 22 from a practical point of view. It may just as well be directly connected to the input of the shift network 20. Function A better understanding of the circuit described above can be obtained from the following description of the function in connection with the timing diagram in Figure 4 and those illustrated in Figures 5-7. - examples.

The binary word to be shifted is applied to the lines 0-15 in the input data bus. At the same time, the selector line (one level) is activated and the data field for the shift size is sent to the shift control circuit 21. At the occurrence of the next clock pulse (two in Figure 4), the appropriate levels are activated in the shift network 20, the binary data array on the input data bus being stored in register 22. the entrance of the network 20 via the bus 23 and is thereby propagated. At the next clock pulse (tl in Figure 4), said data is stored in the register 22 and the operation is repeated except that the selector control line is not activated (0 level). Figure 5-7 illustrates the operation on a secondary word to achieve different functions.

Figure 5 illustrates the operation on a binary word to achieve a shift to the left by 7 positions. At the first passage through the device, the binary word is shifted to the left 7 positions (levels 1, 2 and 3 are activated), however, the resulting word is mirror-mapped in the register 22 due to the cross-connections 24. At the second passage the shift network is not activated at any level and due to the cross-connections 24, the register 22 contains the desired binary data word, which is available on the output data bus.

Figure 6 illustrates the operation on a binary word to achieve a shift to the right by 9 positions. At the first passage through the network, none of the levels is activated, but due to the cross-connections 24, the binary word in the register 22 is the mirror image of the binary word on the input data bus. at the second passage through the network 20, the binary data word in the register 22 is shifted to the left 9 positions (levels 1 and 4 are activated) and is stored again in the register 22 via the cross-connections 24. The binary data word _ in the register 22 represents a shift of 9 positions 7806741-0 to the right relative to the original binary data word and is now available on the output data bus.

Figure 7 illustrates the operation of a binary data word to achieve isolation of a data field within the word. It is desirable to isolate a data field comprising bits 3-6 of the binary word and to place it at the least significant positions in the word. At the first passage through the network, the word 9 positions are shifted to the left (levels 1 and 4 activated) and as a result of the cross-connections 24, the resulting data word in the register 22 includes the mirror image of the data field located at the least significant positions with bits 0, 1 and 2 in addition. These are removed from the floor by re-passing through the shift net with a shift to the left of 12 positions (levels 3 and 4 activated). The resulting binary word in register 22 contains the desired data field located at the least significant positions of the word with the remaining bits of the word in the form of zeros.

In general, the function of the circuit can be summed up as follows. For a shift to the left Y bit positions of a binary word with N-bits, the binary word Y positions are shifted to the left at the first pass through the circuit and 0 positions are shifted during the second pass. For a shift to the right X bit positions, the binary word O bits is shifted at the first pass through the circuit and X positions are shifted to the left during the second pass. If it is desired to isolate and adjust a data field with W-bits to the right, which field is D bit positions from the most significant end of the word, the binary word D positions are shifted at the first pass through the circuit and NW positions are shifted at the second passage.

As can be seen from the examples above, each shift function to the left or right and each data field isolation or masking function requires two passages through the device. These correspond to two microinstructions of a microprocessor, which with current technology can easily work on one. _..._..._......... 7806741-0 basis of 50 nanoseconds per instruction. Thus, according to the invention, a bidirectional parallel shifter and data processing circuit is provided, which performs all its intended functions for a constant time and for minimal real time.

It further has the advantages of being simple and economical, to which it can be achieved using commercially available bearing components. These advantages are obtained in part due to the fact that only the hardware required for shifting in one direction is required.

The above-described embodiment of the invention utilizes a shift network for shifting a binary data word to the left. It will be appreciated that the invention is equally suitable for a shifting device utilizing a right shifting network. It requires only an inversion and a replacement of shift functions for the first and second passages through the device. Let us consider, for example, the case according to Figure 5, where it is desirable to obtain a shift of 7 positions to the left using a shifting net to the right. At the first passage through the network, none of the levels is activated (no shift) and the word in the register 22 constitutes the mirror image of the original word. At the second passage, the word in register 22 shifts to 7 positions to the right and is mirrored as a result of the cross-links 24. The resulting word in register 22 represents a shift to the left 7 positions relative to the original word. Of course, it is understood that if a right-shifting network is used, the masking function results in the bits in the isolated field being adjusted to the left, ie the field occupies the most significant positions in the word in the accumulator register.

Claims (6)

78067h1'Û Patentkrav 1. For shifting an incoming binary data word by N bits each number up to N -1 positions to the left or right using a shift network (20) arranged to shift a binary word each number up to N -1 positions in only a predetermined direction, characterized in that the incoming binary word is passed through the shift network (20) for the first time to impart to it a first position shift in one direction, that the relative positions of the bits in the binary word obtained from the first passage is changed to form the mirror image of the word, that the mirror image of the word is passed through the network to give it a second position shift in said one direction, and that the relative positions of the bits in the binary word obtained from the second passage through the network is changed to form the mirror image of this word, whereby the obtained second mirror image word represents the desired position shift to the left or you right of the original binary word. Parallel bidirectional shift circuit for shifting a binary data word by N bits of any number up to N -1 positions to the left or right, characterized in that it comprises a shift network (20) for shifting a binary data word any number up to N -1 positions in a predetermined direction, which shift network has N output lines, and a data register (22) with N storage positions and N input lines, that the output lines from the shift network are cross-connected to the input lines of the register, so that a binary word such as stored in this from the shift network forms the mirror image of the binary word that appears at the output of the network, and that the output of the register is fed back to the input of the shift network (20). Circuit according to claim 2, characterized in that the shift network (20) has a plurality of shift levels (A, B, C, D), each comprising a plurality of gates (O-15), the gate the gates in each level of the network (20) are logically connected to the gates in the previous level for shifting a binary data word at the output of this a predetermined number of positions in a predetermined direction, that the gates in each level are also logically connected to the gates in the previous level for transmitting a binary data word at the output thereof without position shift, and that the circuit further comprises means for receiving signals (S1, S2, S4, S8) for controlling the operation of the gates in each level. Circuit according to Claim 3, characterized in that each of the gates in each level of the shift network consists of a data selection gate with a double input. Circuit according to claim 4, characterized in that it comprises a plurality of input and output connections (O-15) for interconnection with input and output data buses, respectively, that each storage element (RO-R15) in the data register (22) comprises a data selection gate with double input, which has a first input connected to one of said input connections (0-15), a second input cross-connected to the shift network (RO / D15 - R15 / DO), and an output connected to the input of the storage element , wherein the output of each storage element (RO-R15) is also connected to a respective one of the output connections, and that the circuit further comprises means for receiving signals for controlling the operation of the data selection gates. Circuit according to claim 5, characterized in that it comprises means (21) for receiving signals for controlling the storage of an input data word in the data register and for circulating the word twice through the shift network and the data register.