SE414360B - PROCEDURE FOR PHASE SYNCHRONIZATION IN A SYNCRONIC DATA TRANSMISSION SYSTEM AND DEVICE FOR EXECUTING THE PROCEDURE - Google Patents

Description

7810735-'6 5. f * 10 (\ 15 f * 20 f * 25 2 phases. (Ein Verfahren zur Dnteníihertrngung auf Primiírgruppenverhinduxng- en NTZ 29, 1976 I [.6 p.1z119-1452). The method entails a complicated analog signal processing and is also dependent on that the transmitted binary data signal contains on average as many ones as zeros.Furthermore, an averaging of the error signal over a large number of data bits is required, which results in long synchronization times.

It is further known a method which, in systems with adaptive equalizers of the transverse type, uses the pin settings of the equalizer for generating a control signal for the bit and carrier phases. (IEEE Transactions on Communication, Sept. 1975, pp. 976-979). This method is well suited for transmission systems where channel equalization with adaptive equalizer is required, but becomes complicated and expensive where so. is not the case.

Regulatory part of the invention.

The technical problem which the present invention seeks to solve lies in providing phase synchronism in the detection of data signals of the kind mentioned.

The indicated solution uses certain sorted zero crossings in the baseband signal obtained after demodulation on the receiver side to create suitable control signals for the phase correction. Further features of the invention appear from the characterizing parts of the appended claims.

The advantages of the indicated solution include a very fast phasing-in process and a large capture area without the use of any special starting process or irritating and the possibility of a realization entirely in digital technology.

Fiïbeskrivning.

The invention will be described in more detail below with the aid of an exemplary embodiment in connection with the accompanying drawing, in which Fig. 1 shows a block diagram of a transmission system in which the invention is shown. “U 10 15 20 25 7810735 '-6 the finding is used.

Fig. 2 shows a so-called Partial Response pulse, Fig. 5 shows associated values of. some signals in the system, Fig. 4 shows a receiver in which the principle of the invention is used, Fig. 5 shows a sorting circuit included in the receiver according to Fig. I: and Fig. 5 shows associated values of some signals on the receiver side of the system.

Preferred embodiments.

The exemplary embodiment described below relates to a synchronous data transmission (64 kb / s) on a 12-group connection in a carrier frequency system. For such a transfer, CCITT has recommended the above-mentioned modulation, ie.

SSBAM-PR IV (Single Side Band Amplitude Modulation »- Partial Response Class IV).

Figure 1 shows in greatly simplified iom, a block diagram of a transmission system for such a transmission. A binary pulse train was transmitted from a data source 1, which is thus desired to be transmitted to the receiving side. An encoder 2 treats this pulse train in this way. that a resulting binary pulse train bn, i.e. the output of the precoder has correlative properties. This means that the value of the signal bn at each pulse moment is a function not only of the simultaneous value of the signal but also of a previous value of the signal bn.

In the example, b = a (9 b applies, i.e. the value of the signal b in each n n n-2 n time is a modulo -2 sum of the simultaneous value of the signal an and the signal b value two time periods earlier.

This: Ear coding does not affect the spectrum of the baseband signal but provides great advantages in the detection on the receiver side, which will be shown below.

The signal bn is applied to a pulse shaper 3, which according to the Partial Response concept for each one in the signal bn emits a so-called Partial Response pulse, the appearance of which is shown in Figure 2. An individual such pulse g (t) apparently has a duration which extends over several periods T in the data signal. The time function of the signal g (t) can be written ~;, -., _ Stf-g; - '-, -_- V,; _ ~ _; -_.-_,' ~; - ~ âf .-; :: . -_. '<§ \ I «fi * -} -, ä: _: str-T -..-».-..-_ ,. »I P-'Ägïšifa 'yT-Yå-ÅÉÜ- fl -e-i-V' - ..;, _ .. ~. 7810735-6 li 77 2 .sinl-t g (t) = - í: -ïTf-í »_ (f) -1 där å- 'oetecknar datahastigheten.

The output signal fl t) of the pulse shaper 3, which is the baseband signal of the transmitter side, thus consists of a number of such pulses g (t) time-shifted nT 'n = 1, 2, u .. in relation to each other. The signal f (t) can thus be written as a sum f * fßb) = 2 bn g (t-nT) n = 0, _- 1 _-_ 1, ¿-_2, ...- where bn is equal to zero or one as above. f * The signal f (t) is allowed in a SSB modulator II to modulate a carrier supplied to the modulator from a carrier source 5 with the frequency 2nd, in the example equal to 10 1 (7) 0 kHz, the lower sideband S ('h ) are used. The signal KSÜD) can then be written A s (1>) = å [fm cos wet + f (1 =) sin wet] A _ where f (f,) is the baseband signal's Hilbert transform.

A _ fa) = Zbnê (Jo-nr), n = o, i'- 1, i 2, and tp 15 ê (t) = _ ¿2_ 1 + cos7fT 77 t 2 ('11) - 1 (h Before the lower sideband signal S (t) as above is transmitted to the receiver side on the line 7, a signal cos wet with an arbitrarily fixed phase position is also added from a pilot tone source 6.

The function and structure of the receiver side is also schematically represented in figure 1. A demodulator 8 demodulates the transmitted one. the signal by means of the pilot tone applied to the transmitter side and filtered out on the receiver side with the angular frequency wc. The baseband signal thus obtained is applied to a data detector 9, which at its output emits a signal aå, which thus has to imitate the signal on the transmitter side as much as possible. The signal 25 is now applied to a data sink 10. -, -; -.-: - ,, 55: * '-z-a'. f- jmf-g-v-: LI-Q V 51.3 * - 1, - «__. Figure 15 shows associated values of some signals in the system. The signal an is, as previously mentioned, the information-carrying signal which is desired to be transmitted, and the signal bn the signal at the output of the encoder. To illustrate how the baseband signal f (t) is formed on the transmitter side, the signal has n. g shows a simplified partial-response pulse for each one in the signal. bn. Summing these pulses with their respective time offsets: the previously mentioned three-level signal f fi i) is obtained.

If it is assumed that the demodulation takes place in the frequency and phase direction on the receiver side, then the baseband signal f (13) must be recreated. The signal dn in Figure 3 is intended to illustrate a sampling signal, the frequency and phase of which have been reproduced in the receiver by means of information in the transmitted baseband signal. If one samples the recovered baseband signal f (1'-) with the signal dn in a data detector and thereby interprets a zero as a zero and both plus and minus one, as a one, a signal aa is obtained, which in the example shown according to the figure a phase-shifted version of the information-carrying signal on the transmitter side.

Figure 3 also clearly shows how both a frequency and a phase deviation from correct values for the signal dn would give a different appearance for the signal aå and thus introduce data errors in the transmission.

Furthermore, if in the receiver the demodulation of the transmitted signal SUF) takes place with a phase error 'P, it can be shown with the previously used designations that the recovered behavior r (t, f) after fine tuning can be written r (t, f) = f (t) . tes f + in). its? It is thus clear from this mathematical writing that the demodulation must be coherent, ie. the demodulation carrier must: Eassyilchronize (“P = O) with the modulation carrier in order to recover an undistorted baseband signal f (t). Of course, incoherent demodulation has consequences for the appearance of the detected data signal al: ooh also introduces data errors in the transmission.

However, there should be, as one can perhaps conclude already after a relatively superficial analysis of the problem, a connection between sampling phase Ä and demodulation phase error ~ P, which gives optimal detection, ie. a recovered data signal al; with lowest error rate- I an article in TRïl-: NSAC- '7810735-6 10 15 20 25 30 TIONS ON COMMUNICATIONS, FEBRUARY 1975 pp.259-265. "THE EFFECTS OF EQUALIZATIDN, TIMING AND CARRIER PHASE ON EYE PATTERNS OF CLASS-l: PARTIAL RESPONSE DATA SIGNALS" it has been shown that such a relationship exists for sensory values of the variables Y and Å within certain given limits. You can define a phase plane with the variables “P and Ö along the axes in a right-angled coordinate system. The values of the variables “f and Å for which a scissor band as above can be derived form an area 91 in the phase plane. The remainder 'of the phase plane can be denoted 92. For the area 91 in the above reference the relation has been derived to * P a JT, OPT where J is the sampling phase and 70 is the demodulation phase error.

Provided that in the synchronization procedure you end up in phase: i. area 91, it is thus necessary to converge towards the state 'F = Ä = 0 taking into account the aforementioned relationship. Should one end up in the area 92 in the initial stage, the condition must first be suitably transferred to the area 91 before the procedure as above is applied.

Figure 5 shows the baseband signal r (t, f ') demodulated on the receiver side, and the sampling signal K1 for the subsequent detection. The sampling times are determined by the positive edge in the signal K1, which has the period time T and the phase J. The fixed state f, d 'of the receiver is assumed to be in area 91 as above. The phase position of a zero crossing in the signal r (t, f) in the time interval (nwâ, - T has - is denoted by 51. It can then be shown that if a '. A_'. A '= 1 at m-1 m + 1 m error-free detection 'then 61 will end up in the phase interval in E'. 77 '<61 <17 Furthermore, it can be shown that the statistical distribution of J 1 by random data sequence is such that the probability Pmb P1 <3% = Prob {J1> 24%? = I: A 17 'with common mathematical designations. The value J1 = JM = ä; thus forms the median. 10 15 20 25 S0 781073576 However, the optimal detection phase position JOPT for a given value of the iasielet * P in area 91 has as above could also be derived to just the value 2 * P-. If one thus sorts out zero crossings as above, ie fl "between two ones in the recovered signal from the demodulated baseband signal and regulates the sampling moment towards the time of these sorted zero crossings, - for statistical reasons, you will automatically find the optimal sampling layer JOPT - JM - n.

Two for the synchronization, ie. the convergence of the receiver towards the fixed state 'P = ¿' = 0, useful control signals D1, D2 are now formed in the (m + 1) th bit interval according to DI = 1 if aåhl-a:. aå fl = 1 and 'd1 D1 = 0 otherwise D2 = 1 if a' .a-r.a '= 1andJ1> J m-1 m m + 1 D2 = 0 otherwise where ö' is the detector moment's recognition moment, ie. bit rate: Eas position, and J 1 as before is the phase position of the sorted zero crossing in the signal r (t, ~ P).

A one in the signal D1 is now reduced: fi the axis position J of the sampling signal K1 with an increment increase the motivating phase position by the same amount. An equilibrium position is then reached on average AJ while a one in the signal D2 is caused by the same number of ones appearing in the two signals D1 and D2 per unit time, the phase K1 of the sampling signal obtaining a value Ö = -gïrtg which according to the above allows optimal detection for a given value on the phase error 'P.

To reduce: Easfelet 'P to in the vicinity of "P = 0, whereby the sampling phase J also goes towards zero as above, one can form two further control signals G2 and CS using zero crossings for which it applies that" eel-z' "In ° ä '" du = 1 ie zero crossings at the sign sequence 1 1 0 1 in the signal aå. If you add the condition that the signal r (t, * P) must not have. The shift sign in the time interval between the detection, which gave the values 7810735-6 '10 15 20 25 “Ål-z Tecken- (z fl m 1), so you can show show that: for the zero crossing at the phase Ål and alihl, a condition that we here denote with Tecken (aäb2) = applies ._? 7 _'-, Ão and É- fi f-f-æ J1 <-íïl- for 1 ° <o signeiernn 02 and cl; the car now in the (now) = e ibit interval according to c2 = 1 nmaåhrnåhfš .n¿ + 1 = 1nnh 6146 and Character (a¿1_2) = Character (aàbl) G2 = Û otherwise 'C3 = 1 oma¿1_2. Aàhi .zgl-.aå + l = loch J1> J and Character (aàka) = Character (an'1_1 ) G3 = 0 otherwise with the same designations as before In a one. In the signal C2 is brought to increase the phase 'P by an increment -NP while a one in the signal G3 is reduced: The base by equal. very. An equilibrium position is thus obtained when the phases P and d 'are both substantially equal to zero, whereby both optimal demodulation and optimal detection have been obtained, i.e. the receiver is synchronized.

Should at the beginning of the synchronization process the receiver's fixed state (7.5) be in the previously mentioned area 02, it applies, thus to partly cover this and quickly transfer the receiver to a fixed state in area 91 where the convergence method just described can be used.

In area 02, as previously mentioned, there is no stable locking position and no convergence algorithm for reading. This means that the probability of violating the inherent code restriction of the partial-response signal increases sharply, which ratio can thus be used, as an indication that the solid state is in area 02. In order to detect such violations of the code-10 15 20 25 - if "ëàiiovzšï-És In the restriction, the r (t, “P) of the demodulated signal is compared to two levels of symmetry located around a zero level and then binary signals A1 and A2 are formed. If at the moment of detection the signal r (t,“ P) is positive, level, the signal A1 is equal to one, otherwise equal to zero, in the following bit range, similarly to the signal A2 equal to one when the signal r (t, f) at the sensing moment is less than the real negative levelman's equal to zero in the following bit interval.

Based on these signals .A1 and A2, one can now form a control signal Dj in the mth time interval such that (n3) m = (Note (Du) m_2 + (A2) m. (Nuínhz where the binary auxiliary signal D11 is formed according to (nlgm = (A1) m + (A2) m. (N4) m_2 The designations (A1) m, (A2) m etc. - refer to the value of the binary signal A1, A2 etc. in the thirteenth time interval (m + J) T <t <(m + 1 + J) T with previously used designations.

According to the above, the control signal DS becomes equal to one in the detection interval if a violation of the Partial-Response restriction has occurred and zero otherwise.

The control signal can thus be used both to correct the phase position f ”of the recreated demodulation carrier, as well as to correct the phase position J of the bit rate.

If the correction is always made with the same sign, ie. for example, the phase position is constantly increased and in addition the phase regulation of the carrier is done faster than the bit rate, different phase combinations * P, J will be searched quickly. until the error pulses in the signal DB cease, which indicates that the fixed state (“P, ¿) has ended up in the range 01, which was the intention. In this area, according to the above, there is a convergence algorithm and the system thus locks in against the fixed state “P equal to J equal to zero.

Figure I: shows, as mentioned, a receiver in which the principle of the invention is used. The units 8, 9 and 10 according to figure 1 can in figure 1; are identified as the demodulator DM, the data detector DT and the data transmitter DS, respectively. The other units according to Figure 1i cooperate according to the idea of the invention to an adjustment of the correct demodulation phase (“f = 0) while the baseband signal r (t, * P) is constantly sampled. optimal phase Yes ". The transmitted sideband S (t) with the added pilot tone with the frequency 100 kHz is thus received from the line 7 of the demodulator DM. The same signal is also applied to a digital phase-locked loop CR, which locks on the pilot frequency and on. output, a binary signal C1 with the frequency 100 kHz 0311 emits an arbitrary fixed phase position.The signal C1 is in turn applied to a phase correction circuit FK input, which phase correction circuit, depending on the signals at three control inputs via its output connected to the demodulator DM carrier input C1, carries a carrier signal an optimal phase position after the oscillation process of the device.

The demodulator thus emits at its output the baseband signal r (t, * P) as above, which is thus at any given moment a function of the phase deviation 'f phase deviation' f from the optimum value.

In a data detector DT connected to the output of the demodulator, the baseband signal is then decoded in order to reproduce the original data signal transmitted from the transmitter side. The properties of the baseband signal have been shown above. such that a decoding per se could be available so that the hasband signal was first rectified and then sampled and compared against a fixed level. However, for special reasons, which appear from what has been mentioned above, in the example shown, a data detector is used in which the baseband signal is not first rectified. This means that the sampling values must be compared against two levels L1 and L2, symmetrically located around the zero level.

These detection levels are obtained according to the prior art from the signal energy or signal amplitude in the baseband signal r (t, 'P), which is connected to the input of a level circuit AD. Said level circuit has two. outputs connected to the detector, one for each level L1 and L2 respectively.

The sampling signal K1 necessary for the detection is formed on the receiver side or the use of disciplinary information in the transmitted baseband signal. Such tactinfomntiolx is available bLa. i_ busbandssignulcns nollgenomgângar, ßp. Which are therefore detected in a zero-pass detector ND, which at its output emits a short-lived pulse each time the baseband signal r (t, f) changes polarity.

If we assume for a moment that the sampling signal K1 is recreated with the appearance shown in Figure 5 and in the data detector DT, the baseband signal r (t, f) samples according to true figure and further compares the collection value against the two levels L1 and L2 plotted in the baseband signal. , signals A1 and A2 are obtained at the output of the detector. The sampling time is then determined by the positive-going edge of the sampling signal or the so-called bit rate Kl.

If at the sensing moment the signal r (t, ~ P) is greater than the level Li, the signal A1 is equal to one, otherwise equal to zero, in the following bit range. Correspondingly, the signal A2 is equal to one when the signal r (t, f) at the sensing moment is smaller than the level L2, otherwise equal. with zero in the following bit range as previously described. If these two signals A1 and A2 are then summed in an EllJšR circuit S, the detected date signal A3 is obtained, according to Figure 6, which in a disturbance-free transmission system constitutes a delayed version of the transmitted signal and has previously been designated as such. The signal A3 equal to that in Figure 1r is connected to the data depression DS.

Now, as previously shown, zero crossings of certain categories are particularly interesting when it comes to forming control signals partly on the iascorrection circuit FK according to the above and partly on a digitally controlled oscillatoi 'TK for sampling signalsx Kl. In order to sort out the interesting zero-through gurks, a sorting circuit SD with a number of inputs and outputs is arranged. This sorting circuit is shown in more detail in Figure 5.

The output signal B1 from the zero crossing detector ND, which is also shown in Fig. 6, is applied to one input of a phase detector FD while the bit rate K1 with the instantaneous phase is applied to the second input of the detector. The detector FD emits two binary output signals B2 and H5. When a detected polarity change in the baseband signal r (t, 7 °) occurs in a time interval when the bit rate signal K1 is equal to a ie. with previously used designations when the phase tf 1 is larger than the phase J, “the output signal BS becomes equal to one. Correspondingly, the output signal H2 becomes equal to one if a pulse in the signal B1 occurs when the signal K1 is equal to zero, ie. when phase Ö l. is less than phase J.

Both output signals B2 and BB are reset by negative edges in the signal K1, '7810735-6 10 15 20 .25 12 ie. at the times t = (m + d '+ T.

The signals B2 and BB are in the sorting circuit SD respectively connected to a clocked one-bit register REG 3 resp. REG 11. These. registers are clocked by negative edges in the bit rate signal K1, which in the sorting circuit is connected via an inverter I to the clock inputs of the registers.

To the sorting circuit SD according to Fig. 5, the detected data signal A3 is also equal to -aå connected in such a way that it is input to a three-bit shift register REGI. The first two bits of this register, which thus contain the two most recently clocked signal values, together with the instantaneous value of the signal A3 are combined in an AND circuit E so that this gives a one in its output signal A11 then. the bit sequence one-zero-one has been detected i.e.

(Anm = (Anm_2 - (Anm - (Anm) This is according to the above just such a zero crossing you want to sort out.

The output signal H4 from the register REGS is combined with the signal A4 in an AND circuit F with the output signal D1. Thus, since a negative edge in the bit rate signal K1 clocks in the signal H2 equal to 1 in the register REGS and thereby makes the output signal B11 equal to 1, this means that during the second half interval of the previous bit interval a zero crossing in the baseband signal r ( t, ”f).

This zero crossing is apparently the same as gave rise to the registered zero bit in the register's REG 1: first bit position.

When the signals B1; and Al: as above is at the same time equal to one, the output signal D1 from the AND circuit I "consequently becomes equal to one. With the conditions given above, the current positive bit rate field is thus phased after the detected zero crossing (compare 'e.g. In addition, the phase difference is less than 1800, so that an adjustment of the bit rate phase to the zero crossing, with the least change in the bit frequency, is achieved with an increase of the signal Kl manen path.

The signal D1 constitutes one of the output signals from the sorting circuit SD and is connected to one control input of said digital controlled oscillator TK.

A one in the signal D1 thereby increases the frequency of the oscillator, which by its output is connected to i.n. . the detector's DT sampling input, thereby reducing the phase difference between the positive edge of the collection signal and the detected zero crossing as this is of the sorted category described above.

Correspondingly, a negative edge in the signal K1 can clock the signal B3 equal to one in the register REGà, whereby its output signal B5 becomes equal to one. When this happens, this means that during the previous half period in the bit rate signal K1 a zero crossing has been detected in the signal r (t, f) but this time with a position relative to the positive edge in the signal K1 such that the fastest adjustment is achieved by a reduction of the instantaneous frequency of the signal K1. Therefore, in the same way as before, the signals A4 and B5 are combined in an AND circuit G with an output signal D2, which thus in the same way as the signal D1 is allowed to actuate the oscillator TK but in this case on a control input where one produces a decrease in the output signal. K1 instantaneous frequency. As far as the system described above is concerned, it apparently achieves the desired adjustment of the sampling phase towards an optimal position with the assumed demodulation phase error 'f. Of course, the solid state (19, J) must also be assumed to be in the previously mentioned area 01.

According to the described method, the control of the demodulation phase should be based on sorted zero crossings at the sign sequence 1101 in the signal reach. Thus, the register REG1 according to Fig. 5 contains the bits 110, mentioned in the order in which they are inserted, and the next bit in the signal A5 is a one, so as before the signal Aä will be equal to one but also the output signal from the AND circuit H, which on its two inputs are fed with the signal A4 and the output from the first bit position of the register HEG1.

According to the method, an additional criterion would be added to the sorted zero crossing, namely that the signal r (t, f) should not have the shift sign in the time interval between the two detections, 'which gave the two first substituted values (two ones) in register REG1. That this criterion is met can be tested by means of one of the two signals A1 and A2 on the output of the detector DT. In the example shown, the signal A1 has been selected, which is also shifted into a three-bit shift register REG2. An EXCLUSIVE OR circuit N with inverted output senses the first two bits now in the register REG2 and thus gives a one at its output then the said ka). "7810735-6 10 111 criterion is met. An auxiliary signal A5 is now formed with an AND circuit M, the two inputs of which are connected to the outputs of the circuits H and N. In this case it is only true that (A5) m + 1 = (Awnwl '( Ayn-Q '[(A1) m-20 (AÜm-1 J Information on flm. Thus sorted the occurrence of the zero crossing in relation to the phase of the current sampling signal is obtained as before from the signals B1 and B5, and by means of two further AND circuits P and Q, two control signals G2 and CS can now be formed according to C2 = A5, B1, and C3 = A5 - .BS The signals G2, and G3 are connected to two of the control inputs of the phase correction circuit FK and provide, as previously mentioned, at a one in each signal a positive and a negative adjustment, respectively, of the phase of the demodulation carrier C11, and an equilibrium position is obtained according to OVQD.

A device according to the above thus solves the problem posed with the phase synchronization and thereby has the advantages stated, all provided that the fixed state ("P, d ') at the beginning of the synchronization is in the range defined above _91.

Should this not be the case, the method described above also provides a solution to this problem. In this way, the locking range is expanded to include all barrel states (f, J).

In the receiver according to Fig. 11, an error detector ED is arranged to receive at its three inputs the signals A1, A2 and K1. The output signal DE, which is formed from these signals so. as indicated above, thus indicates with a one that a violation of the code restriction of the Partial-Response signal has been detected. The signal is applied to the third fl control input on each circuit TK and FK and in these circuits causes the signal changes indicated above, whereby the phase state is quickly transferred to area 01.

Claims (3)

W) '7810735-6 Ü PATBNTKRAV 1 (1) Method for phase filling synchronization in a synchronous data transmission system, which transmits amplitude modulated carrier of a first frequency from a transmitter to a receiver by means of a single sideband of a second frequency train of a second frequency, the modulating signal derived from the binary pulse train being superimposed pulses of so-called bartial Response class 4 type and the transmitted signal in the receiver is first demodulated to baseband level by means of a carrier signal or pilot signal of said first frequency transmitted from the transmitter and recreated in the receiver, and then detected by means of one in the receiver from zero crossings in the transmitted baseband signal reproduced rate signal of said second frequency, characterized in that it comprises the following steps, A. From the result of zero crossings in the transmitted baseband signal a first category is sorted out which are related to the character sequence 101 in the transmitted binary the pulse train at error-free detection, B. For each such zero crossing in the transmitted baseband signal, it is determined whether the zero crossing in a first case is phased before or in a second case after a nearest, periodically recurring sampling moment defined by said beat signal, C. Each such decisive caused to affect the phase of the reproduced beat signal by one phase increment of a given constant size and with such a sign in each case that the phase difference between zero crossings of the sorted type and said sampling instant is gradually reduced. 2. A method according to claim 1, characterized in that it comprises the following steps, A. From the result of zero crossings in the transmitted baseband signal, a second category of those related to the sequence 1101 in the transmitted binary pulse train is sorted out at error-free detection and for which the baseband signal does not shift characters in the time interval between the detections which gave rise to the first ones in said sequence of characters, B. For each zero crossing belonging to said second category it is determined whether the zero crossing in a first case is phased before or in a 7810735-6 10 15 20 25 35 16 other cases after a near, periodically recurring somplication moment defined by said rate signal, C. Each such decision is caused to affect the phase of the recreated carrier signal with a phase increment of a given lconstaxnt magnitude and with such indicating in each case that the phase of the carrier signal is caused to converge and finally lock in an optimal demodulation phase mode. 3. A method according to claim 1 or 2, characterized in that it comprises the following steps, A. Based on signal levels determined at the detection in the baseband signal, it is determined whether there is a violation of the modulating code's inherent code restriction, B. Each positive outcome in the series of such decisions are caused to affect the phase of both the recreated carrier signal and the recreated rate signal with increments of the same sign. 11) A device for phased synchronization in a synchronous data transmission system, which system comprises a transmitter and a receiver for transmitting Partial-Response class f: single sideband amplitude modulated carrier and whose receiver comprises a demodulator provided with a carrier input and a data signal input provided with a clock signal input. which device comprises a carrier regenerator connected to the demodulator's carrier input as well as a rate regenerator connected to the detector's signal signal input comprising a digitally controlled oscillator with at least two controllers thereof, that the rate regenerator consists of a digital phase locked passages and an output, and phase detector with two inputs and two outputs, which in a manner known per se, depending on the mutual phase difference between the signals at the phase detector inputs, are arranged to provide control information to the two control inputs of the oscillator, that one of the phase detectors input is connected to osc illatorn output and its second input via a level pass detector are connected to the output of the demodulator, that the respective outputs of the phase detector are connected to said two of the oscillator sry inputs via a sorting circuit (SD) provided with at least three inputs and at least two outputs. one of said inputs is connected to the output of the data detector and is arranged to sort out and pass to the oscillator only such control information, which is related to detected level passages of a predetermined first. _- ~ .. ... - çffif 'category. 5 ~ f ~ 10 f * 15 20 f * f * ._. --- ....-..... _...,. 5) Device according to claim 4, characterized in that the carrier generator comprises a digital phase-locked loop of a per se known type with its setpoint input connected to the input of the demodulator to filter out the transmitted carrier from the transmitted signal, with its output is connected to the carrier input of the demodulator via a phase correction circuit (FK) controlled from two further outputs on said sorting circuit (SD), the sorting circuit being arranged to sort out and to the phase correction circuit passing only such control information, which is related to detected level throughput. a predetermined second category. Device according to claim 5, characterized in that it comprises a fault detector (ED) provided with three inputs and one output, one input of which is connected to the output of the oscillator (TK) and the other two inputs of which are connected to two outputs of said data detector, that the output of the error detector is connected to a further control input on each oscillator (TK) and the phase correction circuit (FK) and that the error detector is arranged to detect an infringement of the Partial Response signal's inherent code restriction and when such an output exists addition of a relatively large phase increment in the oscillator (TK) and the correction circuit (FK), respectively. vh fl msiïïun .v -neu-wJ-fßvfr- -fa