SE2000199A1 - Method for generating a non-jittering trigger signal in a node of a serial data ring-bus - Google Patents
Method for generating a non-jittering trigger signal in a node of a serial data ring-busInfo
- Publication number
- SE2000199A1 SE2000199A1 SE2000199A SE2000199A SE2000199A1 SE 2000199 A1 SE2000199 A1 SE 2000199A1 SE 2000199 A SE2000199 A SE 2000199A SE 2000199 A SE2000199 A SE 2000199A SE 2000199 A1 SE2000199 A1 SE 2000199A1
- Authority
- SE
- Sweden
- Prior art keywords
- counter value
- slot counter
- data message
- received
- message
- Prior art date
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/422—Synchronisation for ring networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/28—Flow control; Congestion control in relation to timing considerations
- H04L47/283—Flow control; Congestion control in relation to timing considerations in response to processing delays, e.g. caused by jitter or round trip time [RTT]
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
Abstract
A method for providing a trigger signal in a slave node (S1-SN) in a data ring-bus (1) is described, the method comprising the steps of receiving a master clock signal on the clock input (5), updating a slot counter value C with 1 for each clock cycle of the master clock signal received, and resetting the slot counter value C to 1 after the slot counter value C has reached a maximum value, Max, receiving a first data message on the data input (6), adjusting the slot counter value C to S, for the clock cycle in which the end of the first data message was received, wherein S is in the interval 2 to Max-1, receiving a subsequent data message after the first data message, and providing a trigger signal when the slot counter value C equals T, if the end of the subsequent data message is received when the slot counter value C is valid.
Description
METHOD FOR GENERATING A NON-.IITTERING TRIGGER SIGNAL IN A NODE OF A SERIAL DATARING-BUS TECHNICAL FIELD The present invention relates to a method for generating a non-jittering trigger signal in anode of a serial data ring-bus and to a node of a serial data ring-bus configured to generate a non-jittering trigger signal.
BACKGROUND ART Data ring-buses are common in a variety of technical applications. A serial data ring-buscomprises a master node and a plurality of slave nodes. The master node is connected withthe slave nodes by means of a databus which connects all the slave nodes in series. Themaster node and the slave nodes can transmit and receive messages on the data bus. lnaddition to the databus the master node is also connected to the slave nodes by means of oneor more clockbuses. The slave nodes may be connected in series in a ring also by the clock bus.Alternatively, each one of the slave nodes may be connected directly to the master node witha separate clock bus in a so called starcoupling. The data on the ring-bus may be serial data or parallel data. lt is more common to send the data on the ring-bus as seria| data.
A message sent from the master node on the databus may be a message with a question toone or more of the slave nodes to provide information, such as, e.g., status of the slaves, tothe master node. Alternatively, the message sent from the master node on the databus maybe a trigger message triggering an event in one or more of the slave nodes. As the messages inthe ring-bus are transmitted from slave node to slave node there is a delay from reception of amessage at a slave node to the transmission of the message from the slave node. The delay is predictable but may vary due to, e.g., jittering of the trigger signal.
Inkom till Patent- ochregistreringsverket 2020 -lß- Z 1 SUMMARY OF THE lNVENTlON An object of the present invention is to provide a method for generating a non-jittering trigger signal in a slave node of a data ring-bus.
Another object of the present is to provide a device configured to be arranged as a slave node in a data ring-bus.One of these objects is fulfilled with a method according to the independent method claim.Another of these objects is fulfilled with a device according to the independent device claim.
According to a first aspect a method is provided for providing a trigger signal in a slave node ina data ring-bus, which slave node comprises a clock input and a data input. The methodcomprises the steps of receiving a master clock signal on the clock input, updating a slot countervalue C with 1 for each clock cycle of the master clock signal received on the clock input, andresetting the slot counter value C to 1 after the slot counter value C has reached a maximumvalue, Max, wherein Max is an integer > 2. The method also comprises the steps of receiving afirst data message on the data input, adjusting the slot counter value C to S, for the clock cyclein which the end ofthe first data message was received, wherein S is in the interval 2 to Max-1,receiving a subsequent data message after the first data message, and providing a trigger signalwhen the slot counter value C equals T, if the end of the subsequent data message is receivedwhen the slot counter value C is valid, wherein a valid slot counter value C is S, and at least one of S-1 and S+1, wherein T 2 S+1, and wherein T 5 Max.
The data signal is such that a data message is sent with an interval being X-Max, wherein X is aninteger. By having the slot counter set in the interval 2 to Max-1 it is possible for the data signalto jitter one slot forward or backwards while still receiving the data message in the same intervalof the slot counter, i.e., in the same interval 1-Max of the slot counter. By having T 2 S+1 and TS Max it is assured that the trigger signal is provided no earlier than at the end of reception of a message and no later than before reset of the slot counter.The method is preferably controlled by clocked logic in the slave node.
The method according to the first aspect provides a trigger signal which is jitter free. 3S-1 may be considered to be a valid slot counter value C if the end of a subsequent data messageis received when the slot counter value C is S-1 before the reception ofthe end of a subsequentdata message when the slot counter value C is S+1, and S+1 may be considered to be a valid slotcounter value C ifthe end of a subsequent data message is received when the slot counter valueC is S+1 before the reception of the end of a subsequent data message when the slot countervalue C is S-1. The jitter may only occur between two adjacent slots. As long as the end of thedata messages are received in the same slot as for the first message it is not possible to knowbetween which two slots the end ofthe data message could jitter. When the first data messagewhich has jittered is received it is possible to determine between which two slots the end ofthedata message can jitter. The determined two slots are set to be considered as valid while all other slots are set as invalid.
An error message may be generated if the end of a subsequent data message is received whenthe slot counter value C is not valid. lf the end of a data message is received when the slotcounter value is not valid it is due to another reason than jitter. No trigger signal is provided if an error message is generated.
The slot counter value C may be reset if an error message has been generated for apredetermined number of times and/or with a predetermined frequency. By resetting the slotcounter value is meant that the slot counter value C is set to S for the clock cycle in which the end of the next data message is received.
Max may be equal to 5. This leaves space for valid slots to be 2-4 and for the trigger to be provided in a slot after reception of the end of a data message.S may be equal to 3 when Max is equal to 5. Thus, valid counter values may be 2, 3 or 4.
T may be equal to 5 when Max is equal to 5. This assures that the trigger signal is provided at least one clock cycle after the reception of the end of the data message.
According to a second aspect a device if provided which is configured to be arranged as a slavenode in a data ring-bus. The device comprises a clock input and a data input, wherein the deviceis configured to update a slot counter value C with 1 for each clock cycle of a master clock signalreceived on the clock input, and resetting the slot counter value C to 1 after the slot counter value C has reached a maximum value, Max, wherein Max is an integer > 2. The device is also 4configured to adjust, when a first data message is received on the data input, the slot countervalue C for the clock cycle in which the end of the first data message was received to a value S,wherein S is in the interval 2 to Max-1, and to provide a trigger signal when the slot countervalue C equals T, if the end of a subsequent data message, received after the first data message,is received when the slot counter value C is valid, wherein the device is configured to treat S as a valid slot counter value C, wherein T 2 S+1, and wherein T s Max.
The data signal is such that a data message is sent with an interval being X-Max, wherein X is aninteger. By having the slot counter set in the interval 2 to Max-1 it is possible for the data signalto jitter one slot forward or backwards while still receiving the data message in the same intervalof the slot counter, i.e., in the same interval 1-Max of the slot counter. By having T 2 S+1 and Ts Max it is assured that the trigger signal is provided no earlier than at the end of reception of a message and no later than before reset of the slot counter.The device is preferably implemented with clocked logic such as, e.g., an FPGA.The device according to the second aspect provides a trigger signal which is jitter free.
The device may be configured to treat N-1 as a valid slot counter value C if the end of asubsequent data message is received when the slot counter value C is N-1 before the receptionof the end of a subsequent data message when the slot counter value C is N+1, and wherein thedevice is configured to treat N+1 as a valid slot counter value C if the end of a subsequent datamessage is received when the slot counter value C is N+1 before the reception of the end of asubsequent data message when the slot counter value C is N-1. The jitter may only occurbetween two adjacent. As long as the end ofthe data messages are received in the same slot asfor the first message it is not possible to know between which two slots the end of the datamessage could jitter. When the first data message which has jittered is received it is possible todetermine between which two slots the end ofthe data message can jitter. All slots that are not considered valid are considered to be invalid.
The device may be configured to generate an error message if the end of a subsequent datamessage is received when the slot counter value C is not valid. lf the end of a data message isreceived when the slot counter value is not valid it is due to another reason than jitter. No trigger signal is provided if an error message is generated. 5The features described for the method may be combined also with the device according to thesecond aspect. Thus, the slot counter value C may be reset if an error message has beengenerated for a predetermined number of times and/or with a predetermined frequency. Byresetting the slot counter value is meant that the slot counter value C is set to S for the clock cycle in which the end of the next data message is received.
Max may be equal to 5. This leaves space for valid slots to be 2-4 and for the trigger to be provided in a slot after reception of the end of a data message.S may be equal to 3 when Max is equal to 5. Thus, valid counter values may be 2, 3 or 4.
T may be equal to 5 when Max is equal to 5. This assures that the trigger signal is provided at least one clock cycle after the reception of the end of the data message.
The method may comprise the step of issuing an event in the slave node in response to the trigger signal.
After detection of the trigger message a delay may be added before the event is issued tocompensate for the serial bus delay so that the event occurs at the nearly the same time in allslaves. lt will be nearly the same time as it is not possible to predict the actual delay due to thejitter aspect, but the method according to the invention resolves the problem with trigger totrigger jitter. The delay should be different for different slave nodes to compensate for the position of the slave node in the ring bus.
According to a third aspect a data ring-bus is provided comprising a master node and a pluralityof devices, according to the above description, as slave nodes in the data ring-bus. The masternode is configured to send messages with an interval of X-Max, wherein X is a an integer whichhas a fixed value. There might be periods where no trigger message is sent and X may changevalue after a number messages have been sent. As an example Max might be 5 and 27 messagescould be sent with a period of 1000 (5*200). Then there might be a pause of 800 (5*160) followed by 40 new trigger messages with a period of 900 (5*180) ln the following detailed description embodiments of the invention will be described with reference to the appended drawings.
BRIEF DESCRIPTION OF THE DRAWINGSFig. 1 shows a data ring-bus with a master node and slave nodes.
Fig. 2 shows a number of slots/clock cycles in which a message may be received and where a trigger signal is provided.
DETAILED DESCRIPTION Fig. 1 shows a data ring-bus 1 with a master node 2 and slave nodes S1-SN. The slave nodesS1-SN are connected to each other by means of a data ring-bus 3. Each slave node has a datainput 6 and a data output 7. The data bus 4 is connected to the input 6 of each slave node S1-SN. Each slave node read the data signal on the data bus 4 in order to check whether the datasignal contains any message to that slave node S1-SN. ln case the message is not intended forthat slave node or only contains information for the slave node to take some action, the slavenode may output the data signal on the data output 7 as soon as possible with as little delay aspossible. lf, however, the data signal contains a message requesting information from thatslave node, S1-SN, the slave node, S1-SN, must use the data bus 4 to send a response. Thisimplies that the master node have to schedule the request messages so that the slave node has enough time to answer without interrupting the trigger messages.
The data signal may comprise a trigger signal for triggering an event in the slave node. Thetrigger signal may come at periodic intervals in order to trigger events with predeterminedintervals. For some applications it is important that the trigger signal in each slave node occurswith an interval which is a multiple of a predetermined time period. An example of anapplication in which it is important to have the trigger signal at intervals which are multiples ofsuch a predetermined time period is a radar of the type active electronically scanned array(AESA). Each element of the AESA is a slave node in the data ring-bus, i.e., each slave node isthus equipped with a radar emitter 8 as is shown with dashed lines in Figure 1. The radar emitter 8 is connected to the trigger output 11 The slave nodes S1-SN are also connected to each other by means of a clock bus 4. The masternode 2 sends a clock signal on the clock bus 4. Each slave node S1-SN receives the clock signal and transmits it to the next slave node S1-SN. The clock bus continues through each one of the 7 slave nodes S1-SN. Each slave node S1-SN has a clock input 5 on which the slave node S1-SNdetects the clock signal on the bus as is indicated in Fig. 1. ln a data ring bus as shown in Fig. 1the data message will have to be retrieved using data recovery. Data recovery from a datasignal is a technique that is well known to a person skilled in the art and will not be explainedin more detail here. Each slave node comprises a processor 10 which is configured to controlthe slave node S1-SN. A computer program controls the operation of the processor 10. The processor 10 comprises a trigger output 11 for a trigger signal.
The method for providing a trigger signal in a slave node S1-SN in the data ring-bus 1 will nowbe described. The slave node S1-SN receives a master clock signal on the clock input. The slavenode S1-SN updates a slot counter value C with 1 for each clock cycle of the master clock signalreceived on the clock input, and resets the slot counter value C to 1 after the slot counter valueC has reached Max, wherein Max is an integer > 2. When the slave node receives a first datamessage on the data input, the slave node adjusting the slot counter value C to S, for the clockcycle in which the end of the first data message was received, wherein S is in the interval 2 toMax-1. Fig. 2 illustrates the slot counter C. ln the embodiment shown in Fig. 2 Max is 5, i.e., theslot counter will count from 1 to 5 and then return to 1. The slot counter C is set to 3 for theclock cycle in which the end of the first data message was received, i.e., it is defined that theend of the first data message is received in the third slot 13 as is illustrated in Fig. 2. Due tojittering a subsequent data message, received after the first data message, may be received inthe second slot 12 or the fourth slot 14. The second slot 12, the third slot 13 and the fourth slot14 are defined as valid slots. lt the end of a subsequent data message is received in the secondslot 12 it is determined that it is in a valid slot and a trigger signal is provided when the slotcounter value C equals 5, i.e., in the last slot before reset of the slot counter value. lt would bepossible to provide the trigger signal when the counter value equals 4 but in case the end of asubsequent data message was received in the fourth slot there would be very little time toprovide the trigger signal. By providing the trigger signal when the counter value C equals 5 thetrigger signal will not jitter. lt should be understood that an end of a data message is notreceived every time the slot counter is equal to three. A end of a data message is received withan interval being interval being equal to 5X, wherein X is an integer. The method is not dependent on the frequency of the data signal which, typically, has a frequency of 1-100 MHz. 8When the end of a subsequent message is received in the second slot the fourth slot is set asinvalid. The fourth slot is set as invalid as jittering can only result in the end of the data messagejumping between two adjacent slots or clock cycles. Any larger jump is not due to jitter but maybe due to, e.g., that the master node has restarted. Thus, after jittering of the data signal has occurred lf the end of the subsequent data message is received when the slot counter value C is invalidno trigger signal is provided. instead an error message may be issued. ln case of a predeterminednumber of trigger messages in a row that are detected in an invalid slot, the slave node mayreset the slot counter and set the slot counter for the end of the next data message to 3.Alternatively or additionally, the slave node may send a message to the master node requesting the master node to initiate an action such as, e.g., restarting.
The device may be configured to treat N-1 as a valid slot counter value C if the end of asubsequent data message is received when the slot counter value C is N-1 before the receptionof the end ofa subsequent data message when the slot counter value C is N+1, and wherein thedevice is configured to treat N+1 as a valid slot counter value C if the end of a subsequent datamessage is received when the slot counter value C is N+1 before the reception of the end of a subsequent data message when the slot counter value C is N-1.
The above described embodiments may be amended in many ways without departing from the scope of the present invention, which is limited only by the appended claims.
Claims (17)
1. Method for providing a trigger signal in a slave node (S1-SN) in a data ring-bus (1), which slave node (S1-SN) comprises a clock input (5) and a data input (6) configured to receive clata front a rnaster rrfacie, the method comprising the steps of - receiving a master clock signal on the clock input (5), - updating a slot counter value C with 1 for each clock cycle of the master clock signal receivedon the clock input (5), and resetting the slot counter value C to 1 after the slot counter value Chas reached a maximum value, Max, wherein Max is an integer > 2, - receiving a first data message on the data input (6), - adjusting the slot counter value C to S, for the clock cycle in which the end of the first datamessage was received, wherein S is in the interval 2 to Max-1, - receiving a subsequent data message after the first data message, and - providing a trigger signal when the slot counter value C equals T, if the end ofthe subsequentdata message is received when the slot counter value C is valid, wherein a valid slot counter value C is S and at least one of S-1 and S+1, wherein T 2 S+1 and wherein T S Max.
2. The method according to claim 1, wherein S-1 is a valid slot counter value C if the end of asubsequent data message is received when the slot counter value C is S-1 before the receptionof the end of a subsequent data message when the slot counter value C is S+1, and wherein S+1is a valid slot counter value C if the startfgaízíigof a subsequent data message is received whenthe slot counter value C is S+1 before the reception of the start of a subsequent data message when the slot counter value C is S-
3. The method according to claim 1 or 2, wherein an error message is generated if the end of a subsequent data message is received when the slot counter value C is not valid.
4. The method according to claim 3, wherein the slot counter value C is reset if an error messagehas been generated for a predetermined number of times and/or with a predetermined frequency.
5. The method according to any one ofthe preceding claims, wherein Max is equal to 5.
6. The method according to claim 5, wherein S is equal to
7. The method according to claim 5 or 6, wherein T is equal to
8. The method according to any one of the preceding claims, comprising the step of issuing an event in the slave node in response to the trigger signal.
9. The method according to claim 8, wherein after detection of the trigger message, a delay is added before the event is issued.
10. A device (S1-SN) configured to be arranged as a slave node (S1-SN) in a data ring-bus (1), comprising a clock input (5) and a data input (6) configured to receive data from a master emde, wherein the device is configured - to update a slot counter value C with 1 for each clock cycle of a master clock signal receivedon the clock input (5), and resetting the slot counter value C to 1 after the slot counter value Chas reached a maximum value, Max, wherein Max is an integer > 2, - to adjust, when a first data message is received on the data input (6), the slot counter value Cfor the clock cycle in which the end of the first data message was received to a value S, whereinS is in the interval 2 to Max-1, and - to provide a trigger signal when the slot counter value C equals T, if the end of a subsequentdata message, received after the first data message, is received when the slot counter value Cis valid, wherein the device is configured to treat S, and at least one of S-1 and S+1, as a valid slot counter value C, wherein T 2 S+1, and wherein T S Max.
11. The device according to claim 10, configured to treat N«1§_«_1 as a valid slot counter value Cif the end of a subsequent data message is received when the slot counter value C is N»1§_¿1_before the reception ofthe end of a subsequent data message when the slot counter value C iståla-ägt, and wherein the device is configured to treat šßwêï as a valid slot counter value C ifthe end of a subsequent data message is received when the slot counter value C is before the reception ofthe end of a subsequent data message when the slot counter value C is rama-gg.
12. The device according to claim 10 or 11, configured to generate an error message ifthe end of a subsequent data message is received when the slot counter value C is not valid.
13. The device according to claim 12, configured to reset the slot counter value C if an errormessage has been generated for a predetermined number of times and/or with a predetermined frequency.
14. The device according to any one of the claims 10-13, wherein Max is equal to
15. The device according to claim 14, wherein S is equal to
16. The device according to claim 14 or 15, wherein T is equal to
17. A data ring-bus (1) comprising a master node (M) and a plurality of devices (S1-SN) according to any one of claims 8-14 as slave nodes (S1-SN) in the data ring-bus (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE2000199A SE544972C2 (en) | 2020-10-21 | 2020-10-21 | Method for generating a non-jittering trigger signal in a node of a serial data ring-bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE2000199A SE544972C2 (en) | 2020-10-21 | 2020-10-21 | Method for generating a non-jittering trigger signal in a node of a serial data ring-bus |
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| Publication Number | Publication Date |
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| SE2000199A1 true SE2000199A1 (en) | 2022-05-28 |
| SE544972C2 SE544972C2 (en) | 2023-02-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023211320A1 (en) * | 2022-04-25 | 2023-11-02 | Saab Ab | Method for generating a non-jittering trigger signal in a node of a serial data ring-bus |
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| US9021292B2 (en) * | 2011-05-20 | 2015-04-28 | Texas Instruments Incorporated | Method and system for asynchronous serial communication in a ring network by generating an oversampling clock using a fractional rate multiplier and sampling a received data bit sequence that includes voltage and temperature information in a battery management system |
| KR101717407B1 (en) * | 2013-07-19 | 2017-03-16 | 미쓰비시덴키 가부시키가이샤 | Ring-shaped synchronous network system and time slave station |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023211320A1 (en) * | 2022-04-25 | 2023-11-02 | Saab Ab | Method for generating a non-jittering trigger signal in a node of a serial data ring-bus |
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