SE1550180A1 - Extended bandwidth digital doherty transmitter - Google Patents

Extended bandwidth digital doherty transmitter Download PDF

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Publication number
SE1550180A1
SE1550180A1 SE1550180A SE1550180A SE1550180A1 SE 1550180 A1 SE1550180 A1 SE 1550180A1 SE 1550180 A SE1550180 A SE 1550180A SE 1550180 A SE1550180 A SE 1550180A SE 1550180 A1 SE1550180 A1 SE 1550180A1
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block
signal
input
digital
output
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SE1550180A
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SE541265C2 (en
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Fadhel Ghannouchi
Ramzi Darraji
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Ramzi Darraji
Fadhel Ghannouchi
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Priority claimed from US13/563,621 external-priority patent/US8837629B2/en
Application filed by Ramzi Darraji, Fadhel Ghannouchi filed Critical Ramzi Darraji
Publication of SE1550180A1 publication Critical patent/SE1550180A1/en
Publication of SE541265C2 publication Critical patent/SE541265C2/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02Transmitters
    • H04B1/04Circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02Transmitters
    • H04B1/04Circuits
    • H04B1/0475Circuits with means for limiting noise, interference or distortion
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02Transmitters
    • H04B1/04Circuits
    • H04B1/0483Transmitters with multiple parallel paths
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/32Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36Modulator circuits; Transmitter circuits
    • H04L27/366Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator
    • H04L27/367Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion
    • H04L27/368Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion adaptive predistortion
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02Transmitters
    • H04B1/04Circuits
    • H04B2001/0408Circuits with power amplifiers
    • H04B2001/0425Circuits with power amplifiers with linearisation using predistortion
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2614Peak power aspects
    • H04L27/2623Reduction thereof by clipping

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

An extended bandwidth digital Doherty transmitter includes a baseband signal processing block including a digital predistortion unit. It also includes a digital signal distribution unit and a digital phase alignment unit, a signal up-conversion block, an RF power amplification block including the carrier amplifier and one or two peaking amplifiers; and an RF Doherty combining network. In another aspect, a digital Doherty transmitter includes a baseband signal block including a digital predistortion unit, a digital signal distribution unit and an adaptive digital phase alignment unit. In this aspect a signal up-conversion block includes three digital-to-analog converters (DACs) and a tri-channel up-converter or three single-channel up-converters. There is also an RF power amplification block including the carrier amplifier and two peaking amplifiers, and an RF Doherty combining network which includes quarter wavelength impedance transformers.

Description

PCT/CA2013/000578 EXTENDED BANDWIDTH DIGITAL DOHERTY TRANSMITTER FIELD OF THE INVENTION
[0001]The present invention relates generally to digital Doherty transmitters, and, more P' icularly to an extended bandwidth digital Doherty transmitter.
RELATED ART
[0002]To cope with the ever-increasing number of wireless networks users, modern wireless communication standards (3rd generation and beyond) employ spectrum efficient modulation and access techniques, such as quadratic amplitude modulation (QAM), orthogonal frequency division multiplexing (OFDM) and code division multiple access (CDMA). Although these techniques permit an efficient management of the overcrowded radio frequency (RE) spectrum, they also result in creating highly varying envelope signals that are characterized with high peak-to-average power ratio (PAPR). To avoid signal clipping and loss of transmitted information through distortion during power amplification, the transmitter should handle the peak values of the transmitted signal even though it mostly operates at significantly lower average power levels. Accordingly, the power amplifier (PA) of wireless transmitter is forced to operate at large back-off from its saturation point where the power efficiency of the PA drops drastically.
[0003]A popular power amplification architecture for enhancing the efficiency at backed-off output power region is the Doherty amplifier architecture. Fundamentally, a Doherty' amplifier is composed on 1) one main amplifier (commonly denoted as carrier amplifier) that is PCT/CA2013/000678 operating in class-AB and performing signal amplification for all input signal levels, 2) at least one auxiliary amplifier (commonly denoted as peaking amplifier) that is operating in class-C and performing signal amplification starting from a predefined signal level, 3) an input analog power divider for splitting the input signal between the carrier amplifier and the peaking amplifier(s). 4) a non-isolated Doherty output power combiner for combining the outputs of the carrier amplifier and the peaking amplifier(s) which includes quarter wavelength transformers, and 5) 50 Ohms lines inserted at the input of the peaking amplifiers andior carrier amplifier to balance the delay between the branches of the Doherty amplifier_ The use of a non-isolated power combiner initiates an active load modulation mechanism that is based on dynamically changing the load presented to the carrier amplifier through the impedance modulation triggered by the peaking amplifier(s). This allows the carrier amplifier to operate efficiently until it reaches its optimal load while the peaking amplifier(s) is/are simultaneously contributing to the output power of the Doherty amplifier. 100041Practically, the two-stage Doherty amplifier which consists of one carrier amplifier and one peaking amplifier; and, the three-stage Doherty amplifier which consists of one carrier amplifier and two peaking amplifiers are the most used architectures in Doherty based RF transmitters. Practical implantations of four-stage and higher order-stage Doherty amplifiers are rare and not fully convincing in their performance. The main reasons are the rather complex design and the excessive costs of implementation for no significant performance improvement as compared to the two or three-stage Doherty amplifier architecture.
[0005]Ideally, two-stag (three-stage) Doherty amplifier has two (three) maximum efficiency points located within a range of up-to 6 dB (12 dB) of output power back-off PCT/CA201.3/000679 relatively to the saturation output power point. This feature makes the two-stage and three-stage Doherty amplifiers the most suitable architectures for power amplification in 3rd generation and beyond wireless communications applications where the PAPR of the modulated signals is typically ranging between 6 and 12 dB. In practice, two-stage Doherty amplifiers are more suitable when the PAPR is about or slightly higher than 6 dB and three-stage Doherty amplifiers when the PAPR of the signal is significantly higher that than 6 dB. The achievet of such a superior performance requires a quasi-perfect load modulation mechanism which is not likely to happen in fully-analog implementations due to limitations related to inherent hardware impairments in the RF blocks of two-stage or three-stage Doherty amplifiers. [00061In the case of two-or three-stage Doherty amplifier, the dissimilarity in class of operation of the carrier amplifier and the one or two peaking amplifiers results in complex gain fluctuation between the output branches of the Doherty amplifier. As a result, the output signal amplitude from the carrier amplifier and the output signal amplitudes from peaking amplifiers do not match with the ideal current profiles governing the correct operation of the Doherty amplifier. This translates into an imperfect load modulation mechanism and degraded efficiency. 100071In a number of device (transistor) technologies (such as high electron-mobility transistor (I1EIVIT) and gallium nitride (GaN), etc.), the difference in bias conditions between the carrier amplifier and peaking amplifiers results in power-dependant and highly nonlinear phase misalignment within the output branches of the Doherty amplifier which causes severe output power loss, deficient load modulation and degraded efficiency. 100081Another problem related to the Doherty PA is the narrow bandwidth performance.
Indeed, due to the need for using quarter-wavelength impedance transtbrmers to design the PCT/CA2013/000678 output power combiner, the efficiency of the Doherty PA drops significantly as the frequency of operation shifts away from the design frequency of the Doherty PA (fo), which greatly limits its bandwidth.
SUMMARY OF THE INVENTION [00091In one aspect of the present invention, a digital Doherty transmitter has a baseband signal processing block, the baseband signal processing block including a digital predistortion unit, an adaptive digital signal distribution unit and a digital phase alignment unit; a signal up-conversion block, an RF power amplification block, the RF power amplification block including the carrier amplifier and one or two peaking amplifiers; and an RF Doherty combining network, the topology of the RF Doherty combining network is predefined and it depends on the number of stages and the settings of turn-on points of the peaking amplifiers of the Doherty amplifier system .
[0010]In the description of the invention, a three-stage Doherty amplifier will be used.
It is noted that a two-stage Doherty amplifier which includes one peaking amplifier may be considered in one sense a simple and special case of three-stage Doherty amplifier architecture that has two peaking amplifiers. [00111In another aspect of the present invention, a digital Doherty transmitter includes a baseband signal processing block, the baseband signal processing block including a digital predistortion unit, an adaptive digital signal distribution unit and a digital phase alignment unit; a signal up-conversion block; a signal up-conversion block, the signal up-conversion block including three digital-to-analog converters (DACs) and a tri-channel up-converter or three PCT/CA2013/000678 single-channel up-converter: an RF power amplification block, the RF power amplification block including the carrier amplifier and two peaking amplifiers; and an RF Doherty combining network which includes quarter wavelength impedance transformers, the topology of the RF Doherty combining network is predefined and it depends on the number of stage , mode and order of operation of the Doherty amplifier. 100121Further areas of applicability of the present invention will become apparent with reference to the following drawings, description and claims. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
PCT/CA2013/000678 BRIEF DESCRIPTION OF THE DRAWINGS 100131 The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 100141 Figure 1 is a block diagram of the digital Doherty transmitter architecture according to an exemplary embodiment of the present invention.
[0015] Figure 2 is one embodiment illustrating a detailed block diagram of the architecture of Figure 1, using a single tri-channel up-converter. 100161 Figure 3 is an alternate embodiment illustrating a detailed block diagram of the architecture of Figure 1, using three single channel up-converters.
[0017] Figure 4 is an example of a possible signal distribution scheme of an exemplary embodiment of the present invention. 100181 Figure 5 is an example of a possible phase alignment mechanism of an exemplary embodiment of the present invention. 100191 Figure 6 is a block diagram of the prior art. 100201 Figure 7 is an electrical diagram of the prior art. [00211 Figure 8 is a graph illustrating the ideal output currents profile at the fundamental frequency of the circuit of Figure 7. 100221 Figure 9 is an electrical diagram according to an emplary embodiment of the present invention shown in Figure 2.
PC91/CA2013/000679 [00231 Figure 10 is a block diagram of the architecture according to an exemplary embodiment of the present invention where the RF power amplification block has only one peaking amplifier. 100241 Figure II is another embodiment of the invention architecture shown in Figure 10, where the RF power amplification block has only one peaking amplifier, and a dual-channel up-converter. [00251 Figure 12 is an electrical diagram according to an exemplary embodiment of the present invention shown in Figure 11. 100261 Figure 13 is another possible block diagram of the architecture of Figure 10 where the RF power amplification block has only one peaking amplifier, and two single channel up-converters. [00271 Figure 14 is a flowchart illustrating the steps of the execution of the digital adaptive signal distribution algorithm performed by Digital Signal Distribution Unit of the Baseband Processing Block. [00281 Figure 15 is a flowchart illustrating the steps of the execution of the digital phase alignment algorithm for the Digital Phase Alignment Unit of the Baseband Processing Block. [00291 Figure 16 is a flowchart illustrating the steps of the execution of the digital predistortion (DPI)) algorithm for the Digital Predistortion Unit of the Baseband Processing Block. [00301 Figure 17 is a flowchart illustrating the steps of the Baseband Signal Processing Block of the present invention.
PCT/CA2013/0000S [00311 Figure 18 is a block diagram of the architecture when used in adaptive mode according to an embodiment of the present invention where high directivity couplers are used at the output of the R.F power amplification block. [00321 Figure 19 is a block diagram of the architecture of Figure 10, where high directivity couplers are used at the output of the RF power amplification block. 100331 Figure 20 is the measured performance of the prior art compared to a practical implementation of an eXemplary embodiment of the present invention,
[0034] Figure 21 is another measured performance of the prior art compared to a practical implementation of an exemplary embodiment of the present invention. 100351 Figure 22 is a simulated performance of the prior art compared to a practical implementation of an exemplary embodiment of the present invention.
[0036] Figure 23 is the measured performance, in terms of spectrum, of a practical implementation of an exemplary embodiment of the present invention.
PCT/CA2013/000C78 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 100371 The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. 100381 Broadly, an embodiment of the present invention provides a multiple branch digital Doherty transmitter architecture and digital signal processing algorithms for impairments-free operation and linearized three-stage Doherty amplifier. 100391 As seen in Figures 1-3, for a given mode of operation of the digital Doherty transmitter and starting from an initial baseband signal, shown at IN/Q[N, corresponding to a given communication standard, the baseband processing Block 20 generates three different input baseband signals filiN,Ani.c , [IN, PI/QIN, PI. I P2/QIN, P2) so that, after up-conversion via Signal Up-Conversion Block 28 and RE power amplification via R.F Power Amplification Block 44, the magnitudes of the currents at the input of the RF Doherty Combining Network 52 follow the ideal currents profile that is predefined depending on the mode of operation of the multiple stage Doherty transmitter. 10040,1 In order to boost the efficiency of the Doherty PA, the digital signal distribution unit 24 is implanted to adaptively distribute the available power between the input branches of the power amplification block 44 according to a specific power distribution scheme that is derived to ensure the quasi-ideal load modulation behavior at and beyond the nominal design frequency of Doherty PA. Figure 4 shows an example of a possible signal distribution scheme executed at the digital signal distribution unit 24 of an exemplary embodiment of the present invention where the RE power amplification block has only one peaking amplifier. The "Present PCT/CA2013/000678 Invention" graph line illustrates the digital Doherty transmitter, while the "Prior Art" graph line illustrates the state of the prior art. [00411 The baseband signals generated at the digital signal distribution unit 24 are further updated to compensate for any phase misalignment resulting from the non-linear behavior of the devices. The phase misalignment behavior is identified from the amplitude-dependent phase distortion (AM/PM) of the carrier amplifier and the (AM/PM) responses of the peaking amplifiers. The characterization can be achieved by only driving one amplifier at a time with its specific input signal generated at the digital signal distribution unit 24 and collecting its corresponding amplified signal at the output of the digital Doherty transmitter. The output RF signal is down-converted to baseband and benchmarked against the known driving input baseband signal which permits obtaining the AM/PM of the amplifier under test. In the case that the AM/PM responses of the three amplifiers follow similar trend (i.e., AM/PM is quasi-constant versus input power) but with a constant phase difference, a static digital phase alignment is applied to the input baseband data at the input of each peaking branch to align the AM/PM response of the peaking amplifiers with that of the carrier amplifier. In the case that the AM/PM responses of the peaking amplifiers do not follow the same trend as that of the carrier amplifier (i.e., AM./PM responses of peaking amplifiers fluctuate versus input power), an adaptive digital phase alignment is applied to the baseband data at the input of each branch to ensure that the AM/PM response of the carrier amplifier and those of the peaking amplifiers are overlapping at all time. This may be achieved by applying phase digital predistortion (PDPD) to each peaking input baseband signal. This results in three similar AM/PM responses having a constant phase shift that can be aligned as in the case of static phase alignment by just adding a constant phase PCT/CA2013/000670 offset to the input sigial. The graph presented in Figure 5 shows an example of a possible adaptive digital phase alignment of an exemplary embodiment of the present invention where the RF power amplification block 44 has only one peaking amplifier and where the carrier amplifier and peaking amplifier have dissimilar AM/PM characteristics. 100421 The digital phase alignment mechanism ensures the quasi-perfect active load modulation behavior (when the input signal is properly distributed at the digital signal distribution unit 24) and prevents the destructive power summation at the RE Doherty combining network. 100431 The digital phase alignment rneLhanlsm prevents the destructive power summation at the RE Doherty combining network. [00441 Both digital signal distribution unit and digital phase alignment unit ensure the quasi-perfect active load modulation behavior and impairments-free operation of the multiple (three) stage digital Doherty transmitter. [00451 To get the linear operation, the digital predistortion (DPD) is required. This can be achieved by considering the system that consists of digital adaptive signal distribution unit digital phase alignment unit 26+ signal up-conversion block 28+ RF power amplification block 44+ RF Doherty combining network 521 as device-under-test (Dun. As such, the initial characterization and DPI) model identification of the digital Doherty transmitter can be derived based on the initial input baseband signal and the equivalent baseband version of the RF signal at the output of the RI' Doherty combining network 52. 100461 A digital predistortion technique consisting of pre-processing an input baseband signal according to the complement of the transmitter response to compensate for its nonlinearity 11 PCT/CA2013/000678 effects. To achieve this correction, a complex function of the predistorter is determined while satisfying the following conditions: and...vo„,(t) with (x(t))]--- wheref and g represent the complex nonlinear functions of the predistorter and the PA/transmitter, respectively. G represents the smallsignal gain of the Doherty amplifier. The variables xi„ and x,,,, denote the input and output signals respectively. Bothf and g are determined using baseband records at the input and output of the Doherty transmitter.
Following the identification of the predistorter and its cascade before the digital signal distribution unit 24, one can write the following equation for the linearized transmitter: (t) = g[ (x, (t))I= [00471 Referring to Figure 1, the digital Doherty amplifier/transmitter architecture includes a baseband signal processing block 20; a signal up-conversion block 28; an RF power amplification block 44; and an RF Doherty combining network 52, the topology of the RF Doherty combining network is predefined topologies and is depending on the mode of operation of the multiple branch digital Doherty amplifier/transmitter of the present invention. The specific number of multiple branches n of the digital Doherty amplifier/transmitter of the present invention architecture is equal to one (carrier amplifier branch) plus the value n-1 which value equals the number of peaking amplifiers in a particular circuit. 12 PCT/CA2013/000678 100481 The baseband signal processing block 20 includes a digital predistortion unit 22, an adaptive digital signal distribution unit 24 and a digital phase alignment unit 26. The baseband signal processing block 20 is a set of digital signal processing algorithms best shown in Figure 17 that are implemented to ensure impairments-free and linear operation of multiple-stage Doherty amplifiers/transmitters at a given frequency of operation. In this regard, the implementation of digital predistortion unit 22 is best shown in Figure 16; the implementation of digital signal distribution unit 24 is best shown in Figure 14; the implementation of digital phase alignment unit 26 is best shown in Figure 15. The operation and algorithms performed by baseband signal processing block 20 allow for digital processing of digital signals, and for a digital signal output. [00491 In operation, the digital predistortion unit 22 is an algorithm that takes the initial input digital baseband in-phase/ q-uadrature (liN/QiN) signal to generate the predistorted baseband digital signal (Ip„d/Qp„d) intended to feed the digital adaptive signal separation unit 24 according to the equations stated above (see Figure 16). [00501 The digital signal distribution unit 24 is an algorithm that is applied (according to Figure 14) to the digital baseband signal (IPred/QPred) obtained from the digital predistortion unit 24 to generate the digital baseband signals (In/Qc), (Ipi/Qpi) and (42/Qp2) to ensure that, after up-conversion and RF power amplification, the magnitudes of the currents at the input of the RF Doherty combining network follow the ideal currents profile for the mode of operation of the multiple branch digital Doherty transmitter at and beyond the original design frequency of Doherty PA. Precisely, the baseband signal (ipred/Qpred) is adaptively split to compensate for the output RF power loss due to the frequency response of the output combiner for carrier 13 PCT/C2013/O007 frequencies of the baseband signal that are different from the original design frequency of the Doherty PA; and to ensure the quasi-ideal load modulation behavior at and beyond the original design frequency of the Doherty PA. [0051 f The digital signal distribution unit 24 can be implemented based on a set of finite impulse response (FIR) linear phase digital filters that are designed to ensure execution of the optimal signal separation at each frequency component of the transmit signal. [00521 The digital phase alignment unit 26 is an algorithm (according to Figure 15) that is applied to the baseband signal (Ic/Qc), (Ipi/Qpi) and (Ip2/Qp2) to generate the baseband signals (IN,e/Qc), (IN,Fn/Q[Nyt) and (1[N,p2/QrN,p2) in order to compensate in digital domain for the phase imbalance problem. 100531 Referring to Figure 2, the signal up-conversion block 28 may include first, second and third digital-to-analog converters (DACs) 30, 32, and 34, respectively, and a tri-channel up-converter 36. The DACs 30„ 34 and the tri-channel up-converter 36 may be any commercially available parts. Each DAC 30, 32, 34 is an electrical device that converts the baseband streams (IIN,e/QiN.c), (Inept/QIN,Pi) and (IiN,Pi/QiN.Pi) obtained at the output of the baseband signal processing block 20 into continuous analog signals. The tri-channel up-converter 30 is an electrical device that takes the low frequency input analog signals from the DACs 30, 32, 34 to produce the RF signals RFIN,e- (from first single-channel up-converter 38), RF[N,pi (from second single-channel up-converter 40), and RFN,p2(from third single-channel up-converter 42) that are feeding the input of the RF power amplification block 44. 100541 Referring to Figure 2, the signal up-conversion block 28 may include three digital-to-analog converters (DACs) 30, 32, 34, respectively, and first, second, and third single- 14 PCT/CA2013/000678 channel up-converters 38, 40, 42, respectively. The DACs 30, 32, 34 and the single-channel up-converter 38, 40, 42 may be any commercially available parts. Each DAC 30, 32, 34 is an electrical device that converts the baseband streams (Irw,e/QiN,c), (IrN,Pi/Qftep,)and (TEN,p1/Q1Ny) obtained at the output of the haseband signal processing block 20 into continuous analog signals. The up-converter 36 is an electrical device that takes the low frequency input analog signals from the DACs 30, 32, 34 to produce the RI' signals REN,c,RF [N,p, and RFits,u2 that are feeding the input of the RE power amplification block 44. 100551 Referring to Figure 2 and Figure 3, the RE power amplification block 44 includes the carrier amplifier 46 and two peaking amplifiers 48 and 50. The carrier amplifier 46 is an electrical device that amplifies the input radio frequency signal RFiN,c. The two peaking amplifiers 48 and 50 are electrical devices that amplify the input radio frequency signals RE[N,pi and REN,p2. The carrier amplifier 46 and peaking amplifiers 48 and 50 are implemented based on transistors and input and output matching networks. The matching networks may be implemented using passive distributed elements, transmission lines based structures or lumped elements. 100561 In one possible configuration of the multiple stage/branch Doherty amplifier, the transistor of the carrier amplifier 46 and the transistors of the peaking amplifiers 48 and 50 are identical in size. In other possible configurations of the multiple stage/branch Doherty amplifier, the transistors of the carrier amplifier 46 and the transistors of the peaking amplifiers 48 and 50 have different sizes. For a given configuration of device's size ratio between the carrier device and peaking devices, there is predefined mode of operation and ideal output fundamental current profile describing the proper operation of the multiple stage/branch Doherty amplifier.
PCT/CA2013/000678 (00571 Referring to Figure 6, the Doherty combining network 52 compromises passive structures including quarter wavelength (A14)-transmission line impedance transformers as well as k/4-transmission line impedance inverters that are arranged according to a predefined configuration depending on the mode of operation of the multiple branch Doherty transmitter. (00581 Referring to Figure 6, the general architecture of one kind of multiple branch digital Doherty transmitter, a three-stage digital Doherty transmitter, shown generally at 18 includes an input analog power divider 43 which may be physically located in signal up conversion unit 28 or an RE power amplification unit 44, one carrier amplifier 46 and two peaking amplifiers 48 and 50 and an RI' Doherty combining network 52. [00591 Referring to Figure 7, the RE Doherty combining network 52 when the identical devices are used to implement the carrier amplifier and the peaking amplifiers includes four )J4-transmission lines 54, 56 (with characteristic impedances Z0), 58 (with characteristic impedances Z0/2) and 60 (with characteristic impedances 1.73Z0). Z0 62 is the output load impedance of the three-stage Doherty amplifier. (00601 Referring to Figure 8, the ideal currents profile of a three-stage Doherty amplifier, the carrier amplifier 46 and the peaking amplifiers 48 and 50 of which are implemented using identical devices, are such that all output currents are aligned at peak power drive; and, the output current from the carrier amplifier is as twice as the output current of peaking amplifier 48 when peaking amplifier 50 turns O. [00611 Figure 9 shows an electrical diagram according to an exemplary embodiment of the present invention in which the carrier amplifier 46 and the peaking amplifiers 48 and 50 are built using identical devices. 16 PCT/CA2013 /000678 100621 Referring to Figures 18 and 19, the digital Doherty transmitter may further or alternatively include a first, second, andlor third high-directivity coupler 68, 70, 72, respectively, at the out of the carrier amplifier 46 and at the output of each of the peaking amplifiers 48 and 50. The high directivity coupler 68, 70, 72 may be built using passive coupling based structure and embedded within the output matching network of each of the amplifiers of the RF power amplification block 44. The high directivity coupler 68, 70, 72 is used to probe a sample of the output signals of amplifiers in order to: first, continuously monitor their AM1PM responses that may vary with time; and, second, update the input signals as needed.
[0063] Figure 20 shows the measured power efficiency perfbmiance of a practical implementation of an exemplary embodiment of the Present Invention operating at the nominal design frequency where the RF power amplification block has only one peaking amplifier and where only digital phase alignment is applied.
[0064] Figure 21 shows the measured power efficiency performance of the analog Doherty prior art compared to a practical implementation of an exemplary embodiment of the Present Invention (the digital Doherty transmitter of the present invention) operating at the nominal design frequency where the RE power amplification block has only one peaking amplifier and where only digital adapt power distribution was applied. [0065j Figure 22 shows the simulated power efficiency versus frequency performance of the analog Doherty prior art compared to an implementation of an exemplary embodiment of the Present invention (the digital Doherty transmitter of the present invention) where the R12 power amplification block has only one peaking amplifier and where digital adaptive power distribution and digital phase alignment was are applied.
PCT/C2013/000578 [00661 Figure 23 shows the measured performance, in terms of spectrum of a practical implementation of an exemplary embodiment of the present invention operating at the original design frequency where the RF power amplification block has only one peaking amplifier and where digital predistortion and digital adaptive power distribution are applied. 100671 As various modifications could be made to the exemplary embodiments, as described above with reference to the corresponding illustrations, without departing from the scope of the invention, it is intended that all matter contained in the foregoing description and shown in the accompanying drawings shall be interpreted as illustrative rather than limiting. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents. 18

Claims (1)

Claims 1. A multiple branch transmitter, comprising: 1. a baseband processing block for conditioning an input baseband signal; 2. a signal up-conversion block, having an input and an output, said input of said signal up-conversion block being connected to outputs of said baseband processing block, said signal up-conversion block being adapted to generate analog RF signals based on sub-signals obtained from the baseband processing block; 3. an RF power amplification block having an input and an output, said input of said RF power amplification block being connected to said output of said signal up-conversion block, said RF power amplification block to amplify the analog RF signals present at its inputs; 4. an RF combining network having an input connected to said output of said RF power amplification block, and an output that combines the amplified analog RF signals obtained from the RF power amplification block, and wherein the baseband processing block continuously monitors a power envelope of the input signal, and based on the instantaneously monitored power envelope dynamically varying a signal splitting ratio to split the input signal between a plurality of baseband output signals, 2. The multiple branch transmitter of claim 1, wherein said baseband processing block comprises a digital predistortion unit, a digital adaptive signal distribution unit, and a digital phase alignment unit. 3. The multiple branch transmitter of claim 1, wherein said signal-up conversion block comprises digital-to-analog converters (DACs), and one of either a single up-converter and a multi-channel up-converter. 4. The multiple branch transmitter of claim 1, wherein said RF power amplification block comprises a carrier amplifier having an input and an output, at least one peaking amplifier -1 of 8- having an input and an output„ said carrier amplifier and said at least one peaking amplifier being one of identical and different in size and power handling. 5. The multiple branch transmitter of claim 1, further comprising a plurality of high-directivity couplers connected to said output of said carrier amplifier and to said output of said peaking amplifiers. 6. The multiple branch transmitter of claim 1, wherein said RF combining network comprises transmission line based impedance transformers and matching networks, disposed according to a predefined configuration depending on one or more of center frequency, type of analog RF input signal, a mode of operation of said RF power amplification block, and output currents profiles of a carrier amplifier and peaking amplifiers. 7. The multiple branch transmitter of claim 1, wherein said RF combining network output is in communication with said input of said baseband processing block. 8. The multiple branch transmitter of claim 1, wherein linearization of said multiple-branch transmitter is accomplished by using digital predistortion (DPD). 9. The multiple branch transmitter of claim 1, wherein frequency bandwidth extension beyond the nominal frequency band of said multiple branch transmitter is accomplished by using the baseband processing block implemented for digital conditioning of the digital input baseband signal and for generating digital baseband signals. 10. The multiple branch transmitter of claim 1, wherein said RF power amplification block comprises a carrier amplifier having an input and an output, and a peaking amplifier having an input and an output, said carrier amplifier and said peaking amplifier being one of identical and different in size and power handling. 11. The multiple branch transmitter of claim 1, wherein the analog RF signal is contiguous in one-band. -2 of 8- 12. The multiple branch transmitter of claim 1, wherein the signal splitting ratio uses a target performance profile for each of the multiple branches of the multiple branch transmitter. 13. The multiple branch transmitter of claim 1, wherein the signal splitting ratio determines one or both of the power and phase distribution between the baseband output signals. 14. The multiple branch transmitter of claim 1, wherein the signal splitting ratio adaptively distributes power available in the input signal between input branches of the power amplification block according to a power distribution scheme that is derived to ensure a quasi-ideal load modulation behavior at a design frequency of the power amplification block. 15. The multiple branch transmitter of claim 12, wherein the target performance profile is based on current and load performance of each branch of the power amplifier block. 16. The multiple branch transmitter of claim 12, wherein the target performance profile is based on power efficiency of each branch of the power amplifier block. 17. The multiple branch transmitter of claim 12, wherein the target performance profile is based on a frequency bandwidth of each branch of the power amplifier block. 18. The multiple branch transmitter of claim 12, wherein the target performance profile is based on a load modulation of each branch of the power amplifier block. 19. A multiple branch transmitter, comprising: a baseband processing block for conditioning an input baseband signal; a signal up-conversion block, having an input and an output, said input of said signal up-conversion block being connected to outputs of said baseband processing block, said -3 of 8- signal up-conversion block being adapted to generate analog RF signals based on the sub-signals obtained from the baseband processing block; an RF power amplification block having an input and an output, said input of said RF power amplification block being connected to said output of said signal up-conversion block, said RF power amplification block to amplify the analog RF signals present at its inputs; and an RF combining network having an input connected to said output of said RF power amplification block, and an output that combines the amplified analog RF signals obtained from the RF power amplification block, wherein a frequency bandwidth extension beyond the nominal frequency bands of said multiple-branch transmitter is accomplished by using the baseband processing block implemented for digital conditioning of the digital input baseband signal and for generating a plurality of digital baseband signals. 20. The multiple branch transmitter of claim 1, wherein the analog RF signal is noncontiguous over multiple bands. -4 of8- PCT/CA2013/000678 1/23 8L9000/ETOZYD/1Da RF POWER AMPLIFICATION 44 BLOCK 26 .24 BASEBAND PROCESSING BLOCK 'FRED QPRED tr,1 IP1 rip '4" I-4'11 17:2 QP2 28 IIN,C / QIN,ct .Ir N,P irti,,P1 CARRIER AMPLIFIER RFIN,c N. J 6 PEAKING AMPLIFIER 1 48 52 RF DOHERTY ,OMBINATION G BLOCK 1 36 SIGNAL UP-CONVERSION BLOCK lc /t
1. IP PEAKIV outnt ANTLIFIER21 RFoULP 1;
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