SE1400603A2 - Multilevel converter - Google Patents

Abstract

It is presented a multilevel converter for transferring power between a high voltage AC connection and a high voltage DC. The multilevel converter comprises: at least one phase leg each comprising an upper converter arm, and a lower converter arm, connected serially between the positive DC pole and the negative DC pole. Each one of the upper converter arm and the lower converter arm comprises a sequential connection of a first outer section, at least one centre section and a second outer section. Each outer section comprises two switching devices and an energy storage element; and each centre section comprises five switching devices, two energy storage elements and two diodes. The energy storage elements of the at least one centre section are arranged to have, during operation, a reverse polarity in relation to the energy storage elements of the first outer section and the second outer section.(FigA)

Description

25 SUMMARY It is an object to provide an improved structure for a multilevel converter, providing DC side fault blocking capability with a low number of switching devices.

This is solved by an invention according to the appended independent claims.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical ñeld, unless explicitly de fi ned otherwise herein. All references to "a / an / the element, apparatus, component, means, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is now described, by way of example, with reference to the accompanying drawings, in which: Figs 1A-B are schematic diagrams of embodiments of multilevel converters for converting power between DC and AC; Figs 2A-B are schematic diagrams illustrating embodiments of the converter arms 3a-b of the phase legs of the power converter of Figs 1A-B; Figs 3A-I are schematic diagrams of embodiments of the converter arms of the phase leg of the power converter of Figs 1A-B; Fig. 4 is a schematic diagram illustrating a converter arm comprising two center sections; and Fig. 5 is a current chart illustrating an embodiment of a method for controlling the multilevel converter of Figs. 1A-B. 10 15 20 25 30 DETAILED DESCRIPTION The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout the description.

Fig. 1A is a schematic diagram of a multilevel converter 1 for converting power between DC and AC. The multilevel converter 1 converts power in either direction between a high voltage DC connection 81 and a high voltage AC connection 80. The DC connection 81 comprises a positive pole DC * and a negative pole DC: The AC connection 80 comprises a phase terminal AC. A ground terminal may also be provided (not shown). Power can fl ow from DC to AC or vice versa.

Regarding voltage on the DC connection 81, positive and negative are here to be interpreted as mutually relative terms and not absolute. In other words, the positive connection DC * of the DC connection 81 has a higher voltage than the negative pole DC- of the DC connection 81. Hence, for example, the positive pole or the negative pole could be at ground potential, or even both poles DC +, DC- can be greater than ground potential, as long as DC * has a higher voltage than DC- during normal operation.

A phase leg 4 comprises a first converter arm 3a, a first reactor 2a, a second reactor 2b and a second converter arm 3b, connected serially between the positive poles DC * and the negative pole DC 'of the DC connection 81. While the reactors 2a-b are shown here as being provided on the inner side of the converter arms 3a-b, the reactors could alternatively or additionally be provided between the converter arms 3a-b and the respective DC poles DC +, DC 'of the DC connection 81 .The reactors 2a-b act as filters to provide a 10 15 20 25 30 suf fi ciently sinusoidal (or square, saw tooth shaped, etc.) waveform on the AC connection 80.

The AC connection 80 is provided between the first converter arm 3a and the second converter arm 3b, optionally via a transformer 75.

DC side capacitors 12a, 12b are optionally arranged between the positive and negative DC poles, DC * and DC- to allow an AC current to circulate with minimal effect on the DC poles DC +, DC: The two DC side capacitors can optionally be combined in a single capacitor or be implemented using more capacitors connected serially and / or in parallel. Optionally, when a multiphase power converter 1 such as the one shown in F ig 1B is used, the DC side capacitors 12 can be omitted, since an AC current can circulate between the DC sides of the phase legs for the various phases.

Being a multilevel converter, each one of the converter arms 3a-b can generate a plurality of different voltage levels, as controlled by a controller 10.

This is described in more detail below with reference to Figs 3A-I. By providing multilevel conversion, the switching frequency for each switch can be smaller, leading to reduced losses. Moreover, the multiple levels can generate a wave shape closer to a desired wave shape (e.g. sinusoidal) on the AC side, thus reducing the requirements on the reactors 2a-b.

The controller 10 controls the operation of the converter arms 3a-b. The controller 10 can be a single controller or divided into a central controller and local controllers for each converter arm 3a-b. While the controller 10 is shown here provided externally from the phase leg 4, part or all of the controller 10 may also be provided as part of the phase leg 4.

Fig. 1B is a schematic diagram of a three phase multilevel converter 1 for converting power between DC and AC. The three phase power converter 1 here comprises three phase leg 4a-c. In this way, the AC connection comprises three phase terminals ACA, ACB and ACc to be able to provide a three phase connection, e.g. to an AC grid, an AC power source or an AC power load. Optionally, an AC ground terminal is also provided (not shown). 10 15 20 25 30 A corresponding multiphase converter can be achieved for other than three phases by connecting the same number of phase legs as there are phases. In this way, multiphase converters for any suitable number of phases, such as two, four, fi ve, six, etc., phases can be provided.

Total semiconductor loss is dependent on both switching loss and conduction loss, where normally the conduction loss is the dominant loss component in multilevel converters. Conduction loss is reduced when the number of switching devices in the current path are reduced.

The multilevel converters 1 of Figs 1A-B are used for conversion of power for high voltage applications, such as between an AC grid and an HV DC link (or HVDC grid). In one embodiment, high voltage is de fi ned as voltages more than 35 kV.

Figs 2A-B are schematic diagrams illustrating a schematic diagram of embodiments of the converter arms 3a-b of the phase leg of the power converter 1 of Figs 1A-B. The converter arms 3a-b are here represented by a single converter arm 3. The converter arms of Figs 2A-B are known in the art per se.

In Fig. 2A, there are four full-bridge cells 70a-d. Each full-bridge cell comprises four switching elements T1-T4 and an energy storage element C with a voltage U. In this way, each full-bridge cell can contribute with a voltage of U, 0 or -U. The whole converter arm 3 can then be controlled to contribute with any voltage between -4U and + 4U, in increments of U. Each full-bridge cell 70a-d has two switching devices in the electrical path at any one time. With four full-bridge cells, the total number of switching devices in the electrical path is thus eight. In total, there are here sixteen switching devices in the converter arm 3.

Due to the reversibility of the voltage contributions, a fault on the DC side can be handled and isolated on the DC side by proper control of the full-bridge cells. In this way, the AC side can remain connected with no or minimal protective measures. However, each full-bridge cell requires, apart from the 10 15 20 25 30 energy storage element C, four switching devices T1-4. This results in a large component count in terms of switching devices (semiconductors), and also conductive losses.

In Fig. 2B, there are two full-bridge cells 70a-b and two half-bridge cells 71a- b. Each half-bridge cell comprises two switching elements T1-T2 and an energy storage element C with a voltage U. In this way , each half-bridge cell can contribute with a voltage of U or o. The whole converter arm 3 can then be controlled contribute with any voltage between -2U and + 4U, in increments of U. There are twelve switching devices of this converter arm , a reduction from sixteen switching devices of the all full-bridge converter arm of Fig 2A. Each half-bridge cell has one switching device in the electrical path at any one time. With two full-bridge cells and two half-bridge cells, the total number of switching devices in the electrical path is here six, a reduction from eight of the all full-bridge converter arm 3 of Fig 2A.

Hence, compared to the converter arm of Fig 2A, the mixing of half-bridge and full-bridge cells reduces costs for switching devices, as well as the number of switching devices in the electrical path. With 50% full-bridge and 50% half-bridge cells, DC-side faults can still be cleared without requiring breakers on the AC side to open, while the component count is reduced.

However, when it comes to the DC fault blocking capability, it is important to consider both voltage counter and excessive energy during the fault to de fi ne the rating of 4-quadrant cells in the converter arm. A suf fi cient voltage (50% FB cell) needs to be generated by the 4-quadrant cells to block the AC voltage feeding. However, the 4-quadrant cell rating is mainly de fi ned based on the excessive energy caused mainly by the time delay of the protection system (for example 3ms).

When only full-bridge cells are used, the full-bridge cells provide an electrical path through the energy storage elements by natural commutation between adjacent cells. When half-bridge cells are used, the energy storage elements of the half-bridge cells are bypassed through the diode. Thus, during a DC fault, excessive energy is stored in the cables due to the protection delay and 10 15 20 25 30 has to discharge into the full-bridge cells, which causes an overvoltage (only) on the full-bridge cells. Excessive energy causes an over voltage rating on full-bridge cells of about 35% in each converter arm.

Figs 3A-I are schematic diagrams of embodiments of the converter arms 3a-b of the phase leg of the power converter 1 of Figs 1A-B. The converter arms 3a- b are here represented by a single converter arm 3. Figs 3A-I relate to different control states of the converter arm 3. In the embodiment shown in Figs 3A-I, there is only one center section 11, but more may be provided, eg as shown in Fig. 4.

The structure of the converter arm 3 shown in all of Figs 3A-I is identical and will now be described. The converter arm 3 comprises a sequential connection of a first outer section 1oa, a center section 11 and a second outer section 1ob. The positive side of the converter arm 3 is here de fi ned as up in Figs 3A-I and the negative side is down.

The center section 11 comprises a first switching device S1, a second switching device S2, a third switching device S3, a fourth switching device S4, and a fifth switching device S5. Moreover, the center section comprises a first energy storage element C1, a second energy storage element C2, a first diode D1, and a second diode D2.

The first outer section 1oa comprises a sixth switching device S6, a seventh switching device S7 and a third energy storage element C3. Analogously, the second outer section 1ob comprises an eighth switching device S8, a ninth switching device S9 and a fourth energy storage element C4.

The polarity of each energy storage element, during operation, is shown.

Hence, the positive side of the third energy storage element C3 is to the right, to a point between the seventh switching element S7 and the third switching element S3. The positive side of the first energy storage element C1 is to the left, to a point between the first switching element S1 and the first diode D1.

The positive side of the second energy storage element C2 is also to the left, to a point between the fi fth switching element S5 and the second switching 10 15 20 25 30 element S2. Finally, the positive side of the fourth energy storage element C4 is to the right again, to a point between the fourth switching element S4 and the eighth switching element S8.

In this way, the energy storage elements C1, C2 of the center section 11 are arranged to have, during operation, a reverse polarity in relation to the third energy storage element C3 of the outer rst outer section 10a and the fourth energy storage element C4 of the second outer section 10b.

In each one of the first outer section 10a and the second outer section 1ob, a respective connection terminal 5a, 5b of the converter arm 3 is provided between the two switching devices S6, S7; S8, S9. Moreover, the energy storage element C3; C4 is provided in parallel with a serial connection of the two switching devices S6, S7; S8, S9 of the respective outer sections 10a-b. A connection to the center section 11 is provided using connections on either side of the respective energy storage element C3; C4.

Another way to present the center section 11 is that it comprises a first string and a second string. The first string comprises the first switching device S1, the first diode D1 and the second switching device S2. The second string comprising the third switching device S3, the second diode D2 and the fourth switching device S4. The center section 11 further comprising the first energy storage element C1 provided between inner sides of the first switching device S1 and the third switching device S3, the second energy storage element C2 provided between inner sides of the second switching device S2 and the fourth switching device. S4, and the ñfth switching device S5 provided between a fi rst point and a second point, the fi rst point being between the fi rst diode D1 and the second switching device S2 and the second point being provided between the second diode D2 and the third switching device S3 .

Each mentioned switching device S1-S9 comprises a switching element and an antiparallel diode. Each switching device S1-S9 can be implemented using any suitable switch which can be controlled to be either to be in a conducting state or a blocking state. For example, each switch can be implemented using 10 15 20 25 30 insulated gate bipolar transistors (IGBT), Integrated Gate-Commutated Thyristors (IGCT), a Gate Turn-Off thyristors (GTO), power Metal-Oxide- Semiconductor Field-Effect -Transistor (MOSFET), power Bipolar Junction Transistor (BJT), Bi-mode Insulated Gate Transistor (BIGT) or any other suitable high power semiconductor component. Each one of the energy storage elements C1-4 can be of any suitable type, such as a capacitor, a supercapacitor, an inductor, a battery, etc. The voltage across each energy storage element is here denoted U, which voltage is controlled by the controller during operation.

The blocking voltage of the first switching device S1, the second switching device S2, the third switching device S3 and the fourth switching device S4 is 2U. The blocking voltage of the fi fth switching device S5, the sixth switching device S6, the seventh switching device S7, the eighth switching device S8 and the ninth switching device S9 is U. The first and second diodes D1, D2 are rated to withstand half of the current larm through the converter arm 3.

It is to be noted that the outer rst outer section 10a, the center section 11 and the second outer sections 10b, as well as the fi rst and second strings are only ways of describing the components of the converter arm 3. Speci fi cally, there does not need to be separate physical modules corresponding to the outer rst outer section 10a, the center section 11, the second outer sections 10b, the fi rst and second strings, even if that may be the case.

The converter arm 3 is controlled by a controller, such as controller 10 or Fig 1A. The controller is arranged to control the switching devices S1-9 to obtain a desired voltage Vom across the converter arm 3 by controlling an electrical path through the converter arm 3 via a suitable number of energy storage elements, as illustrated by Table 1 and Figs 3A -IN. The current through the v, with a resulting electrical path. It is to be noted that the illustrated switching scheme is only an example and the same output can be achieved using a slightly different switching scheme. Forward path through an energy storage element C1-C4 here denotes a path through the energy storage element C1-C4 from the positive side to the negative side, resulting in a positive voltage 10 15 20 25 30 10 contribution. Analogously, reverse path through an energy storage element C1-C4 here denotes a path through the energy storage element C1-C4 from the negative side to the positive side, resulting in a negative voltage contribution. In order not to clutter the drawings unnecessarily, in Figs 3A-I, only the positive side of the energy storage elements C1-C4 is indicated with a plus (+) sign, while the negative side is the side without the plus sign.

In Fig. 3A, the first switching device S1, the fourth switching device S4, the fourth switching device S5, the seventh switching device S7, and the ninth switching device S9 are all in a conductive state. All other switching devices are in a blocking state. The resulting electrical path for the current Iam is illustrated in the fi gure. In this state, the electrical path leads to a forward path through the first energy storage element C1, the second energy storage element C2, the third energy storage element C3 and the fourth energy storage element C4. In this way, the voltage Vom across the converter arm is here + 4U.

In Fig. 3B, the first switching device S1, the fourth switching device S4, the first switching device S5, the seventh switching device S7, and the eighth switching device S8 are all in a conductive state. All other switching devices are in a blocking state. The resulting electrical path for the current alarm is illustrated in the fi gure. In this state, the electrical path leads to a forward path through the first energy storage element C1, the second energy storage element C2 and the third energy storage element C3. In this way, the voltage Vom across the converter arm is here + 3U.

In Fig. 3C, the first switching device S1, the second switching device S2, the fi fth switching device S5, the seventh switching device S7, and the ninth switching device S9 are all in a conductive state. All other switching devices are in a blocking state. The resulting electrical path for the current alarm is illustrated in the fi gure. In this state, the electrical path leads to a forward path through the first energy storage element C1 and the third energy storage element C3. In this way, the voltage Voot across the converter arm is here + 2U. 10 15 20 25 11 In F ig 3D, the fi rst switching device S1, the second svvitching device S2, the fi fth switching device S5, the sixth switching device S6, and the ninth switching device S9 are all in a conductive state. All other switching devices are in a blocking state. The resulting electrical path for the current alarm is illustrated in the fi gure. In this state, the electrical path leads to a forward path through the first energy storage element C1. In this way, the voltage Vau: across the converter arm is here + 1U.

In Fig 3E, the second switching device S2, the third switching device S3, the fi fth switching device S5, the seventh switching device S7, and the ninth switching device S9 are all in a conductive state. All other switching devices are in a blocking state. The resulting electrical path for the current Iam is illustrated in the figure. In this state, the electrical path does not pass through any energy storage elements. In this way, the voltage Vau: across the converter arm is here (essentially) o.

In Fig 3F, the second switching device S2, the third switching device S3, the fi fth svvitching device S5, the sixth switching device S6, and the ninth switching device S9 are all in a conductive state. All other switching devices are in a blocking state. The resulting electrical path for the current Iam is illustrated in the fi gure. In this state, the electrical path leads to a reverse path through the third energy storage element C3. In this way, the voltage Vau: across the converter arm is here -1U.

In Fig 3G, the second switching device S2, the third switching device S3, the fi fth switching device S5, the sixth switching device S6, and the eighth switching device S8 are all in a conductive state. All other switching devices are in a blocking state. The resulting electrical path for the current Iaam is illustrated in the fi gure. In this state, the electrical path leads to a reverse path through the third energy storage element C3 and the fourth energy storage element C4. In this way, the voltage Vau: across the converter arm is here -2U. 10 15 20 25 12 In F ig 3H, all switching devices are in a blocking state, e.g. for a fault condition or for energization of the energy storage elements. The resulting electrical path for the current Iam, when Iam is positive, is illustrated in the fi gure. In this state, the electrical path passes through the diodes of the fi rst switching device S1, the fourth switching device S4, the fi fth switching device S5, the seventh switching device S7 and the ninth switching device S9. This will energize the energy storage elements C1-C4.

In Fig. 31, all switching devices are in a blocking state, e.g. for a fault condition. The resulting electrical path for the current larm, when Iam is negative, is illustrated in the fi gure. In this state, the electrical path passes through the diodes of the second switching device S2, the third switching device S3, the fi fth switching device S5, the sixth switching device S6 and the eighth switching device S8. Also here, this will energize the energy storage elements C1-C4.

Using the structure of the converter arm illustrated in Figs 3A-I, a six-level bipolar four-quadrant voltage and current cell structure is provided (4 four positive voltage levels and two negative voltage levels).

Moreover, the controller is arranged to control all mentioned switching devices when a fault condition is detected on a DC side to absorb the DC fault within the converter arms.

DC faults can be blocked within the converter arm by providing a reverse voltage. In blocking mode, all energy storage elements are inserted in the electrical path to absorb the excessive energy and reduce or even eliminate the need for converter overrating.

Start-up energization of the converter arm is possible by blocking all devices, as illustrated in Figs 3H-I. Also, the provided structure provides an ability to operate in a boosting mode (reduced DC voltage).

Compared to the mixed-cell structure of Fig. 2B, the structure of Figs. 3A-I is more effective for the same number of voltage levels (-2U to + 4U). 10 15 20 25 13 Specifically, only nine switching device required, compared to the twelve switching devices of the mixed-cells structure. Moreover, there are only switchve switching device in the conduction path, compared to six in the mixed-cell structure, leading to a conduction loss saving of approximately 15%. Also, three fewer gate drive circuits are required due to the reduction in the number of switching devices.

Fig. 4 is a schematic diagram illustrating a converter arm 3 comprising two center sections 11a-b, connected via an intermediate energy storage element C5. In this way, even more voltage levels for the converter arm 3 are possible.

Using this structure, the ratio of number of voltage levels to number of devices is improved further, compared to the structure shown in Figs 3A-I with only one center section.

Specifically, in this embodiment there are fourteen switching devices for seven energy storage elements. This gives a ratio of 14/7 = 2 switching devices per energy storage element. In the embodiment with one center section, there is a ratio of 9/4, approximately 2.66, of switching devices per energy storage element. This can be compared also to the mixed cell structure of Fig 2B, where there are twelve switching devices for four storage elements, i.e. 12/4 = 3 switching devices per energy storage element.

Fig. 5 is an owl chart illustrating an embodiment of a method for controlling the multilevel converter of Figs. 1A-B.

In a control step 30, the switching devices are controlled to obtain a desired voltage across each converter arm. This is achieved by controlling an electrical path through each converter arm via a suitable number of energy storage elements, e.g. as illustrated in Table 1 and Figs 3A-I, described above.

In a conditional fault step 32, it is determined whether a fault condition is detected on the DC side of the multilevel converter. If a fault is detected, the method proceeds to a block step 34. Otherwise, the method returns to the control step 30. 10 15 14 In the handle fault step 34, the fault is handled by controlling the switching devices to absorb the DC fault within the converter arms.

In Fig. 6, an alternative embodiment without boosting operation is shown.

Here, a cell structure is provided which keeps the same structure as the mixed cell solution but where the bottom of the half-bridge cell capacitor is connected to the ac side of the full-bridge cell through a diode. The blocking voltages of the different devices are indicated in as U or 2U, respectively.

Diodes (D13 and D17) are rated to withstand the half converter arm current.

The operation of the arm of Fig. 6 is illustrated in Figs. 7A-C. Table 2 shows one example of possible switching states.

Capacitor S1 S2 S4 S5 S6 Vom Iam. bypass 1 o 1 o 1 o C1, C2 o 1 o 1 1 o -U C1 <0 or> oo 1 1 0 1 -U C2 <0 or> o 0 1 1 1 1 -2U none <0 or> 0 o 0 0 0 0 Energize> o 0 0 0 0 0 Energize <0 Table 2: sample switching scheme for embodiments of Figs 7A-C The cell shown in Fig 6 operates as two normal half-bridge cells during normal operation. When a fault occurs, it can operate as a clamped double cell to utilize all capacitors and block the fault current without over rating.

Due to the diodes, no boosting operation is needed. Moreover, start-up energization of the cell is possible by blocking all devices. 10 15 15 In Fig. 8, an alternative embodiment with boosting operation is shown. The structure is similar to the embodiment of Fig 7, but here the diodes are replaced by controllable elements.

In order to address the boosting operation during the normal operation and reactive power support during the fault, the embodiment of Fig. 8 operates as a full-bridge (4-quadrant cell). Therefore, the cell of Fig 8 has been modified compared to the cell of Fig 6 to achieve reverse voltage during the normal operation. As shown, D3 has been exchanged with S3, a controllable switch, and D7 has been replaced by a thyristor T1, to avoid paralleling during normal operation and thus an inrush current.

The operation of this arm of Fig. 8 is illustrated in Figs. 9A-C. Table 3 shows one example of possible switching states.

Capacitor S1 S2 S3 S4 S5 S6 T1 Vom Iam. bypass 1 oo 1 o 1 oo C1, C2 o 1 oo 1 1 oo -U C1 oo 1 o 1 o 1 o -U C2 oo 1 o 1 1 1 o -2U none o 1 o 1 oo 1 o + U C1 oooooooo Energize> oooooooo Energize Table 3: sample switching scheme for embodiments of Figs 9A-C The cell of Fig 8 operates as two normal half-bridge and full-bridge (mixed) cells during the normal operation. During fault, the cell operates as clamped double cell to utilize all capacitors and block the fault current without over 10 15 16 rating. Moreover this cell supports boosting operation (reduced dc voltage or reactive power support during the dc fault). Also here, start-up energization of the cell is possible by blocking all devices.

Figs. 10A-C are illustrations of an alternative embodiment with a thyristor bypass for AC fault. In order to deal with the AC converter bus fault (single-phase to ground), the full-bridge cell part of the proposed cell should be either bypassed or recon- gured as a half-bridge to clamped the phase voltage in healthy phases. In Fig. 10B, the second thyristor T2 conducts; thereby bypassing all active elements of the cell.

Figs. 11A-D illustrate even more alternative embodiments of converter arm cells.

The invention has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the invention, as de fi ned by the appended patent claims.

Claims (10)

10 20 25 30 17 CLAIMS 1. A multilevel converter (1) for transferring power between a high voltage AC connection (AC) and a high voltage DC connection (81) compiising a positive DC pole (DCt) and a negative DC pole (DC-), the multilevel converter (1) coinprising: at least one phase leg (4, 4a-c) each comprising an upper converter arm (3a), and a lower converter arm (gb), connected serially between the positive DC pole (DC +) and the negative DC pole, wherein a terminal of the AC connection is provided between the upper converter arm (3a) and the lower converter arm (3h); wherein each one of the upper converter arm (3a) and the lower converter arm (3b) comprises a sequential connection of a on rst onter section (ma), at least one center section (11, 11a-h) and a second onter section ( 10b), wherein each one of the outer rst outer section (ma) and the second onter section (mb) comprises two switching devices (S6, S7; S8, S9) and an energy storage element (G3, C4); where each one of the at least one center section (11, na-b) comprises fi ve switching devices (S1, S2, S3, S4, S5), two energy storage elements (C1, C2) and two diodes (D1, D2) ; and wherein the energy storage elements (Ci, C2) of the at least one center section (11, 11a-b) are arranged to have, during operation, a reverse polarity in relation to the energy storage elements (C3, C4) of the first outer section and the second outer section. 2. The multilevel converter (1) according to claim 1, wherein, in each one of the outer rst outer section (ma) and the second outer section (1ob), a connection terminal (5a; 5b) is provided between the two switching devices (S6, S7; S8, 89); and wherein the energy storage element (C3; C4) is provided in parallel with a serial conneaion of the two switching devices (S6, S7; S8, S9); and a connection to the at least center section is provided using connections on either side of the energy storage element (C3; C4). 10 15 20 18 3. The multilevel converter (1) according to any one of the preceding claims, whercin each one of the at least one center section (11, 11a-b) comprises a fi rst string and a second string, the fi rst string comprising a first switching device (S1), a diode (D1) and a second switching device (S2), the second string cornprising a third switching device (S3), a second diode (D2) and a fourth switching device (S4), the center section further comprising a first energy storage element (C1) provided between inner sides of the first switching device (S1) and the third switching device (S3), a second energy storage element (C2) provided between inner sides of the second switching device (S2) and the fourth switching device (S4), and a ñfth switching device (S5) provided between a fi rst point and a second point, the first point being between the first diode (Di) and the second switching device (S2) and the second point being provided between the second diode (De) and the third switching device (S3). 4. The multilevel converter (1) according to any one of the prcceding claims, further comprising a controller (10) arrangcd to control the switching devices to obtain a desired voltage across each converter arm (3a, 3b) by controlling an electrical path through each converter arm (3a, 3b) via a suitable number of energy storage elements. The multilevel converter (1) according to claim 4, wherein the controller (10) is arranged to control all mentioned switching devices when a fault condition is detected on a DC side to absorb the DC fault within the converter arms. 6. The rnultilevel converter (1) according to any one of the preceding claims, wherein each mentioned switching device compfßes a switching element and an antiparallel diode. 7. The multilevel converter (1) according to any one of the preceding claims, wherein each one of the upper converter arm (3a) and the lower converter arm (3b) compiises only one center section (11). 10 20 25 30 19 8. 'fhe multilevel converter (1) according to any one of the preceding claims, wherein each one of the upper converter arm (3a) and the lower converter arm (3b) comprises at least two center sections (na-b), wherein an intermediate energy storage element (C5) is provided across the connection between two adjacent center sections (na-b). 9. A method for controlling a multilevel converter (1) for transferring power between a high voltage AC connection (80) and a high voltage DC connection (81) comprising a positive DC pole (DC +) and a negative DC pole (DG), the multilevel converter (1) comprising: a controller (10), at least one phase leg (4a-c) each comprising an upper converter arm (3a), and a lower converter arm (3b), connected serially between the positive DC pole (DC +) and the negative DC pole, where a terminal of the AC connection is provided between the upper converter arm (3a) and the lower converter arm (3b); wherein each one of the upper converter arm (3a) and the lower converter arm (3b) comprises a sequential connection of a first outer section (roa), at least one center section (11, 11a-b) and a second outer section ( iob), wherein each one of the outer rst outer section (roa) and the second outer section (1ob) comprises two switching devices (S6, S7; S8, S9) and an energy storage element (C3; 04); where each one of the at least one center section (11, na- b) comprises switch ve switching devices (S1, S2, S3, S4, S5), two energy storage elements (G1, G2) and two diodes (D1, D2) ; and wherein the energy storage elements (C1, C2) of the at least one center section (11, 11a-b) are arranged to have, during operation, a reverse polarity in relation to the energy storage elements (C3, C4) of the ñrst outer section and the second outer section, the method being performed in the multilevel converter (1) and cornprising the step of: controlling (30) the switching devices to obtain a desired voltage across each converter arm (3a, 3b) by controlling an electrical path through each converter arm (3a, 3b) via a suitable number of energy storage elements. 10. The method according to claim 7, further comprising the steps of: detecting (32) a fault condition is detected on a DC side of the multilevel converter; and 20 handling (34) the fault by oontrclling the svvitching devices to abscrb the DC fault within the converter arms.