RU95100522A - Multicomputer system synchronizing device
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Multicomputer system synchronizing device
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Publication number
RU95100522A
RU95100522ARU95100522/09ARU95100522ARU95100522ARU 95100522 ARU95100522 ARU 95100522ARU 95100522/09 ARU95100522/09 ARU 95100522/09ARU 95100522 ARU95100522 ARU 95100522ARU 95100522 ARU95100522 ARU 95100522A
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Application filed by Войсковая Часть 25840filedCriticalВойсковая Часть 25840
Priority to RU95100522/09ApriorityCriticalpatent/RU95100522A/en
Publication of RU95100522ApublicationCriticalpatent/RU95100522A/en
FIELD: computer engineering; computer-aided control systems affording synchronous real-time operation of several machines of multicomputer systems. SUBSTANCE: device is provided with second delay element, second AND gate, and D flip-flop; output of first OR gate is connected to R input of D flip-flop and to input of second pulse delay element whose output is connected to clock input of D flip-flop and to first input of second AND gate whose output is connected to second input of second OR gate; D flip-flop output is connected to second inputs of AND gate. EFFECT: simplified design of device due to improved analysis of sync pulse master oscillator failure.
Claims (1)
Изобретение относится к вычислительной технике и может быть использовано в автоматизированных системах управления для обеспечения синхронизации работы нескольких ЭВМ многомашинных комплексов в едином реальном масштабе времени. Цепь изобретения - упрощение устройства за счет усовершенствованного анализа выхода из строя задающего генератора синхроимпульсов. Это достигается тем, что в устройство введены второй элемент задержки импульсов, второй элемент И и D-триггер, причем выход первого элемента ИЛИ соединен с И-входом D-триггера и входом второго элемента задержки импульсов, выход которого соединен с тактовым входом D-триггера и первым входом второго элемента И, выход которого соединен с вторым входом второго элемента ИЛИ, выход D-триггера соединен с вторыми входами элементов И.The invention relates to computer technology and can be used in automated control systems to ensure synchronization of the operation of several computers of multi-machine complexes in a single real time scale. The chain of the invention is the simplification of the device due to the improved analysis of the failure of the master clock generator. This is achieved by introducing a second pulse delay element, a second AND element and a D-trigger into the device, the output of the first OR element being connected to the I-input of the D-trigger and the input of the second pulse delay element, the output of which is connected to the clock input of the D-trigger and the first input of the second AND element, the output of which is connected to the second input of the second OR element, the output of the D-trigger is connected to the second inputs of the And elements.
RU95100522/09A1995-01-111995-01-11Multicomputer system synchronizing device
RU95100522A
(en)