RU94030318A - Device for testing digital integral circuits - Google Patents

Device for testing digital integral circuits

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Publication number
RU94030318A
RU94030318A RU94030318/07A RU94030318A RU94030318A RU 94030318 A RU94030318 A RU 94030318A RU 94030318/07 A RU94030318/07 A RU 94030318/07A RU 94030318 A RU94030318 A RU 94030318A RU 94030318 A RU94030318 A RU 94030318A
Authority
RU
Russia
Prior art keywords
input
output
gate
synchronization
bit
Prior art date
Application number
RU94030318/07A
Other languages
Russian (ru)
Inventor
Ю.И. Шустов
Original Assignee
Российский научно-исследовательский институт космического приборостроения
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Российский научно-исследовательский институт космического приборостроения filed Critical Российский научно-исследовательский институт космического приборостроения
Priority to RU94030318/07A priority Critical patent/RU94030318A/en
Publication of RU94030318A publication Critical patent/RU94030318A/en

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  • Tests Of Electronic Circuits (AREA)

Abstract

FIELD: automation and computer engineering, electronic industry, instruments making. SUBSTANCE: device has N-bit generator of test sequence on input signals for tested object, N-channel signature analyzer and synchronization unit. N D-flip-flops, N XOR gates, N inverse AND gate circuits and N resistors are introduced to accomplish the goal of invention. Output of each bit of generator of test sequence is connected to data input of D-flip-flop and to first input of XOR gate. Output of D-flip-flop is connected to second input of XOR gate and to input of tested object through resistor. Output of XOR gate is connected to first input of AND gate. Second input of AND gate for first bit of generator is connected to synchronization input of D-flip-flop and output of clock synchronization pulses of synchronization unit. while second input of AND gate of each subsequent bit of generator of test sequence is connected to synchronization input of D-flip-flop of corresponding bit and to output of AND gate of previous bit. Output of AND gate of last bit of generator of test sequence is connected to synchronization input of generator of test sequence. EFFECT: increased functional capabilities, increased field of application, practical elimination of expenses on development of programs which tests separate types of microcircuits.

Claims (1)

Результатом осуществления заявляемого изобретения является получение универсального средства контроля широкого круга цифровых ИМС, при использовании которого практически полностью отсутствуют затраты на разработку программ контроля отдельных типов микросхем. Указанный результат достигается благодаря тому, что в устройство, содержащее N-разрядный формирователь тестовой последовательности входных сигналов объекта контроля, N-канальный сигнатурный анализатор и устройство синхронизации, введены N D-триггеров, N схем ИСКЛЮЧАЮЩЕЕ ИЛИ, N схем И с инверсной логикой и N резисторов, выход каждого разряда формирователя тестовой последовательности соединен с входом данных D-триггера и первым входом схемы ИСКЛЮЧАЮЩЕЕ ИЛИ, выход D-триггера соединен с вторым входом схемы ИСКЛЮЧАЮЩЕЕ ИЛИ и через резистор с входом объекта контроля, выход схемы ИСКЛЮЧАЮЩЕЕ ИЛИ соединен с первым входом схемы И, второй вход схемы И первого разряда формирователя соединен с входом синхронимции D-триггера и выходом тактовых синхроимпульсов устройства синхронизации, а второй вход схемы И каждого последующего разряда формирователя соединен с входом синхронизации D-триггера данного разряда и выходом схемы И предыдущего разряда, выход схемы И последнего разряда формирователя соединен с входом синхронизации формирователя тестовой последовательности.The result of the implementation of the claimed invention is to obtain a universal means of monitoring a wide range of digital integrated circuits, using which there are almost no costs for the development of control programs for individual types of microcircuits. This result is achieved due to the fact that N D-flip-flops, N EXCLUSIVE OR circuits, N AND circuits with inverse logic and N are introduced into the device containing the N-bit shaper of the test sequence of input signals of the control object, the N-channel signature analyzer and the synchronization device resistors, the output of each discharge of the test sequence former is connected to the data input of the D-trigger and the first input of the EXCLUSIVE OR circuit, the output of the D-trigger is connected to the second input of the EXCLUSIVE OR circuit and through the resistor with input house of the control object, the output of the circuit EXCLUSIVE OR connected to the first input of the circuit AND, the second input of the circuit And the first discharge of the driver is connected to the synchronization input of the D-trigger and the output of the clock pulses of the synchronization device, and the second input of the circuit And of each subsequent discharge of the driver is connected to the synchronization input D -trigger of this discharge and the output of the circuit AND the previous discharge, the output of the circuit AND the last discharge of the shaper is connected to the synchronization input of the shaper of the test sequence.
RU94030318/07A 1994-08-17 1994-08-17 Device for testing digital integral circuits RU94030318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
RU94030318/07A RU94030318A (en) 1994-08-17 1994-08-17 Device for testing digital integral circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
RU94030318/07A RU94030318A (en) 1994-08-17 1994-08-17 Device for testing digital integral circuits

Publications (1)

Publication Number Publication Date
RU94030318A true RU94030318A (en) 1996-08-10

Family

ID=48448758

Family Applications (1)

Application Number Title Priority Date Filing Date
RU94030318/07A RU94030318A (en) 1994-08-17 1994-08-17 Device for testing digital integral circuits

Country Status (1)

Country Link
RU (1) RU94030318A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2725333C1 (en) * 2019-09-23 2020-07-02 Акционерное общество Научно-производственный центр "Электронные вычислительно-информационные системы" (АО НПЦ "ЭЛВИС") Test unit of ring generators on complementary metal-oxide-semiconductor transistors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2725333C1 (en) * 2019-09-23 2020-07-02 Акционерное общество Научно-производственный центр "Электронные вычислительно-информационные системы" (АО НПЦ "ЭЛВИС") Test unit of ring generators on complementary metal-oxide-semiconductor transistors

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