RU7778U1 - DIGITAL DEVICE FOR CONTROL OF VENTAL CONVERTER - Google Patents

Abstract

A digital device for controlling a three-phase valve converter, containing a clock generator, three communication units with a network, each with an integrator, a zero-organ, an inverter, two one-shots, two three-input OR elements, each input of the first of which is connected to the output of the first one-shot, respectively, of the first, second and a third communication unit with the network, each input of the second three-input OR element is connected to the output of the second one-shot, respectively, of the first, second and third communication units with the network, the distributor and pulses, a time delay device, the inputs of which are connected to the outputs of the first and second elements OR, and the outputs are connected to the inputs of the pulse distributor, characterized in that the first, second and third counters with a capacity corresponding to the bit of the control word of the job, RS are introduced into the time delay device -trigger, D-trigger, integrating unit, and a clock frequency control input is introduced into the clock generator, and the output of the first OR element is connected to the preliminary recording input SE of the first counter, with the input reset the third counter and with the R-input of the RS-flip-flop, the output of the second OR element is connected to the preliminary recording input SE of the second counter and with the S-input of the RS-flip-flop, the output of the clock generator is connected to the clock inputs of the first, second and third counters, the output of the highest order the third counter is connected to the clock input of the D-trigger and to the counter prohibition input of the third counter, the output of the RS-trigger is connected to the D-output of the D-trigger, the output of the D-trigger is connected to the input of the integrating unit, the output of the integrating unit is connected to the control input so

Description

The utility model relates to electrical engineering and can be used to control AC / DC valve converters.

A device for controlling a valve converter is known, comprising three communication units with a network, each with an integrator, a zero-organ, an inverter, two single-vibrators, two three-input OR elements. each input of the first of which is connected to the output of the first one-shot, respectively, of the first, second and third communication blocks with the network, each input of the second three-input element OR is connected to the output of the second one-shot, respectively, of the first, second and third communication blocks with the network / 1 /.

The disadvantages of such a device are: a narrow range of functionality, due to incompatibility with digital control systems; low reliability, due to a large number of elements: the need to adjust the minimum and maximum cutoff angles; the need to match the amplitude of the control signal with the amplitude of the sawtooth generators: the need to adjust the correction device.

Of the known technical solutions, the closest in technical essence to the claimed object is a digital device for controlling a valve converter, containing a clock generator, three communication units with a network, each with an integrator, zero-organ, inverter, two one-shots, two three-input elements OR, each input the first of which is connected to the output of the first one-shot, respectively the first, second and third blocks of communication with the network, each input of the second three-input element OR is connected to the output of the second monostable respectively first, second and grated with a network communication unit, the pulse distributor, the time delay unit, whose inputs are connected to outputs of the first and second OR elements and outputs connected to the inputs of the pulse distributor / 2 /.

- The disadvantages of the known utility model are: a narrow range of regulation and functionality; lack of precision control of the output voltage and reliability of the device.

The low accuracy when controlling a three-phase symmetric thyristor bridge is explained by the following. With an eight-bit job word, the control code contains 256 discrete. In the known device, the range of 256 discrete serves 120 + 30 150 electrical degrees. Part of the bits of the job word is used to synchronize the control angles to the phases.

For a three-phase symmetrical bridge, the synchronization angle is 30 electrical degrees or 42.7 discrete with an eight-bit code. To control the cutoff angle of the thyristors, there remains 213.3 discrete, instead of 256 discrete, which significantly reduces the control range.

The low reliability of the known utility model is manifested when the control word disappears and the phase network frequency changes. The disappearance of the control word leads to the entry of a zero code in the timer and, as a consequence, to the loss of synchronization in phases and to a surge in the output voltage, since pulses to open the thyristors are formed at the moments when the network passes through zero phases.

A decrease in the network frequency leads to an increase in the minimum cutoff angle o min and to overshoot the maximum cutoff angle y (max. The maximum cutoff angle becomes more than 120 electrical degrees, which leads to a voltage drop at the maximum control angles. An increase in the network frequency leads to a decrease in o (. Max and o Ј min overshoot, which leads to a voltage jump at small control angles.

The purpose of the utility model is to expand the range of regulation and functionality, as well as improving the accuracy of control of the output voltage and the reliability of the device.

This goal is achieved by the fact that the first, second and third counters with a capacity corresponding to the capacity of the control word of the task, that is, 256 discrete, are introduced into the time delay device; RS trigger D trigger an integrating unit: and a clock frequency control input is introduced into the clock, and the output of the first OR element is connected to the preliminary recording input SE of the first counter, to the reset input of the third counter and to the R-input of the RS-trigger; the output of the second OR element is connected to the input of the preliminary recording SE of the second counter and to the S-input of the RS trigger; the output of the clock generator is connected to the clock inputs of the first, second and third counters; the high-order output of the third counter is connected to the clock input of the D-flip-flop and to the count prohibition input of the third counter; RS-trigger output is connected to the D-input of the D-trigger: D-trigger output is connected to the input of the integrating unit; the output of the integrating unit is connected to the input of the frequency control of the clock generator; the data inputs of the first and second counters are connected to the corresponding bits of the control word; the overflow outputs P of the first and second counters are connected to the inputs of the pulse distributor.

b - The utility model is illustrated by the accompanying drawings, where in FIG. 1 shows a functional diagram of the device, and in FIG. 2, 3 are timing diagrams explaining the operation of the device.

In FIG. 4 shows a diagram of a possible implementation of the pulse distributor 10.

The device contains: communication units with the BS1-BSZ network according to the number of network phases, each of which contains an integrator 1, zero-organ 2, inverter 3, the first one-shot 4, the second one-shot 5, the first element OR 6, the second element OR 7, the first counter 8, the second counter 9, the pulse distributor 10, the third counter 11, the RS-flip-flop 12, the L-flip-flop 13. The integration unit 14, the clock generator 15, the frequency control input of the clock generator U control.

The output of the first element OR 6 is connected to the input of the preset SE of the first counter 8, with the reset input R of the third counter 11 and with the reset input R of the RS-trigger 12.

The output of the second element OR 1 is connected to the input of the preset SE of the second counter 9 and to the input of the installation S of the RS-trigger 12.

The output of the clock generator 15 is connected to the clock inputs C of the counters 8, 9, 11. The overflow outputs P of the counters 8, 9 are connected to the inputs of the pulse distributor 10.

The high-order output of the third counter 11 is connected to the clock input C of the D-flip-flop 19 and to the counter prohibition input V of the counter 11.

The output of the RS-trigger 12 is connected to the data input D of the D-trigger 13. The output of the D-trigger 13 is connected to the input of the integration unit 14.

The output of the integration unit 14 is connected to the control input

clock frequency U exercise. generator 15.

At the data inputs DO - Dn of the counters 8, 9, the word code of the job with the resolution of p.

The device works as follows.

Narrow synchronization pulses come from the outputs of the OR elements 6, 7, respectively, to the inputs of the preliminary recording SE of counters 8 and 9.

The pulse repetition period at the output of the element OR 6 (7):

That Tc / 3, (1)

where Tc is the period of the network frequency.

 h Pulses at the output of the element OR 7 appear at the moments of coincidence of positive half-waves of phase voltages. In FIG. 1 pulses at the outputs of elements 6, 7 are designated as XT1 and XT2. Thus, the pulses XT1 and XT2 are phase shifted relative to each other by 180 electrical degrees.

During the action of the pulse ХТ1 (ХТ2), the task code N is written into the counter 8 (9). After the termination of the action of the pulse ХТ1 (ХТ2), the counter 8 (9) under the action of the clock frequency fo (U control о), arriving at the counting input C, starts counting up.

After a time interval

3 (2 - N) Ato, (2)

where n is the capacity of the counter 8 (9);

D to - discrete time: D, 1о 1 / fo (U exercise. O);

at the output of the overflow P of the counter 8 (9), a pulse appears, which is fed to the pulse distributor 10 and then to control the thyristors.

In the formation of the interval involved all n - bits of the job code, with:

T min D to; (3)

n T max 2 D1o. (4)

Timing diagrams of the formation of control pulses and output voltage using the pulse distributor circuit 10 shown in FIG. 4. are shown in FIG. 2.

Suppose the network frequency decreases and, accordingly, the period To increases and becomes equal to:

Tv To + D Tv, (5)

where Tv is the increased pulse repetition period ХТ1 (ХТ2); D TV - the absolute value of the increase in the period following XT1 (XT2).

XT1 pulses are fed to the R-input of the RS-flip-flop and installed at its output 0. XT2 pulses are fed to the S-input of the RS-flip-flop and installed at its output 1. Thus, a signal in the form of a meander is generated at the output of the RS-flip-flop. The time to maintain a steady state at the output of the RS-trigger 12 is:

TV4 (To + D TV) / 2 (6)

The ХТ1 pulse also arrives at the R-input of the counter 11, setting it to 0. After the termination of the ХТ1 pulse, the counter 11 starts counting under the action of the frequency fo (U control о). - Through the time interval To4 & to (2/2) (7)

at the output of the high-order bit of counter 11, level 1 is set. The count is terminated. The counter 11 waits for the arrival of the next pulse XT1. Thus, the counting input of the D-trigger 13 receives a positive voltage drop at a time

To4 L to «(2/2), (8)

relative to the momentum XT1.

Since That TV, then, according to the positive voltage drop at the C input of the D-flip-flop, at its output, the value 0 is set, which is supplied to the integrator 14. Voltage U control. starts to decrease smoothly. The frequency f (U ex.) Also begins to decrease smoothly.

The process will continue until the arrival time of the positive voltage drop at the C input of the D-flip-flop Tp Mn (2/2), (9)

where D tn - discrete time of a changing frequency f (U exercise.);

Д1п 1 / fn (U exercise.n) (10)

not equal to the TV interval, so:

Tv tv / 2 (11)

The steady-state frequency fn (U control n) will ensure the filling of the interval TV between pulses ХТ1 (ХТ2) with a discrete number equal to 2.

Wherein:

  & t n (12) Gchgaah 2 D t n. (13)

A similar process occurs when the network frequency increases. In this case, the period To decreases and becomes equal to:

Tn To - D Tn. (14)

where Tn - reduced pulse repetition period

XT1 (XT2);

D Tn - the absolute value of the decrease in the period following XT1 (XT2).

&

n

n

n

n

-I In this case, the time to maintain a steady state at the output of the RS-trigger 12 will be:

Tn4 (To - & Tn) / 2 (15)

Since, in this case, Tn, then according to the positive voltage drop at the C input of the D-flip-flop 13, a value of 1 will be set at its output, which will go to the input of the integrator 14. Voltage U control. starts to increase smoothly. The frequency f (U control) will also begin to increase smoothly.

The process will continue until the arrival time of the positive voltage drop at the C input of the D-flip-flop 13 Tpc D tn4 (2/2), (16)

where Д tn4 is the time discrete of the changing frequency f (U ynp):

D tnv 1 / fnv (U exercise 4). (17)

not equal to the interval Tn4, so that:

Tpn Tn / 2. (18)

The steady-state frequency fnv (U control) will fill the interval Тn between pulses ХТ1 (ХТ2) with the number of time discrete 2

Wherein:

At min Atvn, (19)

n At max 2 Atvn (20)

If the control word disappears, the synchronization pulses XT1 and XT2 write a zero code in the counter 8, 9. As a result, control pulses at the outputs P of the counters 8, 9 are generated at a time relative to XT1 (XT2), equal to:

2 & t, (21)

that is, immediately before the arrival of the next pulses XT1 (XT2). The output voltage of the converter will be equal to zero.

Leaving the network frequency does not lead to unauthorized surges and voltage dips at the output of the converter due to automatic adjustment of the angles of the minimum and maximum cutoffs of the thyristors.

Timing diagrams of frequency control f (U control) are shown in FIG. 3.

& W3fY &

P

P

7 The use of the proposed device allows you to expand the functionality of the thyristor AC to DC converter, in particular, it can be used to power DC traction motors in railway transport, which uses diesel generators with a floating frequency of phase voltages to create a power network by automatically adjusting the clock frequency generator to the phase network frequency.

Using the proposed device also allows you to improve the accuracy of controlling the output voltage due to the full use of the bits of the control word.

Using the proposed device can improve the reliability of the AC to DC converter when the control word disappears and the mains frequency deviates from the nominal value due to automatic adjustment of the angles of the minimum and maximum cutoffs of the thyristors.

Sources of information. 1. Rectifier V-TPP-500-460 UZ passport OEP 561.00.00.000-01PS 2.A. USSR N-1660116, M. cl. 5. Authors: jfi (VNIITI, Kolomna) Н02 М 7/12. / P.V. Maximov G.M. Moskalenko

Claims (1)

A digital device for controlling a three-phase valve converter, containing a clock generator, three communication units with a network, each with an integrator, a zero-organ, an inverter, two one-shots, two three-input OR elements, each input of the first of which is connected to the output of the first one-shot, respectively, of the first, second and a third communication unit with the network, each input of the second three-input OR element is connected to the output of the second one-shot, respectively, of the first, second and third communication units with the network, the distributor and pulses, a time delay device, the inputs of which are connected to the outputs of the first and second elements OR, and the outputs are connected to the inputs of the pulse distributor, characterized in that the first, second and third counters with a capacity corresponding to the bit of the control word of the job, are introduced into the time delay device -trigger, D-trigger, integrating unit, and a clock frequency control input is introduced into the clock generator, and the output of the first OR element is connected to the preliminary recording input SE of the first counter, with the input reset the third counter and with the R-input of the RS-flip-flop, the output of the second OR element is connected to the preliminary recording input SE of the second counter and with the S-input of the RS-flip-flop, the output of the clock generator is connected to the clock inputs of the first, second and third counters, the output of the highest order the third counter is connected to the clock input of the D-flip-flop and to the counter-ban input of the third counter, the output of the RS-flip-flop is connected to the D-output of the D-flip-flop, the output of the D-flip-flop is connected to the input of the integrating unit, the output of the integrating unit is connected to the control input clock frequency, the data inputs of the first and second counters are connected to the corresponding bits of the control word, the overflow outputs P of the first and second counters are connected to the inputs of the pulse distributor.