RU74750U1 - DEVICE FOR FORMING AN ABSOLUTE SIGNAL VALUE - Google Patents

Abstract

A device for generating the absolute value of the signal, containing two comparators, an inverter, two analog keys; the input of the device is connected simultaneously to the first (non-inverting) input of the first comparator, the second (inverting) input of the second comparator, the input of the inverter; the inverter output is connected to the signal input of the second analog switch; the second and first inputs of the first and second comparators, respectively, are “grounded”; the output of the first comparator is simultaneously connected to the control input of the first analog key and the sign output of the device; the output of the second comparator is connected to the control input of the second analog key, characterized in that a phase shifter and an adder are introduced into the device, the input of the phase shifter connected to the input of the device, and the output to the signal input of the first analog key; the outputs of the first and second analog keys are the inputs of the adder, the output of which serves as the output of the device.

Description

The technical field to which the utility model relates.

The utility model relates to the field of digital technology, in particular to devices for converting unipolar analog-to-digital converters into bipolar ones.

State of the art

A device is known for generating the absolute value of the signal, containing a control circuit, five analog switches, a capacitor and a voltage follower on an operational amplifier ([1, p.31, Fig. 37] - ADC and DAC microcircuits. - M.: Dodeka-XXI Publishing House ”, 2005.-432 p.: Ill. + CD).

The disadvantage of this device is the low speed and low accuracy of the formation of the absolute value of the signal.

The closest in technical essence is a device for generating the absolute value of the signal, containing an inverter, two analog keys, two comparators, the device input being connected simultaneously to the first (non-inverting) input of the first comparator, the second (inverting) input of the second comparator, the input of the first analog key, the inverter input, the output of which is connected to the input of the second analog switch; the second and first inputs, respectively, of the first and second comparators, are “grounded”; the outputs of the first and second comparators are connected to the control inputs of the corresponding analog keys, the outputs of which are the output of the device. (Rathor T.S. Digital measurements. ADC / DAC. - M.: Technosphere 2006.-392 s; Fig. 6.50, p. 266).

The disadvantage of this device is the low speed and

low accuracy of the formation of the absolute value of the signal.

Utility Model Disclosure

The technical result that can be achieved using the proposed utility model is to increase the accuracy of the formation of the absolute value of the signal while increasing speed.

The technical result is achieved by the fact that a phase shifter and an adder are introduced into the device for generating the absolute value of the signal, which contains two comparators, an inverter, two analog keys, and the input of the device is connected simultaneously to the first (non-inverting) input of the first comparator, the second (inverting) input of the second comparator, the input of the phase shifter, the input of the inverter, the output of which is connected to the input of the second analog switch; the phase shifter output is connected to the input of the first analog switch; the second and first inputs, respectively, of the first and second comparators, are “grounded”; the outputs of the first and second comparators are connected to the control inputs of the corresponding analog keys, the outputs of which are the inputs of the adder, the output of which serves as the signal output of the device; the output of the first comparator is simultaneously a sign output of the device.

Brief Description of the Drawings

Figure 1 shows the structural diagram of a device for generating the absolute value of the signal.

Figure 2 shows the timing diagrams explaining the principle of operation of the device.

Figure 3 shows the timing diagrams explaining the disadvantages of the prototype.

Utility Model Implementation

The device for generating the absolute value of the signal contains two comparators 1 and 2, a phase shifter 3, an inverter 4, two analog switches 5 and 6, an adder 7, and the input of the device is connected simultaneously to the first (non-inverting) input of the comparator 1, the second (inverting) input of the comparator 2, the input of the phase shifter 3, inverter 4; the output of the phase shifter 3 is connected to the signal input of the first analog switch 5; the output of the inverter 4 is connected to the signal input of the second analog switch 6; the second and first inputs, respectively, of the comparators 1 and 2, are “grounded”; the outputs of the comparators 1 and 2 are connected to the control inputs, respectively, of the analog keys 5 and 6, the outputs of which are the inputs of the adder 7, the output of which serves as the signal output of the device; the output of the comparator 1 is simultaneously a sign output of the device.

The block diagram of the device for generating the absolute value of the signal is shown in figure 1.

The operation of the device is illustrated by the timing diagrams shown in figure 2.

The device for generating the absolute value of the signal is designed to determine the sign (polarity) of the voltage level of the input signal and relay the signal further with a given transmission coefficient, in case of its positive polarity, and in the case of negative polarity, additionally expose the translated signal to the inversion.

The principle of the functioning of the proposed device is based on the fact that the passage of a signal along the i-th part of the electric circuit is accompanied by its delay for a while Δt _i .

A device for generating the absolute value of the signal operates as follows.

In the case of a positive polarity signal entering the device input:

- comparator 1 generates a signal with a level of logical units, Fig.2.b;

- comparator 2 generates a signal with a logic level of zero, Fig.2.v;

- a signal with a logical unit level is sent to the sign output of the device;

- analog key 5 is put into the open state;

- analog key 6 is put into a closed state;

- the input signal shifted by the time Δt (Fig.2.d), through the phase shifter 3, is transmitted, through the open analog switch 5, to the first input of the adder 7;

- the adder 7 normalizes the transfer coefficient of the device and translates the signal to the output, Fig.2.e.

In the case of a negative polarity signal entering the device input:

- comparator 1 generates a signal with a logic level of zero, Fig.2.b;

- the comparator 2 generates a signal with a level of logical units, Fig.2.v;

- a signal with a logic zero level is sent to the sign output of the device;

- analog key 5 is put into a closed state;

- analog key 6 is put into the open state;

- the input signal, inverted and shifted by the time Δt (Fig.2.g), through the inverter 4, is transmitted, through the open analog switch 6, to the second input of the adder 7;

- the adder 7 normalizes the transfer coefficient of the device and translates the signal to the output, Fig.2.e.

In the proposed device, there is a parallel signal processing performed in accordance with the condition:

where Δt _inv is the signal transit time through the inverter (inverter 4);

Δt _{comp.1, 2} - response time of the first comparator (comparator 1), the second comparator (comparator 2);

Δt _{CA1, 2} - operating the first analog switch (analog switch 5), a second analog switch (analog switch 6);

Δt _fv is the signal transit time through the phase shifter (phase shifter 3).

The proposed device is characterized in that:

1) due to the non-criticality of the delay time introduced by the inverter 4, in the circuits of operational amplifiers, on the basis of which both the inverter 4 and the phase shifter 3 are run, it is possible to use correction circuits, which in turn provides better reproduction of the input signal shape (with a lesser degree distortion) at higher frequencies than in the prototype.

2) the ability to reduce the time it takes for the signal to pass through the phase shifter 3 and inverter 4 (primarily by changing the parameters of the correction circuit) to the total switching time of the comparator 1 (2) and analog switch 5 (6), provides a distortion-free formation of the shape of the absolute value of the signal.

That is, in the proposed device, there is an increase in the accuracy of formation of the absolute value of the signal while increasing speed.

This statement is fully confirmed by time charts explaining the principle of operation of the prototype, figure 3.

The prototype functioning algorithm assumes that the input signal, in the case of its positive polarity, is switched to the output of the device without any preliminary processing. And in the case of negative polarity, it is previously inverted.

Given the final response time of the comparators, keys (Fig.3.b, c), the phase shift of the signal at the output of the inverter (Fig.3.g), as well as the possible mismatch of the transmission coefficients of the device during the translation of inverted and non-inverted signals, it is legitimate to say low speed and low accuracy of formation

the absolute value of the signal (Fig.3d) prototype.

Claims (1)

A device for generating the absolute value of the signal, containing two comparators, an inverter, two analog keys; the input of the device is connected simultaneously to the first (non-inverting) input of the first comparator, the second (inverting) input of the second comparator, the input of the inverter; the inverter output is connected to the signal input of the second analog switch; the second and first inputs of the first and second comparators, respectively, are “grounded”; the output of the first comparator is simultaneously connected to the control input of the first analog key and the sign output of the device; the output of the second comparator is connected to the control input of the second analog key, characterized in that a phase shifter and an adder are introduced into the device, the input of the phase shifter connected to the input of the device, and the output to the signal input of the first analog key; the outputs of the first and second analog keys are the inputs of the adder, the output of which serves as the output of the device.