RU59914U1 - COMPOSITE FAST ANALOG-DIGITAL CONVERTER - Google Patents

Abstract

The utility model relates to the field of digital technology, in particular to devices for converting analog voltage to digital code. The essence of the utility model is that to increase the accuracy and speed of analog-to-digital conversion of fast processes, the composite high-speed analog-to-digital converter, in comparison with the prototype, additionally contains a sampling-storage circuit, an analog key, a memory register, a control input, a synchronization unit containing an RS trigger and two delay elements. 4 ill. 1 P-ly.

Description

The technical field to which the utility model relates.

The utility model relates to the field of digital technology, in particular to devices for converting analog voltage to digital code.

State of the art

A device for a high-speed analog-to-digital converter (ADC) is known, which contains two groups of differential switches on transistors with n switches in each group and 2 · n reference current sources, three amplitude analyzers summing resistors, and the bases of the first transistors of each switch are connected to the input bus and the input of the first amplitude analyzer, and the base of the second transistors with voltage sources, the emitters of the transistors of each switch are connected to the corresponding sources cam of the reference current, the first conclusions of the summing resistors are connected to the power supply bus, and the second conclusions are connected to the inputs of the second and third amplitude analyzers, respectively (A.Arbel R. Kurz., Fast ADC, IEEE Trans on Nucl Sc., Vol. NS-22 (1975), Febr., S 446-449).

The disadvantage of this device is its low accuracy. A device for a high-speed analog-to-digital converter is known, which contains three amplitude analyzers, two groups of differential switches on transistors and reference current sources according to the number of coarse quanta, conventionally assumed to be four, although this number can be any other, and two summing resistors. Reference voltages are applied to the bases of the right ones according to the transistor circuit

U ₁ , U ₁ + ΔU, U ₂ , U ₂ + ΔU. An analog input signal is applied to the bases of the left ones according to the transistor circuit and the first inputs of all three amplitude analyzers, the second inputs of the second and third amplitude analyzers are connected to the corresponding summing resistors. The outputs of the amplitude analyzers form the output of the device (USSR Author's Certificate, No. 750722 of 04.24.78).

The disadvantage of this device is that on its basis it is almost impossible to implement an accurate (multi-bit) and at the same time high-speed ADC.

The closest in technical essence and the achieved positive effect and accepted by the authors as a prototype is a composite high-speed ADC containing an m-bit parallel ADC of a rough scale, two DC voltage sources, an arithmetic-logic unit, two exact scale digitization units; moreover, the arithmetic-logic unit contains two multiplexers, an exclusive OR element and an adder of two m-bit numbers, and each digitizing unit of the exact scale contains a difference amplifier with a resistor connected in parallel to the inverting input, a scale comparator, an n-bit parallel ADC and a group of k identical current switches, each of which consists of a differential stage on transistors, a current generator and a positive DC bus + E (RF Patent, No. 2110887 from 05.29.96).

The disadvantage of this analog-to-digital converter is the low accuracy of analog-to-digital conversion of fast processes, accompanied by an underestimation of speed relative to the level that is potentially possible for parallel structures.

These shortcomings are due to a possible change in the voltage level of the input signal during the conversion of fast processes, as well as to the dynamic mode of operation of the digitizing units of the accurate scale in the absence of any synchronizing devices and

devices for sampling and storing the voltage level of the input signal, which inevitably leads to a continuous change of codes at the output of the off-scale comparator, and therefore to a compulsory increase in the time of generating the code at the output of the arithmetic-logical unit and, as a whole, to conversion errors.

Utility Model Disclosure

The technical result that can be achieved using the proposed utility model is to increase the accuracy and speed of analog-to-digital conversion of fast processes.

The technical result is achieved by the fact that a composite high-speed analog-to-digital converter (ADC) containing an m-bit parallel ADC of a rough scale, two DC voltage sources, an arithmetic-logic unit, two digitization units of an accurate scale, and the arithmetic-logical unit contains two multiplexers , an exclusive OR element and an adder of two m-bit numbers; and each accurate scale digitizing unit contains a difference amplifier with a resistor connected in parallel to the inverting input, a scale comparator, an n-bit parallel ADC and a group of k identical current switches, each of which consists of a differential stage on transistors, a current generator, and a positive constant bus voltage + E, combined into an analog-to-digital conversion unit, a sampling-storage scheme, a synchronization unit, an analog key, a memory register, a control input, and analog in od inverter connected to the input sample and hold circuit, the inverter control input coupled to an input of the synchronization and control input of the sample-hold circuit, whose output is an analog switch connected to the input, which control input is connected to the first output block

synchronization, the second and third outputs of which are connected to the control inputs of the memory register, respectively, recording and reset, the inputs of which are connected to the outputs of the analog-to-digital conversion unit, the output of the analog key is connected to the input of the analog-to-digital conversion unit; and the synchronization unit contains two delay elements and an RS-trigger; the input of the synchronization unit is connected to the inputs of both delay elements and the S input of the RS-trigger, the output of the latter is the first output of the synchronization unit, the output of the second delay element is the third output of the synchronization unit, and the output of the first delay element is connected to the R input of the RS-trigger is the second output of the synchronization block.

Brief Description of the Drawings

Figure 1 shows the structural diagram of a composite high-speed analog-to-digital Converter.

Figure 2 shows the structural diagram of the synchronization unit.

Figure 3 shows the structural diagram of the block analog-to-digital conversion.

4 is a timing chart explaining the operation of a composite high-speed analog-to-digital converter.

Utility Model Implementation

A composite high-speed analog-to-digital converter (ADC) consists of a sampling-storage circuit 1, the input of which is connected to an analog (information) input of the converter, the control input of the converter is connected to the input of the synchronization unit 2 and the control input of the sampling-storage circuit 1, the output of which is connected to the input of the analog key 3, the control input of which is connected to the first output of the synchronization unit 2, the second and third outputs of which are connected to the control inputs of the memory register 4, respectively records

and a reset, the inputs of which are connected to the outputs of the analog-to-digital conversion unit 5, the output of the analog switch 3 is connected to the input of the analog-to-digital conversion unit 5, which contains an m-bit parallel ADC of a rough scale 6, the first and second DC voltage sources 7 and 8, an arithmetic logic unit 9, two digitization units of an accurate scale 10, wherein the arithmetic logic unit 9 contains two multiplexers 11 and 12, an exclusive OR 13 element and an adder 14 of two m-bit numbers; and each block of digitization of the accurate scale 10 contains an amplifier of difference 15 with a resistor 16 connected in parallel to the inverting input, a scale comparator 17, an n-bit parallel ADC 18, and a group 19 of k identical current switches 20, each of which consists of a differential stage on the first 21 and the second 22 npn transistors, a current generator 23 and a positive DC bus + E 24.

The block diagram of the synchronization unit 2 is shown in figure 2.

The input of the synchronization unit 2 is connected to the inputs of both delay elements 25 and 26 and the S input of the RS-trigger 27, the output of the latter is the first output of the synchronization unit 2, the output of the second delay element 26 is the third output of the synchronization unit 2, and the output of the first delay element 25 is connected to R to the input of the RS-trigger 27 and at the same time is the second output of the synchronization unit 2.

The operation of the device is illustrated by the timing diagrams shown in figure 4.

Composite high-speed analog-to-digital Converter operates as follows.

The pulse of duration t ₁ ÷ t ₂ (Fig.4.a), arriving at the control input of the converter, at time t ₁ allows the sampling-storage circuit 1 to select and store the voltage level of the input signal.

By time t ₂ (Fig. 4.a), the sample-storage circuit 1 completes the memorization process. In the General case, the interval t ₁ ÷ t ₂ (Fig.4.a) is calculated

units nc. (In the AD9059 ADC, the aperture time is 2.7 ns. (Http://www.gaw.ru/pdf/AD/adc/ad9059.pdf), the sampling time of the built-in sampling-storage circuit is 1 ns. (Www.compitech. com / html.cgi / arhiv / 00_01 /stat_34.htm)).

The RS-trigger 27 of the synchronization unit 2 in a single state at the input S is translated at time t ₂ (Fig.4.b) the trailing edge of the input pulse. The RS-trigger 27 generates an analog key control signal 3, which is fed to the first output of synchronization unit 2.

At time t ₂ (Fig.4.b), the potential coming from the first output of the synchronization unit 2 puts the analog switch 3 in the open state. The voltage from the output of the sample-storage circuit 1 is supplied to the input of the analog-to-digital conversion unit 5. The sample-storage circuit 1 keeps the voltage level of the input signal unchanged until the conversion process of this sample is completed.

Due to the invariance of the voltage level of the input signal, a virtually static mode of operation by the input signal will take place:

- parallel m-bit ADC rough scale 6 included in the block of analog-to-digital conversion 5; as a result, the code at the output of the parallel m-bit ADC of the coarse scale 6 is stabilized, and the jitter of the low-order code will not be observed;

- parallel n-bit ADC 18 included in the block of analog-to-digital conversion 5; as a result, the code at the output of the parallel n-bit ADC 18 is stabilized and there will be no jitter of the low-order code;

- groups of k identical current switches 19, as a result of which the current at the output of a group of k identical current switches 19 is stabilized, and there will be no voltage fluctuations at the inverting input of the difference amplifier 15.

The latter is especially important, since the off-scale comparators 17 operate at values of overexcitation voltages,

many times higher than the values of overexcitation voltages of the corresponding comparators of the m-bit parallel ADC of a rough scale 6, and therefore, without taking measures to stabilize the input level voltage, which takes place in the prototype, due to fluctuations repeatedly amplified by the difference amplifier 15, a continuous change of states will be observed codes at the output of the off-scale comparators 17. Inconsistent change of codes received at the inputs of the arithmetic-logical unit 9 will lead to a decrease in the accuracy of analog conversions x signals block analog-to-digital conversion 5, and to reduce its speed due to the inevitability of an increase in transient times.

The signal (pulse) at the control input of the converter of duration t ₁ ÷ t ₂ (Fig.4.a):

- delayed by the delay element 26 of the synchronization unit 2 to the moments t ₃ ÷ t ₄ (Fig.4.v), the delay element 26 generates a reset signal of the memory register 4, which is received at the third output of the synchronization unit 2;

- delayed by the delay element 25 of the synchronization unit 2 to the moments t ₅ ÷ t ₆ (Fig.

The signal of duration t ₃ ÷ t ₄ (Fig.4.c), coming from the third output of the synchronization unit 2 to the input of the memory register 4 reset control, performs the reset of the memory register 4 triggers.

For the time interval t ₂ ÷ t ₅ (Fig.4.g) block analog-to-digital conversion 5 completes the conversion of the input analog signal.

A signal of duration t ₅ ÷ t ₆ (Fig.

When the proposed Converter in cyclic mode,

information about the converted sample of the input signal will be stored in memory register 4 during the interval (Fig.4.d), that is, the further process of reading information from the converter will not introduce a delay in the process of analog-to-digital conversion and will not reduce the speed of the converter as a whole.

In the prototype, this feature is not provided.

The proposed utility model in comparison with the prototype and other well-known technical solutions has the following advantages:

- the possibility of eliminating methodological conversion errors that affect the final conversion time of the analog signal. Despite the introduction of guaranteed time protection intervals (delays), the proposed composite high-speed converter is rated best in comparison with the prototype according to the performance criterion relative to the potential for parallel structures;

- thanks to the introduction of a sampling-storage scheme into the converter and tight synchronization of the converter operating modes, it was possible to avoid changing the voltage level of the input signal during the conversion of fast-moving processes, which means that it was possible to increase the accuracy of the analog-to-digital conversion of fast-moving processes.

Claims (1)

A composite high-speed analog-to-digital converter (ADC) containing an m-bit parallel ADC of a rough scale, two DC voltage sources, an arithmetic-logical unit, two blocks of digitization of an exact scale, and the arithmetic-logical unit contains two multiplexers, an exclusive OR element and an adder of two m-bit numbers, and each block for digitizing the exact scale contains a difference amplifier with a resistor connected in parallel to the inverting input, a roll-off comparator, an n-bit parallel ADC, and a group of k and identical current switches, each of which consists of a differential cascade on transistors, a current generator and a positive DC bus + E, combined into an analog-to-digital conversion unit, characterized in that a sampling-storage circuit, a synchronization unit, an analog switch are introduced into it memory register, control input, wherein the analog input of the converter is connected to the input of the sample-storage circuit, the control input of the converter is connected to the input of the synchronization block and the control input of the sample-x An antenna whose output is connected to an analog key input, the control input of which is connected to the first output of the synchronization unit, the second and third outputs of which are connected to the control inputs of the memory register, respectively, of recording and reset, whose inputs are connected to the outputs of the analog-to-digital conversion unit, the analog output the key is connected to the input of the analog-to-digital conversion unit, and the synchronization unit contains two delay elements and an RS-trigger, while the input of the synchronization unit is connected to the inputs of both elements delay and S entry RS-trigger, the output of the latter is the first output of the synchronization unit, an output of the second delay element is a third output of the synchronization unit and the output of the first delay element connected to the R input of RS-flip-flop and is also a second output of the synchronization unit.