RU34827U1 - Pulse Width Modulator - Google Patents

Abstract

A pulse-width modulator containing a power source, a control element, the first output of which is connected to the first output of the power source, and the second output to the second output of the resistor current sensor and the first output of the limiting resistor, the second output of which is connected to the second output of the power source, the current source controlled circuit, the first and second conclusions of which are connected respectively with the first and second terminals of the resistor current sensor, a logic chip based on complementary MOS transistors (CMO microcircuit), containing at least five inverters, the first power output of which is connected to the first output of the power source, and the second power output to the second output of the power source, the output of the first inverter is connected to the input of the second inverter, a frequency-setting capacitor connected between the input of the first inverter and the output of the second inverter, a frequency-setting resistor connected between the input and output of the first inverter, a timing capacitor, the first output of which is connected to the output of the second inverter, and the second output through a pull-up resistor - to the second output of the power supply, the first diode, the anode of which is connected to the second output of the time-varying capacitor, and the cathode - to the output of the third inverter, the input of the fourth inverter is connected to the anode of the first diode, and its output - to the input of the fifth inverter, the output of which is an output of a pulse-width modulator, characterized in that a first resistor and a second diode are inserted into it and a Schmidt trigger is included at the input of each inverter of the CMOS chip, the first resistor being connected between the first output

Description

Pulse Width Modulator.

The utility model relates to electrical engineering and can be used in the construction of control devices for switching power supplies.

Known pulse-width modulator (PWM), containing a linearly varying voltage generator, a feedback signal amplifier, a current protection comparator and a pulse-width modulated signal comparator 1, 2. PWM is used in the construction of control devices for switching power supplies to generate power switch control signals.

The disadvantages of this technical solution include its implementation on analog functional units (amplifiers, comparators), which, regardless of the operating mode, continuously consume current. As a result, the entire PWM node consumes a relatively large current (tens of milliamps). This reduces the overall UTD of the power source using the specified PWM, complicates it, forcing to introduce an additional low-voltage channel specifically for powering the PWM. If, in addition, the modulator operates at a high frequency (hundreds of kilohertz), the above-mentioned functional units are executed on bipolar transistors, which further increases energy consumption. With a decrease in the load at the output of the power source or at idle, the voltage of the power channel of such a SHOIM decreases to values that impede the normal operation of the power source as a whole. These shortcomings narrow the functionality and scope of the considered technical solutions.

MKI7: G 05 F 1/56 power supply, given in 3. Its functional diagram is shown

in FIG. 1. The pulse-width modulator contains a power source, a control element, the first output of which is connected to the first output of the power source, and the second output to the second output of the resistor current sensor and the first output of the limiting resistor, the second output of which is connected to the second output of the power source, current controlled circuit, the first and second conclusions of which are connected respectively with the first and second terminals of the resistor current sensor, a logic chip based on complementary MOS transistors (CMOS - microcircuit), containing at least five inverters, the first power output of which is connected to the first output of the power source, and the second output of the power is connected to the second output of the power source, the output of the first inverter is connected to the input of the second inverter, a frequency-setting capacitor connected between the input of the first inverter and the output a second inverter, a frequency setting resistor connected between the input and output of the first inverter, a timing capacitor, the first output of which is connected to the output of the second inverter, and the second output through bp the resisting resistor - to the second output of the power source, the first diode, the anode of which is connected to the second output of the timing capacitor, and the cathode - to the output of the third inverter, the input of which is connected to the first output of the resistor current sensor, the input of the fourth inverter is connected to the anode of the first diode, and its output - to the input of the fifth inverter, the output of which is the output of a pulse-width modulator.

Common features of the proposed technical solution and prototype are a power source, a control element, the first output of which is connected to the first output of the power source, and the second output to the second output of the resistor current sensor and the first output of the limiting resistor, the second output of which is connected to the second output of the power source, controlled current source, first and

2 second conclusions of which are connected respectively to the first and second

the terminals of the resistor current sensor, a logic chip based on complementary MOS transistors (CMOS chip) containing at least five inverters, the first power output of which is connected to the first output of the power source, and the second output to the second output of the power source, the output of the first inverter connected to the input of the second inverter, a frequency-setting capacitor connected between the input of the first inverter and the output of the second inverter, a frequency-setting resistor connected between the input and output of the first inverter, bp a decoupling capacitor, the first terminal of which is connected to the output of the second inverter, and the second terminal, through the timing resistor, to the second terminal of the power source, the first diode, the anode of which is connected to the second terminal of the timing capacitor, and the cathode - to the output of the third inverter, the fourth inverter input is connected to the anode of the first diode, and its output to the input of the fifth inverter, the output of which is the output of a pulse-width modulator.

At the first and second inverters, a square-wave driver was made, the pulse duration and pause of which is determined by the values of the frequency-setting resistor and capacitor. The timing diagram of the input voltage of the first inverter I1 is shown in FIG. 2a, and at the output of the second inverter I2, which is the output of the master oscillator, in FIG. 26. Through the time-setting capacitor, the signal from the output of the master oscillator goes to the input of the fourth inverter I4, and is removed from the output of the fifth inverter I5, which is the output of the pulse-width modulator. The charge time constant of the time-setting capacitor is selected several times longer than the period of the master oscillator, so that the maximum duration of the pulses at the outputs of the master oscillator and the pulse-width generator coincides. The current source of the monitored circuit measures the instantaneous current value in the power switch circuit. Instant value

1(,

3 voltages on the resistor current sensor in proportion to the value

indicated current and shown in FIG. 2g During a single state at the PWM output, the power switch is open, the current in the controlled circuit increases, during the zero state at the PWM output, the power switch is closed, and there is no current in the controlled circuit. The maximum value of the current in the controlled circuit Tmax corresponds to the voltage on the resistor current sensor, equal to the threshold voltage of the CMOS inverters of the microcircuit, which is 0.4 ... 0.5 of the supply voltage of the microcircuit.

Since the input resistance of the CMOS inverter is extremely large (10 ... Ohms), the instantaneous voltage value at the input of the inverter FROM during the pulse is the sum of the voltage drop across the limiting resistor 3 (constant bias) and resistor current sensor 5 (pulse component): UBX from Uorp + Up rWhen the resistance of control element 2 changes during PWM operation, the constant displacement Uorp changes. The maximum value of the voltage at the input of the third inverter FROM UBX from during the pulse is Unop.

When turned on, first SR1M generates pulses of maximum duration equal in duration to the width of the output pulse of the master oscillator (I2 inverter), and the voltage at the input of the third inverter FROM UBX from increases, remaining less than the threshold value Unop (Fig.2d). There is no feedback signal. The resistance of the control element is extremely high. If during the next working cycle the above Unop value is reached, at the output of the third inverter, and after this and at the PWM output, the zero state will be forcedly set. The power switch will close, which will protect it from overcurrent. When the adjustable PWM parameter, for example, the output voltage of the switching power supply, reaches its nominal value, a feedback signal appears, the resistance of the control element decreases and the current flowing through it creates

on the limiting resistor constant bias Uorp. Since the total value of the voltage at the input of the third IZ inverter during regulation does not exceed Unop, the amplitude of the pulse component of the voltage — the voltage drop at the Irdt resistor current sensor — should decrease. And this, in turn, can be achieved only by reducing the pulse duration at the output of the LSM. Thus, by varying the degree of conductivity of the regulating element, it is possible to widely vary the duration of the PWM output pulse.

The disadvantages of the considered technical solution include increased current consumption from the power source. This feature of the PWM under consideration is explained by the circuit of the output stage of all the elements of the CMOS chips - a complementary pair of field-effect transistors (p- and p-channel) 4. When the input voltage of the first inverter I1 approaches a threshold value, the p-channel transistor of the output stage goes into active mode . The R-channel transistor remains open for some time. At the same time, “through current” flows through them, uselessly consuming the energy of the power source and heating the microcircuit. This effect occurs every time the voltage at the inverter input relatively slowly approaches the threshold value, which is observed twice during the period at the input of the first inverter I1 and once during the period at the input of the third IZ (Fig. 2a, 2e).

The technical task of the proposed utility model is to reduce the current consumed from the power source and expand the functionality of the PWM.

The stated technical problem is solved by the fact that a pulse-width modulator is proposed comprising a power supply, a regulating element, the first output of which is connected to the first output of the power source, and the second output to the second output of the current resistor sensor and the first output of the limiting resistor, the second output

5

which is connected to the second output of the power source, the current source of the controlled circuit, the first and second conclusions of which are connected respectively to the first and second terminals of the resistor current sensor, a logic chip based on complementary MOS transistors (CMOS chip) containing at least five inverters, the first the power output of which is connected to the first output of the power source, and the second power output to the second output of the power source, the output of the first inverter is connected to the input of the second inverter, A capacitor connected between the input of the first inverter and the output of the second inverter, a frequency-setting resistor connected between the input and output of the first inverter, a timing capacitor, the first output of which is connected to the output of the second inverter, and the second output through the timing resistor to the second output of the power source, the first diode the anode of which is connected to the second output of the time-setting capacitor, and the cathode is connected to the output of the third inverter, the input of the fourth inverter is connected to the anode of the first diode, and its output is to the input of the fifth an inverter, the output of which is the output of a pulse-width modulator, the first resistor and the second diode introduced into it and a Schmidt trigger at the input of each inverter of the CMOS chip, the first resistor connected between the first output of the resistor current sensor and the input of the third inverter, to which a second diode is connected to the anode, the cathode of which is connected to the output of a pulse-width modulator.

The introduction of additional elements and non-obvious connections into the devices made it possible to reduce the current consumed by the PWM, which, in turn, extends its functionality.

The applicant did not find technical solutions having similar features with features that distinguish the claimed solution from the prototype, and, therefore, the proposed technical solution has significant differences. The proposed device is made of standard elements,

which are serially produced by industry. It is assembled by typical installation operations using standard equipment and does not require adjustment, which is especially important in serial production. Therefore, the proposed device meets the criterion of industrial applicability.

Pa fig. 3 shows a functional diagram of the proposed PWM.

The proposed pulse-width modulator contains a power source 1, a regulating element 2, a limiting resistor 3, a current source of a controlled circuit 4, a resistor current sensor 5, a frequency-setting capacitor 6 and a resistor 7, a CMOS logic chip 8, containing at least five I1 inverters - Ip with Schmidt triggers at the inputs, the first diode 9, the timing resistor 10 and the capacitor 11, the first resistor 12 and the second diode 13.

In the proposed PWM, the first output terminal of the CMOS chip 8 is connected to the first terminals of the regulator; its element 2 and power supply 1, the second terminal of the power supply of the CMOS chip 8 is connected to the second terminals of the limiting resistor 3 and power source 1. The second terminal of the regulating element 2 is connected to the first output of the limiting resistor 3 and the second conclusions of the current source of the controlled circuit 4 and the resistor current sensor 5, the first conclusions of which are connected to the input of the third inverter FROM and the anode of the second diode 13 through the first resistor 12. atod second diode 13 is connected to the output of the fifth inverter I5, which is the output PWM. The output of the third inverter FROM is connected to the cathode of the first diode 9, the anode of which is connected to the input of the fourth inverter I4 and the second output of the timing capacitor I, the first output of which is connected to the output of the second inverter I2. The timing resistor 10 is connected between the second terminals of the timing capacitor None of the power source 1. The output of the first inverter I1 is connected to the input of the second inverter I2, and the output

7 of the fourth inverter I4 - with the input of the fifth inverter I5. Frequency setting

a capacitor 6 is connected between the input of the first inverter I1 and the output of the second inverter I2. Frequency-setting resistor 7 is connected between the input and output of the first inverter I1.

As a regulatory element 2, as in the prototype, some element can be used that changes its resistance, for example, a phototransistor or optocoupler photodiode, magnetodod, etc. The current source of the controlled circuit 4 can be, for example, a current transformer, primary whose winding is included in the protected power circuit. Unused PWM circuits, inverters of the microcircuit can be connected in parallel with the fifth inverter to amplify the PWM output (not shown in Fig. 3).

The operation of the proposed PWM is illustrated in FIG. 4. In contrast to the prototype, the switching of the inverter I1 occurs at times when the voltage at its input reaches the tripping values Ucp and releasing Uoxn (Fig. 4a). The presence of the Schmidt trigger at the input of the inverter I1 eliminates the effect of “through currents with a relatively slow change in the input voltage, since the signal at the output of the Schmidt trigger (that is, at the input of the inverter itself) already has a rectangular shape with steep edges. The same effect takes place at the input of the inverter FROM (Fig. 4e).

When the PWM is turned on, there is no feedback signal, the regulating element 2 is closed, the voltage at the limiting resistor 3 is practically equal to 0. At the PWM output, rectangular pulses of maximum duration are generated, as in the prototype (Fig. 4c). A timing diagram of the current of the monitored circuit (or voltage across the resistor current sensor 5) is shown in FIG. The appearance and increase of the feedback signal entails an increase in the constant bias to values close to Ucp (Fig. 4e), and a corresponding decrease in the duration of the PWM output pulse. However, here, unlike

Jv / o26 2

8

of the prototype, the switching of the inverter FROM can only happen after the voltage at its input decreases to a minimum of UOTH-value. For this purpose, the circuit “first resistor 12 - second diode 13.” is inserted into the circuit. After setting the PWM output to zero, the second diode 13 opens and forcibly fixes the voltage at the input of the third inverter FROM at the level UDZ Uoxn (Fig. 4e). In this case, the first resistor 12 limits the current through the second diode 13. When a single state is established at the output of the CID, the second diode 13 is locked and does not affect the pulse formation process. Since the input resistance of the inverter is extremely large, the value of the first resistor 13 practically does not affect the operation of the PWM. The remaining parameters of the proposed PWM in comparison with the prototype remain unchanged.

In the manufactured SHOIM sample, the current consumed from the power source at the minimum output pulse duration (about 0.5 microseconds) was eight times less than that of the prototype. This circumstance allows us to expand the scope of the proposed SHR1M in the direction of micropower pulse converters, which expands its functionality.

Sources used when writing an application.

1. Integrated microcircuits: Microcircuits for switching power supplies and their application. - M. DODEKA, 1997, 224 p. - ISSN-587835-0010-6. from. 38.

2. Integrated circuits: Integrated circuits for switching power supplies and their application. - M. DODEKA, 1997, 224 p. - ISSN-587835-0010-6. from. 87.

3. Certificate for utility model JNf223006.

4. Zeldin E. A. Digital integrated circuits in information-measuring equipment. - L .: Energoatomizdat. Leningrad Department, 1986.- p. 65.

Claims (1)

A pulse-width modulator containing a power source, a control element, the first output of which is connected to the first output of the power source, and the second output to the second output of the resistor current sensor and the first output of the limiting resistor, the second output of which is connected to the second output of the power source, the current source controlled circuit, the first and second conclusions of which are connected respectively with the first and second terminals of the resistor current sensor, a logic chip based on complementary MOS transistors (CMO microcircuit), containing at least five inverters, the first power output of which is connected to the first output of the power source, and the second power output to the second output of the power source, the output of the first inverter is connected to the input of the second inverter, a frequency-setting capacitor connected between the input of the first inverter and the output of the second inverter, a frequency setting resistor connected between the input and output of the first inverter, a timing capacitor, the first output of which is connected to the output of the second inverter, and the second output through a pull-up resistor - to the second output of the power supply, the first diode, the anode of which is connected to the second output of the time-varying capacitor, and the cathode - to the output of the third inverter, the input of the fourth inverter is connected to the anode of the first diode, and its output - to the input of the fifth inverter, the output of which is an output of a pulse-width modulator, characterized in that a first resistor and a second diode are inserted into it and a Schmidt trigger is included at the input of each inverter of the CMOS chip, the first resistor being connected between the first output th current detector and the input of the third inverter, to which is connected a second diode anode, a cathode connected to the output of the pulse width modulator.