RU2824593C1 - Control method, semiconductor memory and electronic device - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: use for DM in a given test mode to prevent data processing errors by a circuit. Essence of the invention consists in the fact that the semiconductor memory device is in a given test mode, a first Model Register (MR) and a second MR associated with the Data Pin (DQ) are configured to directly determine the impedance of the Data Mask Pin (DM). For DM, there is no need to add determination of the state of the output signal generator and the corresponding control circuit for a given test mode in order to ensure adaptation of the given test mode to the DM.

EFFECT: enabling prevention of data processing errors by the circuit.

22 cl, 12 dwg, 3 tbl

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This disclosure is based on/claims priority from Chinese Patent Application No. 202210307454.8, filed on March 25, 2022, and Chinese Patent Application No. 202210498332.1, filed on May 9, 2022, the disclosures of which are incorporated herein by reference in their entirety.

AREA OF TECHNOLOGY

[0002] The present disclosure relates to the technical field of semiconductors, in particular, to a control method, a semiconductor memory device and an electronic device.

LEVEL OF TECHNOLOGY

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, which at least has a data pin (DQ) and a data mask pin (DM). In this case, DQ has two functions: writing data and reading data, and DM is configured to receive a write data mask input signal and mask unnecessary input data during the write operation, and supports only the data write function. In the fifth edition of the memory device specification (also called Double Data Rate 5 SDRAM (DDR5)) it is necessary to check the impedance of DM or DQ in some test modes.

DISCLOSURE OF THE ESSENCE OF THE INVENTION

[0004] The present disclosure provides a control method, a semiconductor memory device and an electronic device, and defines a control method for a DM in a given test mode to prevent data processing errors by the circuit.

[0005] In a first aspect, embodiments of the present invention provide a control method applied to a semiconductor memory device. The semiconductor memory device may include a DM. The DM may be configured to receive a recording data input mask signal. The method may include the following operations.

[0006] When the semiconductor memory device is in a specified test mode, in response to selecting the DM as a test object, the impedance of the DM is controlled as a first impedance parameter by a first model register (MR); or, in response to determining that the DM is not selected as a test object, the impedance of the DM is controlled as a second impedance parameter by a second MR.

[0007] In this case, the semiconductor memory device further includes at least one DQ, which is configured to receive or output data, wherein the first MR is configured to indicate that the impedance of at least one DQ in the output signal generator state is a first impedance parameter, and the second MR is configured to indicate that the impedance of at least one DQ in the termination state is a second impedance parameter.

[0008] In a second aspect, embodiments of the present invention provide a semiconductor memory device. The semiconductor memory device includes a first MR, a second MR, a DM, and a first driver circuit connected to the first MR, the second register, and the DM, respectively.

[0009] The DM is configured to receive a recording data input mask signal.

[0010] The first driver circuit is configured to, when the semiconductor memory device is in a given test mode, control the impedance DM as a first impedance parameter corresponding to the first MR in response to selecting the DM as a test object, or

[0011] controlling the impedance of the DM as a second impedance parameter corresponding to the second MR in response to determining that the DM is not selected as the test object.

[0012] In this case, the semiconductor memory device further includes at least one DQ that can be configured to receive or output data, wherein the first MR is configured to indicate that the impedance of at least one DQ in the output signal generator state is a first impedance parameter, and the second MR is configured to indicate that the impedance of at least one DQ in the termination state is a second impedance parameter.

[0013] In a third aspect, embodiments of the present invention provide an electronic device that includes the semiconductor memory device described in the second aspect.

[0014] In embodiments of the present invention, a control method, a semiconductor memory device and an electronic device are provided. When the semiconductor memory device is in a predetermined test mode, the first MR and the second MR related to the DQ are configured to directly determine the impedance of the DM. For the DM, there is no need to add the determination of the state of the output signal generator and the corresponding control circuit for the predetermined test mode in order to ensure the adaptation of the predetermined test mode to the DM. The impedance of the DM can be tested in the predetermined test mode to prevent data processing errors by the circuit.

BRIEF DESCRIPTION OF DRAWINGS

[0015] Fig. 1 is a block diagram of a control method according to one embodiment of the present invention.

[0016] Fig. 2 is a block diagram of another control method according to one embodiment of the present invention.

[0017] Fig. 3 is a schematic block diagram of a semiconductor memory device according to one embodiment of the present invention.

[0018] Fig. 4A is a local block diagram I of a semiconductor memory device according to one embodiment of the present invention.

[0019] Fig. 4B is a local block diagram II of a semiconductor memory device according to one embodiment of the present invention.

[0020] Fig. 5 is a schematic block diagram of a first decoding module according to one embodiment of the present invention.

[0021] Fig. 6 is a schematic block diagram of a first driver circuit according to one embodiment of the present invention.

[0022] Fig. 7 is a detailed schematic block diagram I of a first driver circuit according to one embodiment of the present invention.

[0023] Fig. 8 shows a detailed schematic block diagram II of a first driver circuit according to one embodiment of the present invention.

[0024] Fig. 9 is a schematic block diagram of a second driver circuit according to one embodiment of the present invention.

[0025] Fig. 10 is a detailed schematic block diagram of I of a second driver circuit according to one embodiment of the present invention.

[0026] Fig. 11 shows a detailed schematic block diagram II of a second driver circuit according to one embodiment of the present invention.

[0027] Fig. 12 is a schematic diagram of a composite structure of an electrical device according to one embodiment of the present invention.

IMPLEMENTATION OF THE INVENTION

[0028] The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are used only to illustrate the corresponding invention, but are not intended to limit it. In addition, it should be noted that for convenience of description, only parts related to the corresponding disclosure are shown in the drawings.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of the present invention. The terms used herein are for the purpose of describing embodiments of the present invention only and are not intended to be limiting.

[0030] In the following description, reference is made to “some embodiments” that describe a subset of all possible embodiments, but it should be understood that “some embodiments” may represent the same or different subsets of all possible embodiments and may be combined with each other without creating conflicts.

[0031] It should be noted that the terms "first\second\third" used in the embodiments of the present invention are used only to distinguish similar objects and do not represent a specific order of objects. It should be understood that the specific order or sequence of "first\second\third" may be interchangeable under possible circumstances, so that the embodiments of the present invention described herein may be implemented in an order different from that illustrated or described herein.

[0032] Below are explanations of professional terms used in embodiments of the present invention and the corresponding relationship of some nouns:

[0033] Dynamic Random Access Memory (DRAM)

[0034] Synchronous Dynamic Random Access Memory (SDRAM)

[0035] Double Data Rate SDRAM (DDR)

[0036] DDR5 Specification (DDR5 SPEC)

[0037] Data Pin (DQ)

[0038] Data Mask Pin (DM)

[0039] Package Output Driver Test Mode (PODTM)

[0040] Mode Register (MR)

[0041] Operand (OP)

[0042] The DDR5 SPEC defines a new test mode called PODTM, which is configured to enable the output driver of a DQ or DM via the host after the chip is packaged, while other DQs or DMs are in the terminated state, which makes it possible to test whether the increased impedance of the enabled DQ or DM in the output driver state is as expected. However, since the state of the DM output driver is not initially defined, PODTM may not be adapted to the DM, and data processing errors in the circuit easily occur.

[0043] Based on this, in embodiments of the present invention, a control method is provided. When the semiconductor memory device is in a predetermined test mode, the first MR and the second MR related to the DQ are configured to directly determine the impedance of the DM. For the DM, there is no need to add the determination of the state of the output signal generator and the corresponding control circuit for the predetermined test mode in order to ensure that the predetermined test mode is adapted to the DM. The impedance of the DM can be tested in the predetermined test mode to prevent the occurrence of data processing errors by the circuit.

[0044] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] In the embodiment of the present invention related to Fig. 1, a flow chart of a control method according to one embodiment of the present invention is shown. As shown in Fig. 1, this method may include the following operations.

[0046] In step S101, when the semiconductor memory device is in a predetermined test mode, in response to selecting the DM as the test object, the impedance of the DM is controlled as a first impedance parameter by the first MR; or, in response to determining that the DM is not selected as the test object, the impedance of the DM is controlled as a second impedance parameter by the second MR.

[0047] It should be noted that this control method is applicable to a semiconductor memory device. The semiconductor memory device includes a DM and at least one DQ. In this case, the DQ is configured to receive or output data and has a write function or a read function, and also has a completion state and an output signal generator state. The DM is configured to receive a signal of the input mask of the write data and has only a write function and has a completion state.

[0048] In an embodiment of the present invention, the specified test mode refers to a PODTM provided in DDR5, and the PODTM is configured to test the impedance of the DM or at least one DQ after packaging. More specifically, the PODTM allows the host to test an increased impedance of the DM or DQ.

[0049] When the DM is selected as a test object in the PODTM, the first MR is configured to control the impedance of the DM as a first impedance parameter. In this case, since the first MR is configured to indicate an increased impedance of the DQ in the state of the output signal generator, the host can test the increased impedance related to the output signal generator of the DM, and there is no need to determine the state of the output signal generator of the DM.

[0050] When the DM is not a test object in the PODTM, the second MR is configured to control the impedance of the DM as a second impedance parameter. In this case, since the second MR is configured to specify the impedance in the completion state, the influence of the DM on the test result of the selected test object can be excluded.

[0051] Thus, when the semiconductor memory device is in a given test mode, the first MR and the second MR are configured to directly determine the impedance of the DM. For the DM, there is no need to add the determination of the state of the output signal generator and the corresponding control circuit for the given test mode in order to ensure the adaptation of the given test mode to the DM, and the impedance of the DM can be checked in the given test mode in order to avoid data processing errors by the circuit.

[0052] In some embodiments, the method further includes the following steps.

[0053] When the semiconductor memory device is in a specified test mode, in response to selecting a DQ as a test object, the impedance of the DQ is controlled as a first impedance parameter by the first MR; or, in response to determining that the DQ is not selected as a test object, the impedance of the DQ is controlled as a second impedance parameter by the second MR.

[0054] Thus, when DQ is selected as a test object in PODTM, the increased impedance of the output signal driver of DQ is controlled by the first MR in such a way as to obtain a test result of DQ. When DQ is not used as a test object in PODTM, DQ is controlled as being in a terminated state by the second MR in such a way as to avoid the influence of DQ on the test result of the selected test object.

[0055] In some embodiments, it is determined that the semiconductor memory device enters a specified test mode and selects a test object by means of a third MR; or it is determined that the semiconductor memory device does not enter a specified test mode by means of a third MR.

[0056] It should be understood that each MR has a plurality of OP bits for providing corresponding control functions. In an embodiment of the present invention, an OP related to an embodiment of the present invention in a first MR is referred to as a first OP, an OP related to an embodiment of the present invention in a second MR is referred to as a second OP, and an OP related to an embodiment of the present invention in a third MR is referred to as a third OP.

[0057] In other words, in an embodiment of the present invention, it is determined whether the semiconductor memory device enters the PODTM by the third OP in the third MR, and in the case of entering the PODTM, the test object is selected from the DM and at least one DQ of the data. Then, the impedance of the selected test object is controlled as a first impedance parameter (essentially an increased impedance of the output signal driver) by the first OP in the first MR, and the impedance of the unselected pin is controlled as a second impedance parameter (essentially a termination impedance) by the second OP in the second MR so as to obtain a test result of the impedance of the test object. For the DM, there is no need to add the determination of the state of the output signal driver and the corresponding control circuit for a given test mode to ensure that the given test mode is adapted to the DM, and the impedance of the DM can be checked in the given test mode to avoid data processing errors by the circuit.

[0058] In some embodiments, the default sequence number of the first MR is 5, and the first OP refers to the OP from the second bit to the first bit stored in the first MR, represented as MR5 OP[2:1]. The default sequence number of the second MR is 34, and the second OP refers to the OP from the second bit to ^{the 0th} bit stored in the second MR, represented as MR34 OP[2:0]. The default sequence number of the third MR is 61, and the third OP refers to the OP from the ^4th bit to the ^0th bit stored in the third MR, represented as MR61 OP[4:0]. In this case, the default sequence number refers to the sequence number of the MR in DDR5.

[0059] The third OP MR61 OP[4:0], the first OP MR5 OP[2:1] and the second OP MR34 OP[2:0] are described in detail below with reference to tables 1-3.

[0060] As shown in Table 1, MR61 OP[4:0] is configured to determine whether an input to the PODTM is required and to determine the selected pin. It should be understood that the number of DM and DQ is different for semiconductor memories for different numbers of bits. For a 4-bit (X4) memory device, one DM of the least significant bits (represented as DML) and four DQ of the least significant bits (respectively, designated as DQL0-DQL3) are used. For an 8-bit (X8) memory device, one DM of the least significant bits (represented as DML) and eight DQ of the least significant bits (respectively, designated as DQL0-DQL7) are used. For a 16-bit (X16) memory device, one DM of the least significant bits (represented as DML), one DM of the most significant bits (represented as DMU), eight DQ of the least significant bits (respectively designated as DQL0-DQL8) and eight DQ of the most significant bits (respectively designated as DQU0-DQU8) are used.

[0061] If MR61 OP[4:0] = 00000 _B , it means that the semiconductor memory device is not in the PODTM. If the value of MR61 OP[4:0] is any combination other than 00000 _B in Table 1, it means that the semiconductor memory device is in the PODTM. In particular, if MR61 OP[4:0] = 00001 _B , it means that the test object is the DML. If MR61 OP[4:0] = 00010 _B , it means that the test object is the DMU (valid only for 16-bit memory device). In particular, if MR61 OP[4:0] = 10000 _B , it means that the test object is the DQ of the 0th bit of DQL0. Other parameters can be understood with reference to those described earlier and their explanation may not be given one after another.

Table 1

MR and OP bit Function Parameter Description MR61 OP[4:0] Output Signal Generator Burst Test Mode 00000 _B : Batch test disabled (default)
00001 _B : Batch DML Test
00010 _B : DMU Batch Test (X16 only)
10000 _B : DQL0 Batch Test
10001 _B : DQL1 Batch Test
10010 _B : DQL2 Batch Test
10011 _B : DQL3 Batch Test
10100 _B : DQL4 Batch Test (X8 and X16 only)
10101 _B : DQL5 Batch Test (X8 and X16 only)
10110 _B : DQL6 Batch Test (X8 and X16 only)
10111 _B : DQL7 Batch Test (X8 and X16 only)
11000 _B : DQU0 Burst Test (X16 only)
11001 _B : DQU1 Packet Test (X16 only)
11010 _B : DQU2 Packet Test (X16 only)
11011 _B : DQU3 Packet Test (X16 only)
11100 _B : DQU4 Packet Test (X16 only)
11101 _B : DQU5 Packet Test (X16 only)
11110 _B : DQU6 Packet Test (X16 only)
11111 _B : DQU7 Packet Test (X16 only)

[0062] As shown in Table 2, MR5 OP[2:1] is configured to determine the increased impedance of the DQ output signal generator, thus the impedance of the selected pin is controlled as the first impedance parameter by MR5 OP[2:1] in PODTM.

[0063] If MR5 OP[2:1] = 00 _V , this means that the enhanced impedance of the input signal driver should be equal to RZQ/7, i.e. 34 ohms. If MR5 OP[2:1] = 01 _V , this means that the enhanced impedance of the input signal driver should be equal to RZQ/6, i.e. 40 ohms. If MR5 OP[2:1] = 10 _V , this means that the enhanced impedance of the input signal driver should be equal to RZQ/5, i.e. 48 ohms. In this case, RZQ is equal to the standard resistance value, i.e. 240 ohms.

Table 2

MR and OP bit Function Parameter Description MR5 OP[2:1] Increased impedance of the output signal generator 00 _B : RZQ/7 (34)
01 _B : RZQ/6 (40)
10 _B : RZQ/5 (48)

[0064] As shown in Table 3, MR34 OP[2:0] is configured to determine the impedance of the termination (RTT_PARK) of the DQ or DM, thus the impedance of the selected pin is controlled as a second impedance parameter by MR34 OP[2:0] in PODTM.

[0065] If MR5 OP[2:0] = 001 _V , it means that the termination impedance is RZQ, i.e. 240 Ω. If MR5 OP[2:0] = 010 _V , it means that the termination impedance is RZQ/2, i.e. 120 Ω. Other parameters can be understood with reference to those described earlier and their explanation may not be given one by one.

Table 3

MR and OP bit Function Parameter Description MR34 OP[2:0] RTT_PARK 000 _B : RTT_OFF by default
001 _B : RZQ (240)
010 _B : RZQ/2 (120)
011 _B : RZQ/3 (80)
100 _B : RZQ/4 (60)
101 _B : RZQ/5 (48)
110 _B : RZQ/6 (40)
111 _B : RZQ/7 (34)

[0066] Additionally, the unexplained data in Tables 1-3 can be understood by referring to the DDR5 SPEC.

[0067] As follows from the above, when the DRAM is in the PODTM, the host is configured to independently enable the output driver circuit of one pin in the DRAM and simultaneously control the other pins so that they are in a terminated state, in order to perform a characteristic test on the packaged DRAM. To enable the PODTM, the host selects the DM or DQ as a test target by setting MR61:OP[4:0], and the host also controls the value of the raised impedance of the output driver circuit of the test target so that it is equal to 34 Ω by setting MR5 OP[2:1] = 00 _B . Meanwhile, the impedance state of the remaining DM or DQ in the DRAM is determined as RTT_PARK using MR34 OP[2:0]. It should be noted that using MR5 OP[5], it is determined whether the DM is enabled. Additionally, if DM is selected as the test target in PODTM, the DRAM can set the DM impedance according to MR5 OP[2:1].

[0068] Below, as an example, a specific method of signal processing is presented that allows the mechanism described above to be implemented.

[0069] As shown in Fig. 2, in some embodiments, in the case of determining that the semiconductor memory device enters a specified test mode, the method further includes the following operations.

[0070] In step S201, a first OP is obtained in a first MR, a second OP in a second MR, and a third OP in a third MR.

[0071] In step S202, the third OP is decoded to obtain a first test flag signal. In this case, the first test flag signal indicates whether the DM is a test object.

[0072] In step S203, one of the first OP and the second OP is selected to control the impedance DM in accordance with the first test flag signal.

[0073] In some embodiments, if it is determined that the semiconductor memory device enters a predetermined test mode, after step S201, the method further includes the following operations.

[0074] In step S204, the third OP is decoded to obtain at least one second test flag signal. In this case, the one second test flag signal indicates whether one DQ is a test object.

[0075] In step S205, one of the first OP and the second OP is selected to control the impedance of the corresponding DQ in accordance with the second test flag signal.

[0076] It should be understood that the order of execution of steps S202 and S204 is not determined. In this case, step S203 is executed after step S202, and step S205 is executed after step S204.

[0077] It should be noted that the first test flag signal is an internal flag signal input for the DM to indicate whether the DM is the test object in the PODTM. The second test flag signal is an internal flag signal input for the DQ to indicate whether the DQ is the test object in the PODTM. Both the first test flag signal and the second test flag signal are obtained by decoding MR61 OP[4:0], the details are given in Table 1 above.

[0078] In some embodiments, for DM, the method further includes the following operations.

[0079] A first non-test state control signal and a second impedance control signal are determined.

[0080] When the semiconductor memory device is in a predetermined test mode, the first impedance control signal is determined based on one of the first OP and the second OP in accordance with the first test flag signal. Or, when the semiconductor memory device is not in a predetermined test mode, the first impedance control signal is determined based on the first non-test state control signal.

[0081] One of the first impedance control signal and the second impedance control signal is selected to control the impedance DM in accordance with an operating state of the semiconductor memory device.

[0082] It should be noted that although the functions of DM and DQ are different, the DM and DQ use similar signal control principles and circuit structures for the convenience of industrial production. In particular, each pin can be regarded as having a read-related attribute and a write-related attribute, and the final impedance of each pin is controlled by an effective signal in a signal corresponding to a read-related attribute and in a signal corresponding to a write-related attribute. In this way, each pin respectively supports a read function and a write function in different working scenarios (although the read function for DM is disabled).

[0083] In one case, the first non-test state control signal is configured to indicate the impedance DM in a state other than the specified test state, and the second impedance control signal is configured to indicate the impedance DQ in the state of the output signal generator. In this case, the impedance DM in a state other than the specified test state may include an impedance during a normal write operation and an impedance when no write or read operations are performed, each of which relates to an attribute related to the recording.

[0084] Here, the first non-test state control signal can be understood as a signal corresponding to an attribute related to recording, and the second impedance control signal can be understood as a signal corresponding to an attribute related to reading. Thus, in the PODTM, the first impedance control signal corresponding to the PODTM is determined in accordance with one of the first OP or the second OP. Or, in a mode other than the PODTM, the first impedance control signal corresponding to an attribute related to recording is determined in accordance with the first non-test state control signal. Then, according to the operating state of the semiconductor memory device, the impedance DM is controlled using the PODTM or the first impedance control signal corresponding to the attribute related to recording or the second impedance control signal corresponding to the attribute related to reading. In particular, the operating states of the semiconductor memory device may include a write state, a read state, a non-read and non-write state, and a specified test mode (PODTM). In this case, (1) when the semiconductor memory device is in the write state, or in the non-read and non-write state, or in the specified test mode, the impedance DM is controlled using the first impedance control signal. (2) When the semiconductor memory device is in the read state, the impedance DM is controlled using the second impedance control signal.

[0085] Thus, by combining the DM signal control strategy in PODTM with the signal control strategy for the entry-related attribute, impedance control is implemented in PODTM.

[0086] In yet another case, the first non-test state control signal is configured to indicate the impedance DQ in the state of the output signal generator, and the second impedance control signal is configured to indicate the impedance DM in a state other than the specified test state.

[0087] Here, the first non-test state control signal can be understood as a signal corresponding to an attribute related to reading, and the second impedance control signal can be understood as a signal corresponding to an attribute related to writing. Thus, in the PODTM, the first impedance control signal corresponding to the PODTM is determined in accordance with one of the first OP or the second OP. Or, in a mode other than the PODTM, the first impedance control signal corresponding to an attribute related to reading is determined in accordance with the first non-test state control signal. Then, according to the operating state of the semiconductor memory device, the impedance DM is controlled using the PODTM or the first impedance control signal corresponding to the attribute related to reading or the second impedance control signal corresponding to the attribute related to writing. In particular, the operating states of the semiconductor memory device may include a write state, a read state, a non-read and non-write state, and a specified test mode (PODTM). In this case, (1) when the semiconductor memory device is in the write state or in the non-read and non-write state, the impedance DM is controlled using the second impedance control signal. (2) When the semiconductor memory device is in the read state or in the specified test mode, the impedance DM is controlled using the first impedance control signal.

[0088] Thus, by combining the DM signal control strategy in PODTM with the signal control strategy for the read-related attribute, impedance control is implemented in PODTM.

[0089] Similarly, a specific signal control method for DQ is given below as an example.

[0090] In some embodiments, for DQ, the method further includes the following steps.

[0091] A third non-test state control signal, a fourth impedance control signal, and a fifth impedance control signal are determined.

[0092] When the semiconductor memory device is in a predetermined test mode, the third impedance control signal is determined based on one of the first OP and the second OP in accordance with the second test flag signal. Or, when the semiconductor memory device is not in a predetermined test mode, the third impedance control signal is determined based on the third non-test state control signal.

[0093] The third impedance control signal and the fifth impedance control signal are selected to control the impedance DQ in accordance with the operating state of the semiconductor memory device, or the fourth impedance control signal and the fifth impedance control signal are selected to control the impedance DQ.

[0094] Thus, in one case, the third non-test state control signal is configured to indicate the impedance of the corresponding DQ in the termination state, and the fourth impedance control signal and the fifth impedance control signal are together configured to indicate the impedance of the corresponding DQ in the output signal generator state. In particular, the operating states of the semiconductor memory device may include a write state, a read state, a non-read and non-write state, and a specified test mode (PODTM). In this case, (1) when the semiconductor memory device is in the write state, or in the non-read and non-write state, or in the specified test mode, the impedance of the DQ is controlled using the second impedance control signal. (2) When the semiconductor memory device is in the read state, the impedance of the DQ is controlled using the fourth impedance control signal and the fifth impedance control signal.

[0095] Thus, by combining the DQ signal control strategy in PODTM with the signal control strategy for the entry-related attribute, impedance control is implemented in PODTM.

[0096] In another case, the third non-test state control signal and the fifth impedance control signal are together configured to indicate the impedance of the corresponding DQ in the output signal generator state, and the fourth impedance control signal is configured to indicate the impedance of the corresponding DQ in the termination state. In particular, the operating states of the semiconductor memory device may include a write state, a read state, a non-read and non-write state, and a specified test mode (PODTM). In this case, (1) when the semiconductor memory device is in the write state or in the non-read and non-write state, the impedance of the DQ is controlled using the fourth impedance control signal and the fifth impedance control signal. (2) When the semiconductor memory device is in the read state or the specified test state, the impedance of the DQ is controlled using the third impedance control signal and the fifth impedance control signal.

[0097] Thus, by combining the DQ signal control strategy in PODTM with the signal control strategy for the read-related attribute, impedance control is implemented in PODTM.

[0098] It should be understood that the write function includes only the high impedance control (as the termination impedance), and the read function includes both the high impedance and the low impedance control. Since only the write function is allowed for DM, but not the read function, only the high impedance control signal is used for DM, and the low impedance control signal of DM will be defined as a fixed level signal to disable the low impedance function. In addition, since DQ supports both the write function and the read function, DQ can work with the high impedance control signal and the low impedance control signal.

[0099] Thus, the attribute DM related to reading includes only one signal (the first non-test state control signal or the second impedance control signal), which is configured to control the increased impedance. The attribute DQ related to reading includes two signals (the third non-test state control signal and the fifth impedance control signal or the fourth impedance control signal and the fifth impedance control signal), which respectively control the increased impedance and the reduced impedance.

[00100] In embodiments of the present invention, a control method is provided. When the semiconductor memory device is in a given test mode, the first MR and the second MR related to the DQ are configured to directly determine the impedance of the DM. For the DM, there is no need to add the determination of the state of the output signal generator and the corresponding control circuit for the given test mode in order to ensure the adaptation of the given test mode to the DM. The impedance of the DM can be tested in the given test mode to prevent data processing errors by the circuit.

[00101] In one embodiment of the present invention, with reference to FIG. 3, a schematic block diagram of a semiconductor memory device 30 according to one embodiment of the present invention is shown. As shown in FIG. 3, the semiconductor memory device 30 includes a first MR 301, a second MR 302, a DM 310, and a first driver circuit 311, wherein the first driver circuit 311 is connected, respectively, to the first MR 301, the second MR 302, and the DM 310.

[00102] DM 310 is configured to receive a recording data input mask signal.

[00103] The first driver circuit 311 is configured to, when the semiconductor memory device 30 is in a given test mode, control, in response to the selection of the DM 310 as the test object, the impedance of the DM 310 as the first impedance parameter using the first MR 301, or control, in response to the DM 310 being selected as the test object, the impedance of the DM 310 as the second impedance parameter using the second MR 302.

[00104] In this case, the semiconductor memory device 30 further includes at least one DQ, which is configured to receive or output data, wherein the first MR 301 is configured to indicate that the impedance of at least one DQ in the output signal generator state is a first impedance parameter, and the second MR 302 is configured to indicate that the impedance of at least one DQ in the termination state is a second impedance parameter.

[00105] Thus, when the semiconductor memory device 30 is in a given test mode, the first MR 301 and the second MR 302 are configured to directly determine the impedance of the DM 310. For the DM 310, there is no need to add a determination of the state of the output signal generator and the corresponding control circuit for the given test mode in order to ensure that the given test mode is adapted to the DM 310. The impedance of the DM 310 can be tested in a given test mode to prevent data processing errors by the circuit.

[00106] In some embodiments, as shown in Fig. 4A, the semiconductor memory device 30 further includes at least one second driver circuit 321 and each second driver circuit 321 is connected to the first MR 301, the second MR 302 and one DQ 320.

[00107] The second driver circuit 321 is configured to, when the semiconductor memory device 30 is in a given test mode, control, in response to the selection of the corresponding DQ 320 as the test object, the impedance of the DQ 320 as the first impedance parameter by means of the first MR 301; or control, in response to the fact that the DQ 320 is not selected as the test object, the impedance of the DQ 320 as the second impedance parameter by means of the second MR 302.

[00108] It should be understood that in Fig. 4A only one DQ 320 is shown for illustration, and in the semiconductor memory device 30 there are actually more DQs. Embodiments of the present invention do not limit the number of DM 310 and DQ 320.

[00109] It should be noted that the specified test mode may be a PODTM, which allows the host to test increased DM or DQ impedance.

[00110] In some embodiments, as shown in Fig. 4B, the semiconductor memory device 30 further includes a third MR 303 and a first decoding module 304.

[00111] The first MR 301 is configured to store and output a first operand (OP).

[00112] The second MR 302 is configured to store and output the second OP.

[00113] The third MR 303 is configured to store and output a third OP. In this case, the third OP is configured to indicate whether the semiconductor memory device 30 has entered a specified test mode.

[00114] The first decoding module 304 is configured to receive the third OP, decode the third OP, and output a first test flag signal. In this case, the first test flag signal is configured to indicate whether the DM 310 is an object of testing.

[00115] The first driver circuit 311 is further configured to receive a first test flag signal, a first OP and a second OP; and to select, in accordance with the first test flag signal, one of the first OP and the second OP for controlling the impedance of the DM 310 in the event that the semiconductor memory device 30 enters a specified test mode.

[00116] In some embodiments, as shown in Fig. 4B, the first decoding module 304 is further configured to decode the third OP and output at least one second test flag signal. In this case, the one second test flag signal is configured to indicate whether one DQ is a test object.

[00117] The second driver circuit 321 is further configured to receive a corresponding second test flag signal, the first OP and the second OP; and to select, in accordance with the second test flag signal, one of the first OP and the second OP for controlling the impedance of the DQ 320 in the event that the semiconductor memory device 30 enters a specified test mode.

[00118] It should be noted that the first test flag signal is an internal flag signal inputted for the DM 310 to indicate whether the DM 310 is an object of testing in the PODTM. The second test flag signal is an internal flag signal inputted for the DQ 320 to indicate whether the DQ 320 is an object of testing in the PODTM. Both the first test flag signal and the second test flag signal are obtained by decoding in accordance with the third OP.

[00119] Thus, in an embodiment of the present invention, it is determined whether the semiconductor memory device 30 enters the PODTM by means of the third OP in the third MR, and in the case of entering the PODTM, the test object is selected from the DM and at least one DQ of data. Then, the impedance of the selected test object is controlled as a first impedance parameter (essentially an increased impedance of the output signal generator) by means of the first OP in the first MR, and the impedance of the non-selected test object is controlled as a second impedance parameter (essentially a termination impedance) by means of the second OP in the second MR so as to obtain a test result of the impedance of the test object. For the DM, there is no need to add the determination of the state of the output signal generator and the corresponding control circuit for a given test mode in order to ensure that the given test mode is adapted to the DM. The impedance of the DM can be tested in a given test mode in order to prevent the occurrence of data processing errors by the circuit.

[00120] It should be noted that the standard sequence number of the first MR is 5, and the first OP refers to the OP from the second bit to the first bit stored in the first MR, represented as MR5 OP[2:1]. The standard sequence number of the second MR is 34, and the second OP refers to the OP from the second bit to ^{the 0th} bit stored in the second MR, represented as MR34 OP[2:0]. The standard sequence number of the third MR is 61, and the third OP refers to the OP from the ^4th bit to the ^0th bit stored in the third MR, represented as MR61 OP[4:0].

[00121] As shown in Fig. 5, taking the 8-bit (X8) semiconductor memory device 30 as an example, the first decoding module 304 is configured to receive the third OP MR61 OP[4:0] and decode it to obtain a first test flag signal PODTM_DM_EN, a second test flag signal PODTM_DQ0_EN-PODTM_DQ7_EN. In this case, the second test flag signal PODTM_DQ0_EN-PODTM_DQ7_EN is configured to indicate whether DQ0L0-DQL7 DQ are test objects in the PODTM. It should be understood that the logic circuit in the first decoding module 304 is configured in accordance with the above-mentioned Table 1.

[00122] A detailed description of the structure of the first driver circuit 311 is given below as an example.

[00123] In an embodiment of the present invention, the semiconductor memory device 30 is further configured to determine a first non-test state control signal, a second impedance control signal, and a first calibration signal ZQ1_CODE[N-1:0].

[00124] As shown in Fig. 6, the first driver circuit 311 may include a first signal processing module 41, a first logic module 42, and a first driver module 43.

[00125] The first signal processing module 41 is configured to receive the first test flag signal PODTM_DM_EN, the first OP MR5 OP[2:1], the second OP MR34 OP[2:0] and the first non-test state control signal; and output, based on one of the first OP MR5 OP[2:1] and the second OP MR34 OP[2:0], the first impedance control signal in accordance with the first test flag signal PODTM_DM_EN when the semiconductor memory device 30 is in a predetermined test state; or output, based on the first non-test state control signal, the first impedance control signal when the semiconductor memory device 30 is not in a predetermined test mode.

[00126] The first logic module 42 is configured to receive the first impedance control signal, the second impedance control signal and the first calibration signal ZQ1_CODE[N-1:0]; and also select and logically combine the first impedance control signal, the second impedance control signal and the first calibration signal ZQ1_CODE[N-1:0] to output the first target signal PU1_MAIN_CODE.

[00127] The first module 43 of the generator includes a plurality of first impedance blocks, and is also configured to receive the first target signal PU1_MAIN_CODE and control the plurality of first impedance blocks using the first target signal PU1_MAIN_CODE so as to control the impedance of the DM 310.

[00128] It should be understood that the DM 310 only supports the recording function and does not need to output data. In the termination state, only the level-up function is supported, but not the level-down function, so that the first driver circuit 311 has only the first impedance control signal and the second impedance control signal, which are configured to control the level-up function, but do not include signals related to the level-down function control. In addition, the increased resistance value of each first impedance block may be a standard resistance value. However, when environmental parameters such as temperature and voltage in the actual working environment change, the resistance value of the first impedance block may also change accordingly. Thus, the first calibration signal ZQ1_CODE[N-1:0] is configured to calibrate the resistance value of each first impedance block to the standard resistance value. In this case, all of the first impedance blocks share the first calibration signal ZQ1_CODE[N-1:0].

[00129] It should be noted that the first impedance control signal and the second impedance control signal respectively correspond to two attributes, i.e., an attribute related to writing and an attribute related to reading. It should be understood that, in a mode other than PODTM corresponding to an actual operating state, one of the first impedance control signal and the second impedance control signal is valid, which is combined with the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE. In addition, in the PODTM mode, the second impedance control signal is invalid, and the first impedance control signal is combined with the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE. In this case, the actual signal in the first impedance control signal and the second impedance control signal is configured to enable or disable the function of increasing the level of the first impedance block, and the first calibration signal ZQ1_CODE[N-1:0] is configured to calibrate the resistance value of the first impedance block to a standard resistance value when the function of increasing the level of the first impedance block is enabled.

[00130] In some embodiments, as shown in Fig. 6, the first signal processing module 41 includes a second decoding module 411, a third decoding module 412, a first selecting module 413, and a second selecting module 414.

[00131] The second decoding module 411 is configured to receive the first OP MR5 OP[2:1], decode the first OP MR5 OP[2:1], and output the first decoded signal RONpu_CODE[M:0].

[00132] The third decoding module 412 is configured to receive the second OP MR34 OP[2:0], decode the second OP MR34 OP[2:0], and output the second decoded signal RTT_CODE[M:0].

[00133] The first selecting module 413 is configured to receive the first test flag signal PODTM_DM_EN, the first decoded signal RONpu_CODE[M:0] and the second decoded signal RTT_CODE[M:0]; and select one of the first decoded signal RONpu_CODE[M:0] and the second decoded signal RTT_CODE[M:0] to output the first test state control signal in accordance with the first test flag signal PODTM_DM_EN.

[00134] The second selecting module 414 is configured to receive the test enable signal PODTM_EN, the first test state control signal and the first non-test state control signal; and to select one of the first test state control signal and the first non-test state control signal to output the first impedance control signal in accordance with the test enable signal PODTM_EN.

[00135] It should be understood that the logic circuit in the second decoding module 411 is configured in accordance with the above-mentioned table 2, that is, the first decoded signal is configured to represent the resistance value (the first impedance parameter) of the impedance Ron of the driver, and the logic circuit in the third decoding module 412 is configured in accordance with the above-mentioned table 3, that is, the second decoded signal is configured to represent the resistance value (the second impedance parameter) of the termination impedance RTT. In addition, M is a positive integer, and its specific value must be determined in accordance with the actual working scenario.

[00136] It should be noted that the test enable signal PODTM_EN is configured to indicate whether the semiconductor memory device is in the specified PODTM test mode and whether decoding has been performed in accordance with the third control code MR61 OP[4:0]. As shown in Table 1 above, when the value of MR61 OP[4:0] is in other combination forms other than 00000B in Table 1, this indicates that the semiconductor memory device is in the specified PODTM test mode, and the test enable signal PODTM_EN is in the first level state (for example, logical "1"). When MR61 OP[4:0] = 00000B, this indicates that the semiconductor memory device is not in the specified PODTM test mode and the test enable signal PODTM_EN is in the second level state (for example, logical "0"). In addition, it should be understood that if one of the first test flag signal or the second test flag signal is in the first level state, the test enable signal PODTM_EN is in the first level state. Both the first test flag signal and the second test flag signal are in the second level state, and the test enable signal PODTM_EN is in the second level state.

[00137] For the first driver circuit 311 shown in Fig. 6, in accordance with different definitions of the first non-test state control signal and the second impedance control signal, two specific embodiments of the mode can be applied.

[00138] In one embodiment of the mode, the first non-test state control signal is configured to indicate the impedance DM in a state different from the specified test state, and the second impedance control signal is configured to indicate the impedance DQ in the state of the output signal generator. In other words, by combining the DM signal control strategy in the PODTM with the signal control strategy for the attribute related to the record, impedance control is implemented in the PODTM.

[00139] Accordingly, as shown in Fig. 7, the first impedance control signal is represented as ODT_MUX[M:0], and the second impedance control signal is represented as IMPpu_CODE[M:0]. In particular, compared with Fig. 6, the first driver circuit 311 in Fig. 7 further includes a first pre-processing module 44 and a second pre-processing module 45. The first pre-processing module 44 is configured to decode the first OP MR5 OP[2:1] to obtain the second impedance control signal IMPpu_CODE[M:0]. The second pre-processing module 45 is configured to determine the first non-test state control signal according to MR34[5:3] including RTT_WR, MR35[2:0] including RTT_NOM_WR, MR35[5:3] including RTT_NOM_RD, MR34[2:0] including RTT_PARK, and MR33[5:3] including DQS_RTT_PARK. The specific values of the above signals relate to the DDR5 SPEC regulation, and the signals in this part do not affect the implementation of undisclosed embodiments that will not be described in detail. In addition, in the following description, if the semiconductor memory device 30 is in the PODTM, the test enable signal PODTM_EN is equal to a logical "1". If the semiconductor memory device 30 is not in the PODTM, the test enable signal PODTM_EN is equal to a logical "0". If the DM 310 is a PODTM test object, the first signal PODTM_DM_EN of the test flag is equal to a logical "1". If the DM 310 is not a PODTM test object, the first signal PODTM_DM_EN of the test flag is equal to a logical "0".

[00140] The operating principle shown in Fig. 7 is explained below in three operating scenarios.

[00141] In the operation scenario 1, the semiconductor memory device 30 is included in the PODTM, and the DM 310 is the test object. At this time, since the first test flag signal PODTM_DM_EN is a logic "1", the first selection module 413 outputs the first decoded signal RONpu_CODE[M:0] to obtain the first test state control signal. Since the test enable signal PODTM_EN is a logic "1", the second selection module 414 outputs the first test state control signal determined by the first selection module 413 to obtain the first impedance control signal ODT_MUX[M:0]. As described earlier, the second impedance control signal IMPpu_CODE[M:0] in the PODTM is invalid, so that the first logic module 42 essentially logically combines the first impedance control signal ODT_MUX[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thus controlling the impedance of the DM 310. In this case, the invalidation of the second impedance control signal IMPpu_CODE[M:0] can be ensured in at least two ways, namely by adding a corresponding logic element for blocking the signal to the first pre-processing module 44 or by adding a corresponding logic element for blocking the signal to the first logic module 42.

[00142] As follows from the above, in operating scenario 1, the impedance of DM 310 is essentially controlled by the first OP MR5 OP[2:1].

[00143] In the operation scenario 2, the semiconductor memory device 30 is included in the PODTM, and the DM 310 is not an object of testing. At this time, since the first test flag signal PODTM_DM_EN is a logic "0", the first selection module 413 outputs the second decoded signal RTT_CODE[M:0] to obtain the first test state control signal. Since the test enable signal PODTM_EN is a logic "1", the second selection module 414 outputs the first test state control signal determined by the first selection module 413 to obtain the first impedance control signal ODT_MUX[M:0]. As described previously, the second impedance control signal IMPpu_CODE[M:0] in PODTM is invalid, so that the first logic module 42 essentially logically combines the first impedance control signal ODT_MUX[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of DM 310.

[00144] As follows from the above, in operating scenario 2, the impedance of DM 310 is essentially controlled by the second OP MR34 OP[2:0].

[00145] In the operation scenario 3, the semiconductor memory device 30 is not included in the PODTM. At this time, since the first test flag signal PODTM_DM_EN is a logic "0", the second selection module 414 outputs the first test state control signal determined by the second pre-processing module 45 to obtain the first impedance control signal ODT_MUX[M:0]. At this time, the first pre-processing module 44 outputs the second impedance control signal IMPpu_CODE[M:0]. Since the DM 310 only supports the recording function, the second impedance control signal IMPpu_CODE[M:0] in the mode other than PODTM is invalid, and the first impedance control signal ODT_MUX[M:0] is valid, so that the first logic module 42 combines the first impedance control signal ODT_MUX[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the DM 310.

[00146] As follows from the above, in the operating scenario 3, the impedance of the DM 310 is essentially controlled by the second pre-processing module 45 depending on the actual operating state.

[00147] In another embodiment of the mode, the first non-test state control signal is configured to indicate the impedance DQ in the state of the output signal generator, and the second impedance control signal is configured to indicate the impedance DM in a state different from the specified test state. In other words, by combining the DR signal control strategy in the PODTM with the signal control strategy for the attribute related to reading, impedance control is implemented in the PODTM.

[00148] Accordingly, as shown in Fig. 8, the first impedance control signal is represented as IMPpu_CODE[M:0], and the second impedance control signal is represented as ODT_CTRL[M:0]. In particular, compared with Fig. 6, the semiconductor memory device 30 in Fig. 8 also includes a first pre-processing module 44 and a second pre-processing module 45. The first pre-processing module 44 is configured to decode the first OP MR5 OP[2:1] to obtain the first non-test state control signal. The second pre-processing module 45 is configured to determine the second non-test state control signal in accordance with MR34[5:3] including RTT_WR, MR35[2:0] including RTT_NOM_WR, MR35[5:3] including RTT_NOM_RD, MR34[2:0] including RTT_PARK, and MR33[5:3] including DQS_RTT_PARK.

[00149] Similarly, the operating principle shown in Fig. 8 is explained below in three operating scenarios.

[00150] In the operation scenario 1, the semiconductor memory device 30 is included in the PODTM, and the DM 310 is the test object. At this time, since the first test flag signal PODTM_DM_EN is a logic "1", the first selection module 413 outputs the first decoded signal RONpu_CODE[M:0] to obtain the first test state control signal. Since the test enable signal PODTM_EN is a logic "1", the second selection module 414 outputs the first test state control signal determined by the first selection module 413 to obtain the first impedance control signal IMPpu_CODE[M:0]. As described previously, the second impedance control signal ODT_CTRL[M:0] in PODTM is invalid, so that the first logic module 42 essentially logically combines the first impedance control signal IMPpu_CODE[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of DM 310.

[00151] Thus, in operating scenario 1, the impedance of DM 310 is also controlled via the first OP MR5 OP[2:1].

[00152] In the operation scenario 2, the semiconductor memory device 30 is included in the PODTM, and the DM 310 is not an object of testing. At this time, since the first test flag signal PODTM_DM_EN is a logic "0", the first selection module 413 outputs the second decoded signal RTT_CODE[M:0] to obtain the first test state control signal. Since the test enable signal PODTM_EN is a logic "1", the second selection module 414 outputs the first test state control signal determined by the first selection module 413 to obtain the first impedance control signal IMPpu_CODE[M:0]. As described previously, the second impedance control signal ODT_CTRL in PODTM is invalid, so that the first logic module 42 essentially logically combines the first impedance control signal IMPpu_CODE[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of DM 310.

[00153] Thus, in operating scenario 2, the impedance of DM 310 is also controlled by the second MR34 OP[2:0].

[00154] In the operation scenario 3, the semiconductor memory device 30 is not included in the PODTM. At this time, since the first test flag signal PODTM_EN is a logic "0", the second selection module 414 outputs the first non-test state control signal determined by the first pre-processing module 44 to obtain the first impedance control signal IMPpu_CODE[M:0]. At this time, the second pre-processing module 45 outputs the second impedance control signal ODT_CTRL[M:0]. Since the DM only supports the recording function, the first impedance control signal IMPpu_CODE[M:0] in the mode other than PODTM is invalid, and the second impedance control signal ODT_CTRL[M:0] is valid, so that the first logic module 42 combines the second impedance control signal ODT_CTRL[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the DM 310.

[00155] Thus, in operating scenario 3, the impedance of DM 310 is also controlled by the second pre-processing module 45 depending on the actual operating state.

[00156] In addition, it should be noted that in Fig. 7 and Fig. 8, the symbol "/" marked on the signal path indicates that there are actually multiple signal paths and only one of them is shown for illustration. In other words, each signal of MR34 OP[2:0], MR5 OP[2:1], RONpu_CODE[M:0], RTT_CODE[M:0], IMPpu_CODE[M:0], ZQ1_CODE[N-1:0], ODT_CTRL[M:0], ODT_MUX[M:0] and PU1_MAIN_CODE includes a plurality of sub-signals, and each sub-signal has its own signal path.

[00157] The signal processing process in the first driver circuit 311 will be described below with reference to Fig. 7 or Fig. 8.

[00158] In some embodiments, as shown in Fig. 7 or Fig. 8, each of the first decoded signal RONpu_CODE[M:0], the second decoded signal RTT_CODE[M:0], the first test state control signal, the first non-test state control signal, and the first impedance control signal includes (M+1) subsignal bits represented as [M:0]. The first selecting module 413 includes (M+1) first data selectors, and the second selecting module 414 includes (M+1) second data selectors. In this case, the input of one of the first data selectors, respectively, receives a 1-bit subsignal of the first decoded signal RONpu_CODE[M:0] and a 1-bit subsignal of the second decoded signal RTT_CODE[M:0], wherein the output of one of the first data selectors is configured to output a 1-bit subsignal of the first test state control signal, and the ends on the control side of all the first data selectors receive the first test flag signal PODTM_DM_EN. The input of one of the second data selectors receives a 1-bit subsignal of the first test state control signal and a 1-bit subsignal of the first non-test state control signal, wherein the output of one of the second data selectors is configured to output a 1-bit subsignal of the first impedance control signal, and the ends on the control side of all the second data selectors receive a test enable signal. In this case, M is a positive integer.

[00159] It should be noted that the first test state control signal is represented as the first test state control signal [M:0], the first non-test state control signal is represented as the first non-test state control signal [M:0], and the first impedance control signal is represented as the first impedance control signal [M:0]. Thus, the first of the first data selectors receives RONpu_CODE[0], RTT_CODE[0], and PODTM_DM_EN, respectively, and selects one of RONpu_CODE[0] and RTT_CODE[0] to output the first test state control signal [0] in accordance with PODTM_DM_EN. The first of the second data selectors respectively receives the first test state control signal [0], the first non-test state control signal [0] and PODTM_EN, and selects one of the first test state control signal [0] and the first non-test state control signal [0] to output the first impedance control signal [0] in accordance with PODTM_EN. Other data can be understood with reference to the above information.

[00160] In some embodiments, the second impedance control signal includes (M+1) sub-signal bits, and the first calibration signal ZQ1_CODE[N-1:0] includes N sub-signal bits. The first target signal includes A groups of sub-signals, and each group of sub-signals includes N sub-signal bits. The first group of signals in the first target signal is represented as PU1_MAIN_CODE_1[N-1:0], the second group of signals in the first target signal is represented as P PU1_MAIN_CODE_2[N-1:0], and A groups of signals in the first target signal are represented as PU1_MAIN_CODE_A[N-1:0].

[00161] The first driver module 43 includes A first impedance blocks, and each first impedance block is configured to receive a group of sub-signals in the first target signal PU1_MAIN_CODE. In this case, as shown in Fig. 7 or Fig. 8, the first logic module 42 is specifically configured to determine whether a level increase function of at least one first impedance block is enabled, according to the first impedance control signal and the second impedance control signal; and to determine, in a case where the level increase function of the a ^th first impedance block is enabled, a level state of the a ^th group of sub-signals in the first target signal PU1_MAIN_CODE according to the first calibration signal so as to control a resistance value of the a ^th first impedance block to correspond to a standard resistance value; or determining that, in the case where the level-up function of the a ^th first impedance block is disabled, the a ^th sub-signal group in the first target signal PU1_MAIN_CODE is in the first level state. In this case, all of a, N, and A are integers, a is less than or equal to A, and (M+1) is less than or equal to A.

[00162] It should be understood that the plurality of first impedance blocks are in a parallel state and each first impedance block can provide a standard value of resistance RZQ. Thus, if the increased impedance of the DM 310 is to be set to RZQ/2, the functions of increasing the level of two first impedance blocks are enabled, and the functions of increasing the level of the remaining first impedance blocks are prohibited. If the increased impedance of the DM 310 is to be set to RZQ/3, the functions of increasing the level of three first impedance blocks are enabled, and the functions of increasing the level of the remaining first impedance blocks are prohibited. Other situations can be understood with reference to those described earlier.

[00163] It should be understood that for the first logic module 42 there is only one valid signal between the first impedance control signal and the second impedance control signal. In the case where M + 1 ≤ A, using a 1-bit subsignal in the valid signal, it is controlled whether the function of increasing the level of one or more first impedance blocks is enabled.

[00164] Thus, for example, in the case where M + 1 = A = 7, if we assume that the actual signal in the first impedance control signal and the second impedance control signal is IMPpu_CODE[6:0], then IMPpu_CODE[0] controls the first impedance control signal, IMPpu_CODE[1] controls the second first impedance block …… IMPpu_CODE[6] controls the seventh first impedance block. In particular, if we assume that IMPpu_CODE[6:0]=1111111, the level values for each group of subsignals (seven groups in total) in the first target signal coincide with the level value of the first calibration signal, so that the increased resistance values of all seven first impedance blocks are equal to RZQ, and the increased resistance of DM 310 is equal to RZQ/7. Assuming that IMPpu_CODE[6:0]=1111000, the level values for the sub-signal groups from the first sub-signal group to the third sub-signal group in the first target signal are in the first level state, and all the level values for each sub-signal group in the sub-signal groups from the fourth sub-signal group to the seventh sub-signal group are respectively the same as the level value of the first calibration signal, so that all the impedance blocks from the first impedance block to the third first impedance block are disconnected. All the increased resistance values for the impedance blocks from the fourth first impedance block to the seventh first impedance block are equal to RZQ, so that the increased impedance of DM 310 is equal to RZQ/4. Other situations can be understood with reference to those described earlier.

[00165] For example, in the case where M + 1 = 4 and A = 7, if it is assumed that the actual signal in the first impedance control signal and the second impedance control signal is the IMPpu_CODE[3:0] signal, IMPpu_CODE[0] controls the first first impedance control signal, IMPpu_CODE[1] controls the second first impedance block and the third first impedance block, IMPpu_CODE[2] controls the fourth first impedance block and the fifth impedance block, and IMPpu_CODE[3] controls the sixth first impedance block and the seventh impedance block. In particular, assuming that IMPpu_CODE[3:0]=1111, the level values for each sub-signal group in the first target signal are the same as the level value of the first calibration signal, so that the increased resistance values of all seven first impedance blocks are equal to RZQ, and the increased resistance of DM 310 is equal to RZQ/7. Assume that IMPpu_CODE[3:0]=1100, the level values for the sub-signal groups from the first sub-signal group to the third sub-signal group in the first target signal are in the first level state, and all the level values for each sub-signal group in the sub-signal groups from the fourth sub-signal group to the seventh sub-signal group are respectively the same as the level value of the first calibration signal, so that all the impedance blocks from the first impedance block to the third first impedance block are turned off. All increased resistance values for the impedance blocks from the fourth first impedance block to the seventh first impedance block are equal to RZQ, so that the increased impedance of DM 310 is equal to RZQ/4. Other situations can be understood with reference to those described earlier.

[00166] Based on this, it can be concluded that if the function of increasing the level of a certain first impedance block is permitted, the increased resistance value of the first impedance block is calibrated to a standard resistance value using a first calibration signal, otherwise, if the function of increasing the level of the first impedance block is prohibited, the corresponding circuit of the first impedance block is turned off using a fixed signal in the first level state.

[00167] In some embodiments, as shown in Fig. 7 or Fig. 8, each first impedance block includes N first switching transistors (e.g., first switching transistor 431 in Fig. 7 or Fig. 8), N second switching transistors (e.g., second switching transistor 432 in Fig. 7 or Fig. 8), and 2N first resistors (e.g., first resistor 433 in Fig. 7 or Fig. 8). The control-side end of ^{the nth} first switching transistor in the ^ath first impedance block is connected to the ^nth subsignal in the ^ath group of subsignals in the first target signal, the first end of one of the first switching transistors is connected to the first end of one of the first resistors, and the second end of one of the first switching transistors is connected to the power signal. The end on the control side of one of the second switching transistors is connected to the ground signal VSS, the first end of one of the second switching transistors is connected to the ground signal VSS, the second end of one of the second switching transistors is connected to the first end of one of the first resistors, and all the second ends of the 2N first resistors are connected to DM. In this case, n is less than or equal to N. In particular, the signal connected to the end on the control side of the second switching transistor must be determined in accordance with a specific circuit logic and is mainly designed to control the second switching transistor so that it is in an off state.

[00168] It should be noted that, taking the first impedance unit shown in Fig. 7 or Fig. 8 as an example, the first impedance unit is configured to receive a first group of sub-signals PU1_MAIN_CODE_1[N-1:0] in the first target signal. PU1_MAIN_CODE_1[N-1:0] includes N sub-signals PU1_MAIN_CODE_1[0], from PU1_MAIN_CODE_1[1] to PU1_MAIN_CODE_1[N-1]. Each sub-signal is configured to control an operating state of one of the first switching transistors respectively so as to control the first impedance unit to perform the level-up function using a standard resistance value or not to perform the level-up function.

[00169] In addition, in Fig. 7 or Fig. 8, three first switching transistors (only one first switching transistor 431 is numbered), three second switching transistors (only one second switching transistor 432 is numbered), and six first resistors (only one first resistor 433 is numbered) are shown in the first impedance block, but in actual scenarios, the number of first switching transistors/second switching transistors/first resistors may be greater or less.

[00170] It should be understood that the DM 310 only supports the data write function and provides the termination impedance, so that there is no need to perform the pull-down function. Therefore, the first ends of all the second switching transistors are connected to the ground signal VSS, i.e., all the second switching transistors are turned off.

[00171] A detailed description of the structure of the second driver circuit 321 is given below as an example. It should be understood that although some signals in the second driver circuit 321 and some signals in the first driver circuit 311 have different names, the source electrodes and waveforms are basically the same, so the same names in English are used.

[00172] In an embodiment of the present invention, the semiconductor memory device 30 is further configured to determine a third non-test state control signal, a fourth impedance control signal, a fifth impedance control signal, a second calibration signal ZQ2_CODE[N-1:0] and a third calibration signal ZQ3_CODE[N-1:0].

[00173] As shown in Fig. 9, the second driver circuit 321 may include a second signal processing module 51, a second logic module 521, a third logic module 522, and a second driver module 53.

[00174] The second signal processing module 51 is configured to receive the second test flag signal PODTM_DQ_EN (for example, the above-mentioned PODTM_DQ0_EN or PODTM_DQ1_EN …… or PODTM_DQ7_EN), the first OP MR5 OP[2:1], the second OP MR34 OP[2:0] and the third non-test state control signal; and output, based on one of the first OP MR5 OP[2:1] and the second OP MR34 OP[2:0], the third impedance control signal in accordance with the second test flag signal PODTM_DQ_EN when the semiconductor memory device 30 is in a predetermined test state; or output, based on the third non-test state control signal, the third impedance control signal when the semiconductor memory device 30 is not in a predetermined test mode.

[00175] The second logic module 521 is configured to receive the third impedance control signal, the fourth impedance control signal and the second calibration signal ZQ2_CODE[N-1:0]; and also select and logically combine the fourth impedance control signal and the second calibration signal ZQ2_CODE[N-1:0] to output the second target signal PU2_MAIN_CODE.

[00176] The third logic module 522 is configured to receive the fifth impedance control signal and the third calibration signal ZQ3_CODE[N-1:0]; and to logically combine the fifth impedance control signal and the third calibration signal ZQ3_CODE[N-1:0] to output the third target signal PD_MAIN_CODE.

[00177] The second module 53 of the generator includes a plurality of second impedance blocks and is configured to receive the second target signal PU2_MAIN_CODE and the third target signal PD_MAIN_CODE; and to control the plurality of second impedance blocks using the second target signal PU2_MAIN_CODE and the third target signal PD_MAIN_CODE to control the impedance of the corresponding DM 320.

[00178] It should be noted that each DQ 320 corresponds to a corresponding second driver circuit 321, and in the embodiment of the present invention, only one second driver circuit 321 is used as an example for explanation.

[00179] It should be understood that the DQ 320 supports a write function and a read function, and includes both a level-up function and a level-down function. Therefore, there is not only a third impedance control signal that is configured to control the level-up function in the second driver circuit 321, but also a fifth impedance control signal that is configured to control the level-down function.

[00180] It should be noted that the second calibration signal ZQ2_CODE[N-1:0] is configured to calibrate an increased resistance value, i.e. the second calibration signal ZQ2_CODE[N-1:0] is configured to calibrate an increased resistance value of each second impedance block to a standard resistance value. The third calibration signal ZQ3_CODE[N-1:0] is configured to calibrate a reduced resistance value, i.e. the third calibration signal ZQ3_CODE[N-1:0] is configured to calibrate a reduced resistance value of each second impedance block to a standard resistance value.

[00181] In addition, since the first calibration signal ZQ1_CODE[N-1:0] and the second calibration signal ZQ2_CODE[N-1:0] are configured to calibrate an increased resistance value, in some embodiments, it can be considered that the deviations in the first impedance block and the second impedance block are within an acceptable error range, so that the first calibration signal ZQ1_CODE[N-1:0] and the second calibration signal ZQ2_CODE[N-1:0] can represent the same signal.

[00182] In addition, it should be noted that for the second driver circuit 321, the actual signal in the third impedance control signal and the fourth impedance control signal is combined with the second calibration signal ZQ2_CODE[N-1:0] by the second logic module 521 in such a way as to generate a second target signal PU2_MAIN_CODE, configured to control the level increase function of the second impedance block 53. The structure of the circuit and the signal processing process for this part of the circuit can be correspondingly understood with reference to the first driver circuit 311, the description of which is not repeated here.

[00183] In addition, the second driver circuit 321 also combines the fifth impedance control signal and the third calibration signal ZQ3_CODE[N-1:0] by means of the third logic module 522 to generate the third target signal PD_MAIN_CODE, configured to control the level-lowering function of the second impedance block 53.

[00184] In some embodiments, as shown in Fig. 9, the second signal processing module 51 may include a fourth decoding module 511, a fifth decoding module 512, a third selecting module 513, and a fourth selecting module 514.

[00185] The fourth decoding module 511 is configured to receive the first OP MR5 OP[2:1], decode the first OP MR5 OP[2:1], and output the third decoded signal RONpu_CODE[M:0].

[00186] The fifth decoding module 512 is configured to receive the second OP MR34 OP[2:0], decode the second OP MR34 OP[2:0], and output a fourth decoded signal RTT_CODE[M:0].

[00187] The third selecting module 513 is configured to receive the second test flag signal PODTM_DQ_EN, the third decoded signal RONpu_CODE[M:0] and the fourth decoded signal RTT_CODE[M:0]; and select one of the third decoded signal RONpu_CODE[M:0] and the fourth decoded signal RTT_CODE[M:0] to output the third test state control signal in accordance with the second test flag signal PODTM_DM_EN.

[00188] The fourth selection module 514 is configured to receive a test enable signal PODTM_EN, a third test state control signal, and a third non-test state control signal; and to select one of the third test state control signal and the third non-test state control signal to output a third impedance control signal in accordance with the test enable signal PODTM_EN. In this case, the test enable signal PODTM_EN is configured to indicate whether the semiconductor memory device 30 is in a specified test mode.

[00189] For the second driver circuit 321 shown in Fig. 9, two specific embodiments of the mode may be applied in accordance with different definitions of the third non-test state control signal and the fourth impedance control signal.

[00190] In one embodiment, the third non-test state control signal is configured to indicate the impedance of the corresponding DQ in the termination state, and the fourth impedance control signal and the fifth impedance control signal are together configured to indicate the impedance of the corresponding DQ in the output signal generator state. In other words, by combining the DQ signal control strategy in the PODTM with the signal control strategy for the attribute related to the record, impedance control is implemented in the PODTM.

[00191] Accordingly, as shown in Fig. 10, the third impedance control signal is represented as ODT_MUX[M:0], the fourth impedance control signal is represented as IMPpu_CODE[M:0], and the fifth impedance control signal is represented as IMPpd_CODE[M:0]. In particular, compared with Fig. 9, the semiconductor memory device 30 in Fig. 10 further includes a third pre-processing unit 54 and a fourth pre-processing unit 55. The third pre-processing unit 54 is configured to decode the first OP MR5 OP[2:1] to obtain the fourth impedance control signal IMPpu_CODE[M:0]. The fourth pre-processing module 55 is configured to determine the third non-test state control signal according to MR34[5:3] including RTT_WR, MR35[2:0] including RTT_NOM_WR, MR35[5:3] including RTT_NOM_RD, MR34[2:0] including RTT_PARK, and MR33[5:3] including DQS_RTT_PARK. In addition, in the following description, if the semiconductor memory device 30 is in the PODTM, the test enable signal PODTM_EN is a logical "1". If the semiconductor memory device 30 is not in the PODTM, the test enable signal PODTM_EN is a logical "0". If the corresponding DQ 320 is a test object of the PODTM, the corresponding first test flag signal PODTM_DQ_EN is a logical "1". If DQ 320 is not a PODTM test target, the corresponding first PODTM_DQ_EN test flag signal is a logical "0".

[00192] The operating principle of the second driver circuit 321 of Fig. 10 is essentially the same as that of the first driver circuit 311 of Fig. 7, which can be understood with reference to the previous description of Fig. 7, and may not be repeated in this embodiment of the present invention. In addition, the second driver circuit 321 of Fig. 10 also has an additional part for controlling the impedance of the decrease in level, that is, the third logic module 522, the signal processing principle of which may relate to the following description. It should be understood that, since the DQ 320 supports the write function and the read function, in the mode other than PODTM, it is necessary to determine whether the third impedance control signal or the fourth impedance control signal is valid in accordance with the actual operating requirements, and then the valid signal and the second impedance control signal ZQ2_CODE[M:0] are logically combined to obtain the second target signal PU2_MAIN_CODE.

[00193] In another embodiment, the third non-test state control signal and the fifth non-test state control signal are together configured to indicate the impedance of the corresponding DQ in the output signal generator state, and the fourth impedance control signal is configured to indicate the impedance of the corresponding DQ in the completion state. In other words, by combining the DQ signal control strategy in the PODTM with the signal control strategy for the attribute related to reading, impedance control is implemented in the PODTM.

[00194] Accordingly, as shown in Fig. 11, the third impedance control signal is represented as IMPpu_CODE[M:0], the fourth impedance control signal is represented as ODT_CTRL[M:0], and the fifth impedance control signal is represented as IMPpd_CODE[M:0]. In particular, compared with Fig. 9, the second driver circuit 321 in Fig. 11 also includes a third pre-processing module 54 and a fourth pre-processing module 55. The third pre-processing module 54 is configured to decode the first OP MR5 OP[2:1] to obtain a third non-test state control signal. The fourth pre-processing module 55 is configured to determine the fourth impedance control signal in accordance with MR34[5:3] including RTT_WR, MR35[2:0] including RTT_NOM_WR, MR35[5:3] including RTT_NOM_RD, MR34[2:0] including RTT_PARK, and MR33[5:3] including DQS_RTT_PARK.

[00195] The operating principle of the second driver circuit 321 of Fig. 11 is essentially the same as that of the first driver circuit 311 of Fig. 8, which can be understood accordingly with reference to the previous description of Fig. 8, and it may not be repeated in this embodiment of the present invention. In addition, the second driver circuit 321 of Fig. 11 also has an additional part for controlling the impedance of the reduction of the level, i.e., the third logic module 522, the signal processing principle of which may relate to the following description.

[00196] The signal processing process in the second driver circuit 321 will be described below with reference to Fig. 10 or Fig. 11.

[00197] In some embodiments, each of the third decoded signal RONpu_CODE[M:0], the fourth decoded signal RTT_CODE[M:0], the third test state control signal, the third non-test state control signal, and the third impedance control signal includes (M+1) subsignal bits. The third selecting module 513 includes (M+1) third data selectors. The fourth selecting module 514 includes (M+1) fourth data selectors. In this case, the input of one of the third data selectors receives a 1-bit subsignal of the third decoded signal RONpu_CODE[M:0] and a 1-bit subsignal of the fourth decoded signal RTT_CODE[M:0], wherein the output of one of the third data selectors is configured to output a 1-bit subsignal of the third test state control signal, and the ends on the control side of all third data selectors receive the second test flag signal PODTM_DQ_EN. The input of one of the fourth data selectors receives a 1-bit subsignal of the third test state control signal and a 1-bit subsignal of the third non-test state control signal, wherein the output of one of the fourth data selectors is configured to output a 1-bit subsignal of the third impedance control signal, and the ends on the control side of all fourth data selectors receive the test enable signal PODTM_EN.

[00198] It should be noted that the third test state control signal is represented as the third test state control signal [M:0], the third non-test state control signal is represented as the third non-test state control signal [M:0], and the third impedance control signal is represented as the third impedance control signal [M:0]. Thus, the first third data selector receives RONpu_CODE[0], RTT_CODE[0], and PODTM_DQ_EN respectively, and selects one of RONpu_CODE[0] and RTT_CODE[0] to output the third test state control signal [0] in accordance with PODTM_DQ_EN. The first fifth data selector receives the third test state control signal [0], the third non-test state control signal [0], and PODTM_EN, respectively, and selects one of the third test state control signal [0] and the third non-test state control signal [0] to output the third impedance control signal [0] in accordance with PODTM_EN. Other situations can be understood by reference to those described earlier and by analogy.

[00199] In some embodiments, the fourth impedance control signal includes (M+1) bits of sub-signals. The second calibration signal ZQ2_CODE[N-1:0] and the third calibration signal ZQ3_CODE[N-1:0] include N bits of sub-signals. The second target signal PU2_MAIN_CODE and the third target signal PD_MAIN_CODE include a group of sub-signals. Each group of sub-signals includes N bits of sub-signals. The second generator module 53 includes A second impedance units, and each second impedance unit is configured to receive a group of sub-signals in the second target signal PU2_MAIN_CODE and a group of sub-signals in the third target signal PD_MAIN_CODE. In this case, the second logic module 521 is in particular configured to determine whether the level increase function of at least one second impedance block is enabled, in accordance with the third impedance control signal and the fourth impedance control signal; and to determine, in the case where the level increase function of the a ^th second impedance block is enabled, the level state of the a ^th group of sub-signals in the second target signal PU2_MAIN_CODE in accordance with the second calibration signal ZQ2_CODE[N-1:0] so as to control the resistance value of the second impedance block, which must correspond to the standard resistance value; or to determine, in the case where the level increase function of the a ^th second impedance block is disabled, that the a ^th group of sub-signals in the second target signal PU2_MAIN_CODE is in the first level state. The third logic module 522 is in particular configured to determine whether the function of increasing the level of at least one second impedance block is enabled, in accordance with the fifth impedance control signal; and to determine, in the case where the function of decreasing the level of the a ^th second impedance block is enabled, the level state of the a ^th group of sub-signals in the third target signal PD_MAIN_CODE in accordance with the third calibration signal ZQ3_CODE[N-1:0] so as to control the resistance value of the second impedance block, which must correspond to the standard resistance value; or to determine, in the case where the function of decreasing the level of the a ^th second impedance block is disabled, that the a ^th group of sub-signals in the third target signal PD_MAIN_CODE is in the second level state.

[00200] It should be noted that the actual signal in the third impedance control signal and the fourth impedance control signal is combined with the second calibration signal ZQ2_CODE[N-1:0] by the second logic module 521 so as to obtain the second target signal PU2_MAIN_CODE, thereby controlling the level increase function of the second impedance block. The structure and operation of the second logic module 521 are essentially the same as those of the first logic module 42, and the operating principle of the second logic module 521 may refer to the above description of the first logic module 42 and may not be repeated here.

[00201] The third logic module 522 is configured to combine the fifth impedance control signal IMPpd_CODE[M:0] and the third calibration signal ZQ3_CODE[N-1:0] to obtain the third target signal PD_MAIN_CODE in such a way as to control the level reduction function of the second impedance block. Similarly, the 1-bit subsignal of the fifth impedance control signal IMPpd_CODE[M:0] controls whether the level reduction function of one or more second impedance blocks is enabled. Based on this, it can be concluded that if the level-down function of a certain second impedance block is enabled, the increased resistance value of the second impedance block is calibrated to a standard resistance value using the third calibration signal ZQ3_CODE[N-1:0] so as to perform the level-down function, otherwise, if the level-down function of the second impedance block is disabled, the corresponding circuit of the second impedance block is turned off using a fixed signal in the second level state.

[00202] In some embodiments, each second impedance block includes N third switching transistors (e.g., third switching transistor 531 in Fig. 10 or Fig. 11), N fourth switching transistors (e.g., fourth switching transistor 532 in Fig. 10 or Fig. 11), and 2N second resistors (e.g., second resistor 533 in Fig. 10 or Fig. 11). The control-side end of the ^nth second switching transistor in the ^ath third impedance block is connected to the ^nth subsignal in ^{the ath} group of subsignals in the second target signal, the first end of one of the third switching transistors is connected to the first end of one of the second resistors, and the second end of one of the third switching transistors is connected to the power signal. The control-side end of the ^nth fourth switching transistor in the ^ath second impedance block is connected to the ^nth sub-signal in ^{the ath} group of sub-signals in the third target signal, the first end of one of the fourth switching transistors is connected to the ground signal, the second end of one of the fourth switching transistors is connected to the first end of one of the second resistors, and all second ends of the 2N second resistors are connected to the corresponding DQ.

[00203] It should be noted that, taking the first second impedance unit shown in Fig. 10 or Fig. 11 as an example, the first second impedance unit is configured to receive the first group of sub-signals PU2_MAIN_CODE_1[N-1:0] in the second target signal and the first group of sub-signals PD_MAIN_CODE_1[N-1:0] in the third target signal. In this case, PU2_MAIN_CODE_1[N-1:0] includes the sub-signals PU2_MAIN_CODE_1[0], PU2_MAIN_CODE_1[1] …… PU2_MAIN_CODE_1[N-1], and each sub-signal is configured to control the operating state of one of the third switching transistors, respectively, so as to control the second impedance unit to perform the level-up function using the standard resistance value or not to perform the level-up function. PD_MAIN_CODE_1[N-1:0] includes sub-signals PD_MAIN_CODE_1[0], from PD_MAIN_CODE_1[1] to PD_MAIN_CODE_1[N-1], and the sub-signal is configured, respectively, to control the operating state of one of the fourth switching transistors in such a way as to control the second impedance block to perform the level-down function using a standard resistance value or not to perform the level-down function.

[00204] In addition, in Fig. 10 or Fig. 11, three third switching transistors (only one third switching transistor 531 is numbered), three fourth switching transistors (only one fourth switching transistor 532 is numbered) and six second resistors (only one second resistor 533 is numbered) are shown in the first second impedance block, but in actual scenarios, the number of third switching transistors/fourth switching transistors/second resistors may be more or less.

[00205] In the preceding content, the first level state is a high level state, and the second level state is a low level state. The high level state refers to a level value at which the N-channel field-effect transistor is turned on or the P-channel field-effect transistor is turned off. The low level state refers to a level value at which the N-channel field-effect transistor is turned off or the P-channel field-effect transistor is turned on.

[00206] Both the first switching transistor and the third switching transistor are P-channel field-effect transistors, and the second switching transistor and the fourth switching transistor are N-channel field-effect transistors. The end on the control side of the P-channel field-effect transistor is a gate electrode, the second end of the P-channel field-effect transistor is a source electrode, the first end of the P-channel field-effect transistor is a drain electrode, the end on the control side of the N-channel field-effect transistor is a gate electrode, the second end of the N-channel field-effect transistor is a drain electrode, and the first end of the N-channel field-effect transistor is a source electrode. The standard resistance value is 240 ohms.

[00207] In embodiments of the present invention, a semiconductor memory device is proposed. When the semiconductor memory device is in a given test mode, the first MR and the second MR related to the DQ are configured to directly determine the impedance of the DM. For the DM, there is no need to add the determination of the state of the output signal generator and the corresponding control circuit for the given test mode in order to ensure the adaptation of the given test mode to the DM. The impedance of the DM can be tested in the given test mode to prevent the occurrence of data processing errors by the circuit.

[00208] In another embodiment of the present invention, with reference to FIG. 12, a schematic diagram of a composite structure of an electronic device 60 according to one embodiment of the present invention is shown. As shown in FIG. 12, the electronic device 60 may include a semiconductor memory device 30 described in any of the previous embodiments.

[00209] In an embodiment of the present invention, the semiconductor memory device 30 may be a DRAM chip.

[00210] Additionally, in some embodiments, the DRAM chip complies with the DDR5 memory specification.

[00211] Embodiments of the present invention mainly relate to a control method and a corresponding control circuit for DM and DQ of a semiconductor memory device. When the semiconductor memory device is in a predetermined test mode, the first MR and the second MR related to DQ are configured to directly determine the impedance of DM. For DM, there is no need to add the determination of the state of the output signal generator and the corresponding control circuit for the predetermined test mode in order to ensure adaptation of the predetermined test mode to DM. The impedance of DM can be tested in a predetermined test mode to prevent data processing errors from occurring by the circuit.

[00212] The foregoing represents only preferred embodiments of the present invention and is not intended to limit the scope of protection of the present invention.

[00213] It should be noted that in the present invention, the terms "including," "comprising," or any other variation thereof are intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that includes a number of elements includes not only those elements but also other elements not explicitly stated or elements inherent in the process, method, article, or device. Without further limitation, defining an element by the sentence "comprising ..." does not exclude the existence of other identical elements in a process, method, article, or device that includes that element.

[00214] The above numbers of embodiments of the present invention are for description only and do not represent advantages or disadvantages of the embodiments.

[00215] The methods disclosed in several embodiments of the method presented in the present invention can be arbitrarily combined without conflict to obtain new embodiments of the method.

[00216] The features disclosed in several product embodiments presented in the present invention may be arbitrarily combined without conflict to obtain new product embodiments.

[00217] The features disclosed in several embodiments of the method or device presented in the present invention can be arbitrarily combined without causing conflict to obtain new embodiments of the method or embodiments of the device.

[00218] The foregoing are only specific embodiments of the mode of the present invention and are not intended to limit the scope of protection of the present invention. Any variations or substitutions obvious to those skilled in the art within the technical scope disclosed in the present invention shall be included in the scope of protection of the present invention. Thus, the scope of protection of the present invention depends on the scope of protection of the claims.

INDUSTRIAL APPLICABILITY

[00219] In embodiments of the present invention, a control method, a semiconductor memory device and an electronic device are provided. When the semiconductor memory device is in a given test mode, the first MR and the second MR related to the DQ are configured to directly determine the impedance of the DM. For the DM, there is no need to add the determination of the state of the output signal generator and the corresponding control circuit for the given test mode in order to ensure the adaptation of the given test mode to the DM. The impedance of the DM can be tested in the given test mode to prevent data processing errors by the circuit.

Claims (95)

1. A control method used in a semiconductor memory device comprising a data mask pin configured to receive a write data input mask signal, the method comprising: when the semiconductor memory device is in a specified test mode, controlling the impedance of the data mask pin as a first impedance parameter via the first operating mode register, in response to selecting the data mask pin as a test object; or controlling the impedance of the data mask pin as a second impedance parameter via the second operation mode register, in response to determining that the data mask pin is not selected as a test object; wherein the semiconductor memory device further comprises at least one data pin configured to receive or output data, wherein the first mode register is configured to indicate that the impedance of at least one data pin in the output signal generator state is a first impedance parameter, and the second mode register is configured to indicate that the impedance of at least one data pin in the termination state is a second impedance parameter. 2. The control method according to paragraph 1, according to which, when the semiconductor memory device is in a specified test mode, the method additionally includes: controlling, by means of the first operating mode register, the impedance of the data pin as the first impedance parameter in response to selecting the data pin as the test object; or controlling, via the second operating mode register, the impedance of the data pin as a second impedance parameter in response to determining that the data pin is not selected as a test object. 3. The control method according to paragraph 1, according to which the method additionally includes: determining, via the third operating mode register, that the semiconductor memory device enters a specified test mode and selects the test object; or determining, by means of the third operating mode register, that the semiconductor memory device does not enter the specified test mode. 4. The control method according to paragraph 3, according to which, when determining that the semiconductor memory device enters a specified test mode, the method additionally includes: receiving the first operand in the first mode register, the second operand in the second mode register, and the third operand in the third mode register; decoding the third operand to obtain a first test flag signal; wherein the first test flag signal indicates whether the data mask pin is the test object; and selecting one of the first operand and the second operand to control the impedance of the pin for the data mask in accordance with the first test flag signal. 5. The control method according to paragraph 4, according to which the method additionally includes: determining a first non-test state control signal and a second impedance control signal; determining when the semiconductor memory device is in a predetermined test mode based on one of the first operand and the second operand, the first impedance control signal in accordance with the first test flag signal; or determining when the semiconductor memory device is not in a predetermined test state based on the first non-test state control signal, the first impedance control signal; and selecting, in accordance with an operating state of the semiconductor memory device, one of the first impedance control signal and the second impedance control signal for controlling the impedance of the pin for the data mask; moreover the first non-test state control signal is configured to indicate the impedance of the pin for the data mask in a state other than the specified test state, and the second impedance control signal is configured to indicate the impedance of the pin for the data in the output signal generator state; or the first non-test state control signal is configured to indicate the impedance of the pin for data in the state of the output signal generator, and the second impedance control signal is configured to indicate the impedance of the pin for the data mask in a state other than the specified test state. 6. The control method according to paragraph 4, according to which, in the event of determining that the semiconductor memory device enters a specified test mode, the method additionally includes: decoding the third operand to obtain at least one second test flag signal, wherein one of the at least one second test flag signal indicates whether one of the at least one data pin is a test object; and selecting, in accordance with the second test flag signal, one of the first operand and the second operand for controlling the impedance of a corresponding one of the at least one data pin. 7. The control method according to paragraph 6, according to which the method additionally includes: determining a third non-test state control signal, a fourth impedance control signal, and a fifth impedance control signal; determining when the semiconductor memory device is in a predetermined test mode based on one of the first operand and the second operand, the third impedance control signal in accordance with the second test flag signal; or determining when the semiconductor memory device is not in a predetermined test state based on the third non-test state control signal, the third impedance control signal; and selecting, in accordance with the operating state of the semiconductor memory device, a third impedance control signal and a fifth impedance control signal for controlling the impedance of the data pin, or selecting, in accordance with the operating state of the semiconductor memory device, a fourth impedance control signal and a fifth impedance control signal for controlling the impedance of the data pin; wherein the third non-test state control signal is configured to indicate the impedance of the corresponding pin for data in the completion state, and the fourth impedance control signal and the fifth impedance control signal are together configured to indicate the impedance of the corresponding pin for data in the output signal generator state; or the third non-test state control signal and the fifth impedance control signal are together configured to indicate the impedance of the corresponding pin for data in the output signal generator state, and the fourth impedance control signal is configured to indicate the impedance of the corresponding pin for data in the completion state. 8. The control method according to claim 4, wherein the specified test mode is a burst test mode of the output signal generator, and the burst test mode of the output signal generator is configured to test the impedance of the pin for the data mask or at least one pin for data after packaging; the first mode register has a standard serial number equal to 5, and the first operand refers to the operand from the second bit to the first bit stored in the first mode register; the second mode register has a standard serial number of 34, and the second operand refers to the operand from the second bit to the 0th bit stored in the second mode register; and The third mode register has a standard serial number of 61, and the third operand refers to the operand from bit 4 to bit 0 stored in the third mode register. 9. A semiconductor memory device comprising a first mode register, a second mode register, a data mask pin, and a first driver circuit coupled respectively to the first mode register, the second mode register, and the data mask pin; wherein the data mask pin is configured to receive a signal from the input write data mask; the first driver circuit is configured to, when the semiconductor memory device is in a given test mode, control the impedance of the data mask pin as a first impedance parameter corresponding to the first operating mode register in response to the selection of the data mask pin as a test object, or control the impedance of the data mask pin as a second impedance parameter corresponding to the second operating mode register in response to the fact that the data mask pin is not selected as a test object; wherein the semiconductor memory device further comprises at least one data pin configured to receive or output data, wherein the first mode register is configured to indicate that the impedance of at least one data pin in the output signal generator state is a first impedance parameter, and the second mode register is configured to indicate that the impedance of at least one data pin in the termination state is a second impedance parameter. 10. The semiconductor memory device of claim 9, which further comprises at least one second driver circuit, and each of the at least one second driver circuit is connected to the first mode register, the second mode register and one of the at least one data pin; wherein the second driver circuit is configured to, when the semiconductor memory device is in a given test mode, control the impedance of the data pin as a first impedance parameter by means of the first mode register in response to selecting the data pin as a test object, or control the impedance of the data pin as a second impedance parameter by means of the second mode register in response to determining that the data pin is not selected as a test object. 11. The semiconductor memory device of claim 10, which further comprises a third operating mode register and a first decoding module; wherein the first operating mode register is configured to store and output the first operand; the second operating mode register is designed with the ability to store and output the second operand; the third operating mode register is configured to store and output the third operand; wherein the third operand is configured to indicate whether the semiconductor memory device has entered a specified test mode; the first decoding module is configured to receive the third operand, decode the third operand, and output a first test flag signal; wherein the first test flag signal is configured to indicate whether the pin for the data mask is the test object; and the first generator circuit is further configured to receive a first test flag signal, a first operand and a second operand; and to select one of the first operand and the second operand for controlling the impedance of the pin for the data mask in accordance with the first test flag signal in the event that the semiconductor memory device enters a specified test mode. 12. The semiconductor memory device of claim 11, which is further configured to determine a first non-test state control signal, a second impedance control signal, and a first calibration signal; wherein the first calibration signal is configured to calibrate an increased resistance value; and The first schematic of the shaper contains: a first signal processing module configured to receive a first test flag signal, a first operand, a second operand, and a first non-test state control signal; and to output, based on one of the first operand and the second operand, a first impedance control signal in accordance with the first test flag signal when the semiconductor memory device is in a predetermined test state; or to output, based on the first non-test state control signal, a first impedance control signal when the semiconductor memory device is not in a predetermined test mode; a first logic module configured to receive a first impedance control signal, a second impedance control signal and a first calibration signal; and to select and logically combine the first impedance control signal, the second impedance control signal and the first calibration signal to output a first target signal; and a first driver module comprising a plurality of first impedance blocks and configured to receive a first target signal and control the plurality of first impedance blocks using the first target signal so as to control the impedance of the pin for the data mask; wherein the first non-test state control signal is configured to indicate the impedance of the pin for the data mask in a state different from the specified test state, and the second impedance control signal is configured to indicate the impedance of the pin for data in the state of the output signal generator; or the first non-test state control signal is configured to indicate the impedance of the pin for data in the state of the output signal generator, and the second impedance control signal is configured to indicate the impedance of the pin for the data mask in a state different from the specified test state. 13. The semiconductor memory device according to claim 12, wherein the first signal processing module comprises: a second decoding module configured to receive the first operand, decode the first operand, and output the first decoded signal; a third decoding module configured to receive a second operand, decode the second operand, and output a second decoded signal; a first selecting module configured to receive a first test flag signal, a first decoded signal and a second decoded signal; and select one of the first decoded signal and the second decoded signal to output a first test state control signal in accordance with the first test flag signal; and a second selection module configured to receive a test enable signal, a first test state control signal and a first non-test state control signal; and to select one of the first test state control signal and the first non-test state control signal to output a first impedance control signal in accordance with the test enable signal; wherein the test enable signal is configured to indicate whether the semiconductor memory device is in a specified test mode. 14. The semiconductor memory device of claim 13, wherein each of the first decoded signal, the second decoded signal, the first test state control signal, the first non-test state control signal and the first impedance control signal comprises (M+1) sub-signal bits, the first selection module comprises (M+1) first data selectors, and the second selection module comprises (M+1) second data selectors; wherein the input of one of the first data selectors is configured to receive a 1-bit sub-signal of the first decoded signal and a 1-bit sub-signal of the second decoded signal, wherein the output of one of the first data selectors is configured to output a 1-bit sub-signal of the first test state control signal, and the ends on the control side of all the first data selectors are configured to receive the first test flag signal; the input of one of the second data selectors is configured to receive a 1-bit sub-signal of the first test state control signal and a 1-bit sub-signal of the first non-test state control signal, wherein the output of one of the second data selectors is configured to output a 1-bit sub-signal of the first impedance control signal, and the ends on the control side of all second data selectors are configured to receive a test enable signal; where M is a positive integer. 15. The semiconductor memory device according to claim 14, wherein the second impedance control signal comprises (M+1) sub-signal bits, the first calibration signal comprises N sub-signal bits, the first target signal comprises A groups of sub-signals, and each group of sub-signals comprises N sub-signal bits; the first module of the shaper comprises A first impedance blocks, and each of the first impedance blocks is configured to receive a group of sub-signals in the first target signal; wherein the first logic module is in particular configured to determine whether the level increase function of at least one first impedance block is enabled, in accordance with the first impedance control signal and the second impedance control signal; and to determine, in the case where the level increase function of the a-th first impedance block is enabled, the level state of the a-th group of sub-signals in the first target signal in accordance with the first calibration signal so as to control the resistance value of the a-th first impedance block, which must correspond to the standard resistance value; or to determine, in the case where the level increase function of the a-th first impedance block is disabled, that the a-th group of sub-signals in the first target signal is in the first level state; wherein each of the first impedance blocks comprises N first switching transistors, N second switching transistors and 2N first resistors, the end on the control side of the n-th first switching transistor in the a-th first impedance block is connected to the n-th sub-signal in the a-th group of sub-signals in the first target signal, the first end of one of the first switching transistors is connected to the first end of one of the first resistors, and the second end of one of the first switching transistors is connected to the power signal; the end on the control side of one of the second switching transistors is connected to the ground signal, the first end of one of the second switching transistors is connected to the ground signal, the second end of one of the second switching transistors is connected to the first end of one of the first resistors, and all the second ends of the 2N first resistors are connected to the pin for the data mask; where n, a, N and A are integers, n is less than or equal to N, a is less than or equal to A and (M+1) is less than or equal to A. 16. A semiconductor memory device according to claim 11, in which the first decoding module is further configured to decode the third operand and output at least one second test flag signal; wherein one of the at least one second test flag signal is configured to indicate whether one of the at least one data pin is a test object; and the second driver circuit is further configured to receive a corresponding second test flag signal, the first operand and the second operand; and to select, in the event of the semiconductor memory device entering a specified test mode, one of the first operand and the second operand for controlling the impedance of the data pin in accordance with the second test flag signal. 17. The semiconductor memory device according to claim 16, which is further configured to determine a third non-test state control signal, a fourth impedance control signal, a fifth impedance control signal, a second calibration signal, and a third calibration signal; wherein the second calibration signal is configured to calibrate an increased resistance value, and the third calibration signal is configured to calibrate a decreased resistance value; where the second circuit of the shaper contains: a second signal processing module configured to receive a second test flag signal, a first operand, a second operand, and a third non-test state control signal; and output a third impedance control signal based on one of the first operand and the second operand in accordance with the second test flag signal when the semiconductor memory device is in a predetermined test state; or output a third impedance control signal based on the third non-test state control signal when the semiconductor memory device is not in a predetermined test mode; a second logic module configured to receive the third impedance control signal, the fourth impedance control signal and the second calibration signal; and to select and logically combine the fourth impedance control signal and the second calibration signal to output the second target signal; a third logic module configured to receive the fifth impedance control signal and the third calibration signal, and logically combine the fifth impedance control signal and the third calibration signal to output a third target signal; and a second driver module comprising a plurality of second impedance units and configured to receive the second target signal and the third target signal; and to control the plurality of second impedance units using the second target signal and the third target signal in such a way as to control the impedance of the corresponding pin for the data mask; wherein the third non-test state control signal is configured to indicate the impedance of the corresponding pin for data in the completion state, and the fourth impedance control signal and the fifth impedance control signal are together configured to indicate the impedance of the corresponding pin for data in the output signal generator state; or the third non-test state control signal and the fifth impedance control signal are together configured to indicate the impedance of the corresponding pin for data in the output signal generator state, and the fourth impedance control signal is configured to indicate the impedance of the corresponding pin for data in the completion state. 18. The semiconductor memory device according to claim 17, wherein the second signal processing module comprises: a fourth decoding module configured to receive the first operand, decode the first operand, and output a third decoded signal; a fifth decoding module configured to receive a second operand, decode the second operand, and output a fourth decoded signal; a third selecting module configured to receive the second test flag signal, the third decoded signal and the fourth decoded signal; and select, in accordance with the second test flag signal, one of the third decoded signal and the fourth decoded signal to output the third test state control signal; and a fourth selection module configured to receive a test enable signal, a third test state control signal and a third non-test state control signal, and to select, in accordance with the test enable signal, one of the third test state control signal and the third non-test state control signal to output a third impedance control signal; wherein the test enable signal is configured to indicate whether the semiconductor memory device is in a predetermined test mode. 19. The semiconductor memory device of claim 18, wherein each of the third decoded signal, the fourth decoded signal, the third test state control signal, the third non-test state control signal, and the third impedance control signal comprises (M+1) sub-signal bits, the third selection module comprises (M+1) third data selectors, and the fourth selection module comprises (M+1) fourth data selectors; wherein the input of one of the third data selectors is configured to receive a 1-bit sub-signal of the third decoded signal and a 1-bit sub-signal of the fourth decoded signal, wherein the output of one of the third data selectors is configured to output a 1-bit sub-signal of the third test state control signal, and the ends on the control side of all third data selectors are configured to receive a second test flag signal; the input of one of the fourth data selectors is configured to receive a 1-bit sub-signal of the third test state control signal and a 1-bit sub-signal of the third non-test state control signal, wherein the output of one of the fourth data selectors is configured to output a 1-bit sub-signal of the third impedance control signal, and the ends on the control side of all fourth data selectors are configured to receive a test enable signal. 20. The semiconductor memory device of claim 19, wherein the fourth impedance control signal comprises (M+1) sub-signal bits, wherein each of the second calibration signal and the third calibration signal comprises N sub-signal bits, each of the second target signal and the third target signal comprises A groups of sub-signals, and each group of sub-signals comprises N sub-signal bits; the second module of the generator comprises A second impedance blocks and each of the second impedance blocks is configured to receive a group of sub-signals in the second target signal and a group of sub-signals in the third target signal; wherein the second logic module is in particular configured to determine whether the level increase function of at least one of the second impedance blocks is enabled, in accordance with the third impedance control signal and the fourth impedance control signal; and to determine, in the case where the level increase function of the a-th second impedance block is enabled, the level state of the a-th group of sub-signals in the second target signal in accordance with the second calibration signal so as to control the resistance value of the second impedance block, which must correspond to the standard resistance value; or to determine, in the case where the level increase function of the a-th second impedance block is disabled, that the a-th group of sub-signals in the second target signal is in the first level state; the third logic module is in particular configured to determine whether the function of increasing the level of at least one of the second impedance blocks is enabled, in accordance with the fifth impedance control signal; and to determine, in the case where the function of decreasing the level of the a-th second impedance block is enabled, the level state of the a-th group of sub-signals in the third target signal in accordance with the third calibration signal in such a way as to control the resistance value of the second impedance block, which should correspond to the standard resistance value; or to determine, in the case where the function of decreasing the level of the a-th second impedance block is disabled, that the a-th group of sub-signals in the third target signal is in the second level state; wherein each of the second impedance blocks comprises N third switching transistors, N fourth switching transistors and 2N second resistors, the end on the control side of the n-th second switching transistor in the a-th third impedance block is connected to the n-th sub-signal in the a-th group of sub-signals in the second target signal, the first end of one of the third switching transistors is connected to the first end of one of the second resistors, and the second end of one of the third switching transistors is connected to the power supply signal; the end on the control side of the n-th fourth switching transistor in the a-th second impedance block is connected to the n-th sub-signal in the a-th group of sub-signals in the third target signal, the first end of one of the fourth switching transistors is connected to the ground signal, the second end of one of the fourth switching transistors is connected to the first end of one of the second resistors and all the second ends of the 2N second resistors are connected to the data mask pin. 21. A semiconductor memory device according to any one of paragraphs 15-20, in which the first level state is a high level state and the second level state is a low level state; both the first switching transistor and the third switching transistor are P-channel field-effect transistors, and both the second switching transistor and the fourth switching transistor are N-channel field-effect transistors; the control side end of each of the P-channel field-effect transistors is a gate electrode, the second end of each of the P-channel field-effect transistors is a source electrode, the first end of each of the P-channel field-effect transistors is a drain electrode, the control side end of each of the N-channel field-effect transistors is a gate electrode, the second end of each of the N-channel field-effect transistors is a drain electrode, and the first end of each of the N-channel field-effect transistors is a source electrode; and The standard resistance value is 240 ohms. 22. An electronic device comprising a semiconductor memory device according to any one of paragraphs 9-21.