RU2817029C2 - Light-emitter drive circuit, optical meter comprising light-emitter drive circuit, valuable document inspection device and method for driving light-emitting load by means of light-emitter drive circuit - Google Patents

Abstract

FIELD: optics.

SUBSTANCE: invention relates to a light emitter driving circuit, an optical meter for recognizing machine-readable security features on valuable documents, comprising a light emitter driving circuit, a device for checking valuable documents and a method for driving a light-emitting load through a light-emitting circuit. Result is achieved by the fact that the light emitter drive circuit includes a pulse controller comprising a voltage input for supplying an input voltage, a voltage output for outputting a controlled output voltage for driving the light-emitting load, and a control input for supplying a control voltage for controlling the level of the output voltage, current source comprising a switching element and a voltage-controlled component in series with the light-emitting load, wherein a pulse signal is transmitted to the control output of the switching element, which provides the connection of the control output of the voltage-controlled component with the voltage source in the first switching state of the switching element and absence of connection of control output of voltage-controlled component with voltage source in second switching state of switching element, and control unit, in which the first input is connected to the first output of the voltage controlled component and the second input is connected to the second output of the voltage controlled component in order to pick up the voltage drop on the voltage controlled component in the first switching state, and the output is connected to the control input of the pulse regulator for supplying control voltage, wherein the control voltage is controlled depending on the voltage drop on the voltage-controlled component.

EFFECT: providing high-efficiency operation of a light-emitting load, in particular a LED load, in which voltage variation of a pulse regulator is controlled.

14 cl, 14 dwg

Description

Field of technology to which the invention relates

The present invention relates to a light emitter driving circuit, an optical meter including a light emitter driving circuit, an apparatus for checking valuable documents, and a method for driving a light emitting load by means of the light emitter driving circuit.

State of the art

The light emitter or optical meter drive circuit is, for example, a system component in a banknote processing machine for recognizing machine-readable features. For example, machine-readable features are used in valuable documents (securities), such as banknotes, passports or identity cards (hereinafter also called measurement objects), to be able to confirm the authenticity of the measurement object. In this case, the measurement object is irradiated with quickly switched and powerful light flashes, and the characteristic reaction (response) of the measurement object to these light flashes is assessed. Using this method, you can reliably detect counterfeit measurement objects, i.e. valuable documents.

The device proposed in the invention for checking valuable documents is intended for checking a large number of measurement objects in the shortest possible time. For this purpose, banknote processing machines require transport and processing speeds of several meters per second, in particular from 1 to 12 m/s. Such processing speeds for checking a measurement object, which is then exposed to several flashes of light, place high demands on the generation of these flashes.

Illumination of the measured objects under test is carried out using at least one light emitter, in particular a light-emitting diode (LED). To drive light-emitting loads, light emitter excitation circuits with switching regulators are usually used. The main objective in this case is to drive the light-emitting load at low current ripple and reducing the voltage required to drive the light-emitting load in order to reduce unnecessary power loss.

Publications KR 20090060878 A and KR 101028860 B1 propose LED drive circuits for lighting devices. The presented options focus on the use of pulse width modulation (PWM) in LED drive circuits, allowing efficient brightness control at a constant LED current and constant LED wavelength. None of these circuits are suitable for generating the required amount of alternating ripple current from the LED load.

In the absence of PWM mode, none of the circuits can provide the required value of ripple current to the LED load to achieve the steady state of this circuit immediately after switching on, that is, applying the operating voltage. None of the PWM circuits can provide the required amount of ripple current to the LED load to achieve a steady state for the circuit immediately after the PWM control pulses are applied.

US 2009/0187925 A1 describes an LED drive circuit that supplies constant current to all LEDs connected in series and provides uniform illumination and optimal operating efficiency at low cost over a wide range of input/output voltage and temperature. Short-term voltage changes in the LED leg, such as those provided for in pulsating current operation, would result in a change in LED current. Therefore, this circuit is not suitable for operation in pulse mode.

In addition, specifications for LED drive circuits are known, such as the LM3464 circuit from Texas Instruments or the ZXLD1362 circuit from Zetex Semiconductors. Apparently, these technical solutions can minimize the drain-source voltage drop of the MOSFET in order to minimize power consumption. However, none of the presented solutions are suitable for pulsed operation of an LED load, especially when varying pulse trains, such as those alternating in height, are used to record attributes of a measurement object by emitting light through the LED drive circuit of an optical meter or valuable document verification device.

The present invention is based on the task of implementing highly efficient operation of a light-emitting load, in particular an LED load, in which the change in voltage of a switching regulator is controlled. In this case, different light-emitting loads must be operational. The number and type of light emitters used should not be limited. In addition, the nominal differences in the forward voltage of the light emitters and fluctuations in this voltage during operation must be compensated for in an energy-efficient manner. For example, degradation or heating of the LED load, the use of fast, even cyclically changing pulse sequences (as is required, for example, in a device for checking valuable documents), should not have any effect on the power consumption of the light emitter excitation circuit. In this case, the cyclically varying pulse sequence is a sequence of current pulses, which can have, in particular, different durations, pauses between two pulses and current strengths, repeating at fixed intervals.

The essence of the invention

This problem is solved using the features described in the independent claims of the invention. Preferred embodiments of the invention are given in the dependent claims.

The invention proposes a circuit for excitation of light emitters. The light emitter drive circuit includes a switching regulator containing a voltage input for supplying an input voltage, a voltage output for outputting an adjustable output voltage for driving the light-emitting load, and a control input for supplying a control voltage for regulating the output voltage level.

At least one controllable light emitter is provided as a light-emitting load. The light-emitting load is preferably an LED, also known as a light-emitting diode (LED), or a plurality of LEDs connected in series or parallel with each other. It is also possible to connect several series LED circuits in parallel (LED branches). In yet another preferred embodiment of the invention, the light-emitting load includes at least one other semiconductor light source based on the same principle of operation, for example a laser diode, a cavity light-emitting diode, abbreviated OR-LED, or an organic light-emitting diode, abbreviated OLED . Other loads, such as incandescent lamps, motors or thermoelectric elements, can also advantageously be driven by the excitation current driver of the invention.

A switching regulator is a voltage regulator that provides the basis for efficiently supplying power to a load, in this case a light-emitting load, using an intermittently connected electronic switching element and at least one energy storage device, such as capacitive and/or inductive. The switching regulator may contain a rectification unit.

A switching regulator regulates the input voltage supplied (supplied) to its voltage input, such as AC or DC input voltage, to obtain a DC output voltage, removed (output, available) at the voltage output of this switching regulator and also called output voltage. The DC output voltage is preferably higher, lower or inverted compared to the input voltage.

As a switching regulator, for example, a constant voltage regulator is used, also called a DC/DC regulator, or a DC regulator (English DC = Direct Current), which regulates the input constant voltage supplied to the voltage input of the switching regulator, into an output DC voltage, which can be output to the voltage output of a switching regulator and has a higher (English Buck-Boost Converter - combined converter) or lower (English Buck Converter - step-down converter) level or is inverted.

A buck converter is preferably used as a switching regulator. The buck converter regulates the input voltage supplied to the input of the switching regulator until the output voltage is applied to the output of the switching regulator and has a lower level compared to the applied input voltage.

The switching regulator contains a control input for applying (supplying) control voltage. This control voltage sets the level of the output voltage of the switching regulator. Therefore, the output voltage level depends on the control voltage (= affinity). The control voltage level is injective, preferably injective monotonically increasing/decreasing, and in a particular case, bijectively displayed in the output voltage. Thus, a change in control voltage is uniquely converted into a change in output voltage using a switching regulator. This relationship is preferably linear or logarithmic. A drop in the output voltage is possible only when the energy storage device of the pulse regulator is discharged, that is, when current flows from the latter.

The output voltage that can be obtained from the voltage output of the switching regulator varies preferably linearly depending on the control voltage applied to the control input. The slope of this linear function is called the proportionality coefficient. In a particularly preferred embodiment of the invention, the proportionality coefficient is negative, so that the output voltage decreases as the control voltage increases. This makes the switching regulator particularly easy to operate.

The light emitter excitation circuit proposed in the invention also includes a current source containing a switching element and a voltage-controlled component located in series with the light-emitting load, and a pulse signal is supplied to the control terminal of the switching element, and in the interval of generation of the pulse signal, the switching element is switched to a first switching state in which the control terminal of the voltage-controlled component is connected to the voltage source, and in a pause interval of the pulse signal, the switching element is switched to a second switching state in which the control terminal of the voltage-controlled component is not connected to the voltage source.

In one preferred embodiment of the invention, in the second switching state of the switching element, the control terminal of the voltage-controlled component is connected to a reference potential so that any existing charges are drained from the voltage-controlled component.

The use of the term "current source" instead of the also applicable term "current sink" for this component of the light emitter drive circuit is arbitrary. It should be noted that the choice of the appropriate term is determined only by the direction of the current at the output of the current source/current sink. Thus, a current source produces an output current, whereas if the current flow was reversed, the same component would be called a current sink. Since the current source used here is in series with the light-emitting load, the choice of the term "current source" or "current drain" depends only on the actual position of the light-emitting load relative to the current source/current sink. Since the actual position is not limiting according to the invention, the term "current source" can be used synonymously with the term "current sink". In the present description, the term "current source" is used for this component of the light emitter driving circuit.

The current source is an active two-terminal network in the excitation circuit of light emitters, which produces electric current at the point of its connection to the light-emitting load. In this case, the strength of the supplied current is only slightly or, ideally, not at all dependent on the electrical voltage at the connection point, so that the electric current is practically independent of the connected light-emitting load (connected consumer). For example, when the voltage changes by 1 V, the current changes by only 0.1%. The current source is connected in series with the light-emitting load, such that the current supplied by the current source is the current through the light-emitting load.

The current source contains a switching element, such as an electronic switch, an electromechanical switch, or a mechanical switch. Preferably, an electronic switch, such as a semiconductor switch, is used. The switching element is switched from a first switching state (eg, closed) to a second switching state (eg, open) by means of a pulse signal at its control terminal. In the pulse signal generation interval, the switching element is switched to the first switching state. During the pause interval of the pulse signal, the switching element switches to the second switching state. In the first switching state of the switching element, the current source is switched to an active state, and in the second switching state of the pulse signal, the current source is switched to an inactive state. A pulse signal, preferably a binary switching signal, is applied to a control terminal of the switching element (eg, the gate terminal of a switching transistor). The pulse signal is, for example, the output signal of a microcontroller connected to the control terminal of the switching element.

The switching element of the switching regulator is different from the switching element of the current source and is controlled, independently of the latter, by means of a pulse signal generated in the switching regulator itself.

In addition to the switching element, the current source also contains a voltage-controlled component, preferably a field-effect transistor, or MOSFET for short. The first terminal of the current source switching element is connected to the control terminal of the voltage controlled component. In the first switching state of the switching element, the control terminal of the voltage controlled component is connected to a voltage source, and the current source outputs an electric current in this first (closed) switching state. The voltage-controlled component thereby provides the output current of the current source in the first switching state. In this case, the voltage level of the voltage source sets the level of the output current of the current source. In the second switching state of the switching element, the control terminal of the voltage controlled component is not connected to the voltage source, and the current source does not produce an output current in this second (open) switching state.

The first terminal of the voltage controlled component is connected to the terminal of the light emitting load. Therefore, the output current of the current source passes through the light-emitting load. This means that the output current specified in the pulse signal generating interval by the voltage level at the control terminal of the voltage controlled component and provided by the component also passes through the light-emitting load in the first switching state of the switching element, whereby the light-emitting load emits light. This also means that in the second switching state of the switching element, the current source does not produce an output current, which accordingly does not pass through the light-emitting load, whereby the light-emitting load does not emit light in the second switching state.

In addition, the light emitter driving circuit includes a control unit, the first input of which is connected to the first terminal of the voltage-controlled component of the power source, and the second input is connected to the second terminal of the voltage-controlled component of the power source, for picking up a voltage drop across the voltage-controlled component in the first (closed) state switching The output of the control unit is connected to the control input of the pulse regulator to supply (supply) control voltage to the pulse regulator.

The control voltage is adjusted by the control unit depending on the voltage drop in the first (closed) switching state across the voltage controlled component. This regulation of the control voltage by the control unit is carried out in such a way that the voltage drop across the voltage controlled component is minimal.

The control unit of the invention regulates the output voltage of the switching regulator to a value equal to the sum of the voltage drop across the light-emitting load and the desired minimum voltage drop across the voltage-controlled component.

If the current source contains a current sense resistor (shunt) connected in series with the light-emitting load and a voltage-controlled component, then the output voltage of the switching regulator reaches, as a result of regulation, a value equal to the sum of the voltage drop across the light-emitting load, the target minimum voltage drop across the component , controlled by voltage, and the voltage drop across the current measuring resistor.

By controlling the voltage drop across the voltage controlled component to a minimum, the energy dissipated in that component is minimized, thereby reducing the power consumption of the light emitter drive circuit.

In addition, the change in the output voltage of the switching regulator is compensated. This compensation provides, for example, the possibility of varying for a given light emitter excitation circuit both the number of light emitters and their connection to each other (series or parallel). Nominally different voltages of the light emitters and fluctuations in this voltage during operation of the light emitter drive circuit due to degradation of the latter or temperature fluctuations (heating/cooling) inside or outside the circuit are also compensated in an energy-efficient manner.

The pulse signal at the control terminal of the switching element of the current source is also called a pulse train. A pulse signal is a periodically repeating change in the voltage level at the control terminal of a switching element of a current source, in which in the pulse formation interval (the first switching state) current flows through the voltage-controlled component, and in the pulse pause interval (the second switching state) current passes through the voltage-controlled component does not pass. Due to this cyclic change in the switching state and in accordance with the pulse signal, the control terminal of the voltage-controlled component is connected or not connected to the voltage source, causing the current source to be switched on and off periodically. When a pulsed signal is applied, the current source supplies a pulsating current to the light-emitting load. This pulse signal leads to cyclic pulsating currents and, as a consequence, to periodic (cyclic) switching on and off of the light-emitting load. The current through the light-emitting load in the pulse pause interval is preferably 0 A.

A pulse signal consists of a sequence of at least two separate pulses. Each individual pulse includes a pulse shaping interval (eg, with the voltage set to "HIGH") and a pulse pause interval (eg, with the voltage set to "LOW"). The formation and pause intervals of an individual pulse constitute the period of this pulse. The periods of the at least two individual pulses preferably have the same duration, that is, the individual pulses have a fixed frequency. This frequency is preferably from 100 Hz to 50 kHz (corresponding to a single pulse period of 20 ps to 10 ms).

When using a light emitter drive circuit in a banknote inspection device, these frequencies allow spatially resolved inspection of moving banknotes at typical processing speeds of 1 to 12 m/s. The pulse signal may be a so-called burst signal. A burst signal consists of at least one burst including a limited number of individual pulses. The sum of the periods of all individual pulses in a burst constitutes the burst interval. The burst preferably consists of 5-50 individual pulses. By using a light emitter drive circuit in a banknote inspection device, this allows for the inspection of moving banknotes with spatial resolution, with the light emitter turning on only when a banknote is present in the measurement area.

The burst signal may be a periodically repeating signal. The time interval between two packets following each other is a packet pause. The intervals of formation and pause of a packet constitute the period of this packet. The duration of the burst period is preferably from 10 ms to 1 s. When using a light emitter drive circuit in a banknote validator, this results in one packet per banknote at a typical processing speed of 1 to 12 m/s.

The pulse signal for switching the switching element may be a pulse-width modulated signal such that the duty cycle of the pulse signal may be varied. In this case, the duty cycle shows the ratio of the duration of the pulse formation interval to the duration of the pulse period for a periodic sequence of pulses.

In one preferred embodiment of the invention, the control unit includes a storage capacitor for raising and lowering the control voltage level. To increase the control voltage, the storage capacitor is charged. To reduce the control voltage, the storage capacitor is discharged. Thus, the storage capacitor is a dynamic charge storage device. The resulting average voltage on the storage capacitor is supplied as a control voltage to the control input of the pulse regulator. This makes it possible to compensate for fluctuations in the voltage drop across the light-emitting load and fluctuations in the output voltage of the switching regulator. The voltage drop across the voltage controlled component in the first (closed) switching state causes the component to operate at its optimal operating point, with the voltage drop being minimal in the first (closed) switching state.

The storage capacitor is therefore part of a linear, time-invariant system in the control unit. The storage capacitor is preferably part of two resistor-capacitor circuits, abbreviated RC circuits, designed to create two integrating, time-continuous, linear, time-invariant and easily implemented transfer links in the control unit.

The time constant of the RC circuit for charging the storage capacitor should take such a value that the highest rate of change in the voltage of the storage capacitor is less, preferably 2 times, the ratio of the lowest rate of change of the output voltage and the proportionality coefficient of the pulse regulator. The rate of change of voltage of the storage capacitor can also be reduced, but in this case there would be an unnecessary lengthening of the regulation phase. The rate of change of the output voltage of the pulse regulator is equal to the ratio of the smallest current of the light-emitting load in the interval of pulse formation and the capacity of the energy storage device at the output of the pulse regulator. The time constant selection condition ensures that at the end of the regulation phase there is no negative overshoot of the output voltage pulse of the switching regulator, which could cause the voltage drop across the voltage-controlled component to be too low and subsequently cause an undesirable reduction in the light emitter current.

In a preferred embodiment of the invention the following values are set:

- the lowest rate of change in the output voltage of the pulse regulator dUSRA1/dt = 165 V/s,

- proportionality coefficient of the pulse regulator KS=5.5,

- rate of change of voltage of the storage capacitor dUSK1/dt=dUSRA1/dt/Ks/2 = 15 V/s

- RC circuit charging voltage UL=5 V,

- time constant τ RC circuit (charging) = UL/dUSK1/dt=0.3 s.

Draining of charge from the storage capacitor during pauses of pulse signals is necessary so that the control unit can bring the regulated output voltage of the pulse regulator to the maximum value after turning off the light emitter pulses, which corresponds to the initial state. The time constant of the RC circuit for discharging the storage capacitor must take such a value that the output voltage of the switching regulator increases only by a small amount during the pause. The preferred output voltage rise of a switching regulator is less than 0.1 V during pulse pauses. Increasing the output voltage of a switching regulator results in an increased voltage drop across the voltage-controlled component, which results in increased power loss in the voltage-controlled component. There is no need to select a time constant for the discharge, which guarantees the same increase in the output voltage of the pulse regulator in all operating modes (the duration of the pulse formation and pause intervals), especially with very long pulse pauses. With longer pauses between pulses and a constant pulse formation interval, there is a decrease in duty cycle (the ratio of the duration of the pulse formation interval to the duration of the pulse period). With a constant light source current in the pulse generation interval and a reduced duty cycle, there is a decrease in the average power loss in the voltage-controlled component. Therefore, it is necessary to determine only the value of the longest pulse pause at which the power loss due to an increase in the voltage drop across the voltage-controlled component does not become greater than the power loss at the same value of the light emitter current in the pulse generation interval and the shortest pulse pause (then there is the greatest duty cycle). From this value the discharge time constant for the longest pulse pause and the value that must be determined for the increased output voltage of the switching regulator in the pulse pause are determined. As with the charging process, the proportionality factor of the switching regulator must also be included in the calculation of the discharging process.

In a preferred embodiment of the invention the following values are set:

- increasing the output voltage of the pulse regulator during the pulse pause dUSRA2 = 0.1 V,

- with a minimum voltage drop across a voltage-controlled component of 1.5 V (no rise), the power loss in that component increases by the same factor as the voltage rise: (0.1 V + 1.5 V) / 1, 5 V=1.07,

- proportionality coefficient of the pulse regulator KS=5.5,

- reduction in the voltage of the storage capacitor dUSK2=dUSRA2/KS=0.0182 V,

- longest pulse pause TPause = 0.125 s,

- rate of change of voltage of the storage capacitor dUSK2/dt=dUSK2/TPause = 0.146 V/s,

- maximum storage capacitor voltage USKmax = 2.6 V,

- time constant τ RC circuit (discharge) = USKmax/dUSK2/dt = 18 s.

If in another embodiment of the invention it is necessary to increase the charge time constant (to reduce the rate of change of the storage capacitor voltage), then it is necessary to increase the discharge time constant by the same factor to prevent further increase in power loss in the voltage controlled component.

In a preferred embodiment of the invention, the control unit contains a comparison unit, which at its output produces a comparison voltage depending on the voltage drop across the voltage-controlled component. The reference voltage is preferably a binary voltage, which makes it particularly easy to implement the subsequent control voltage control unit. The comparison unit can be made in the form of a comparator. The output of the comparison unit is connected to the input of the control voltage regulation unit of the control unit. This modular design allows for more flexible configuration of the control unit. The control voltage regulation unit regulates the control voltage depending on the comparison voltage. The output of the control voltage regulation unit is connected to the control input of the pulse regulator to supply control voltage.

In one preferred embodiment of the invention, the control voltage is increased by the control voltage control unit if the (binary) comparison voltage is at a first level, and the control voltage is decreased by the control voltage control unit if the comparison voltage is at a second level different from the first. In this case, the comparison voltage level should be taken into account in the steady-state operating mode of the light emitter excitation circuit, that is, after the end of the regulation phase or the startup phase of the pulse regulator and control unit.

In a preferred embodiment of the invention, the comparison unit comprises a comparator, the first input of which is connected to the first terminal of the voltage-controlled component, and a constant voltage source. The first terminal of the constant voltage source is connected to the second input of the comparator, and the second terminal of the constant voltage source is connected, as a second input of the control unit, to the second terminal of the voltage-controlled component. The constant voltage source supplies a reference voltage to the second input of the comparator, the level of which is compared with the voltage level at the first input of the comparator. Depending on the comparison result, a comparison voltage is applied to the output of the comparator. In this way, a light emitter drive circuit is implemented, the comparison unit of which compares the voltage drop across the voltage-controlled component with a reference DC voltage to obtain a comparison voltage. This circuit takes up little space and has low power consumption.

In a preferred embodiment of the invention, a diode is provided in the line connecting the first terminal of the voltage-controlled component and the first input of the comparator, the anode of which is connected to the first input of the comparator, and the cathode of which is connected, as the first input of the control unit, to the first terminal of the voltage-controlled component. The diode has a blocking function to prevent current flow through the light-emitting load during the pulse pause.

In a preferred embodiment of the invention, the first output of the storage capacitor of the comparison unit is connected to the anode of the diode, and the second output is connected to the second input of the control unit. The storage capacitor of the comparison unit differs from the storage capacitor of the control voltage regulation unit described above. In the case of a variable pulse sequence, the storage capacitor ensures that the control voltage is optimized for the highest current that occurs in the pulse generation interval. In this case, the smallest voltage drop across the voltage-controlled component occurs at the highest current.

In one preferred embodiment of the invention, a voltage source with high internal resistance is provided in the line connecting the anode of the diode and the first input of the comparator. The voltage level of this voltage source exceeds the voltage level of the constant voltage source at the second input of the comparator. As a result, the reference voltage is reliably set to "HIGH" in the circuit's startup state (see below). This ensures the minimum control voltage in the start-up state and therefore the maximum output voltage of the switching regulator, so that the light-emitting load carries the specified current through the light-emitting load when first turned on. The voltage source makes it possible to increase the output voltage of the pulse regulator in the case of a changing light-emitting load during operation of the excitation circuit of this light emitter.

Thus, in the case of an inactive current source (pulse signal pause or second switching state), the storage capacitor of the comparator is charged to the voltage level of the voltage source at the first input of the comparator. Due to the higher voltage level at the first input, the output of the comparator provides the first state of the comparison voltage. If, after this, the current source is connected via a pulse signal in the shaping interval and a decrease in voltage occurs on the voltage-controlled component, the level of which is lower than the difference between the voltage levels at the first input of the comparator and the diode voltage when passing direct current, then the storage capacitor is discharged by the voltage-controlled component through diode to a voltage value that corresponds to the sum of the voltage across the voltage-controlled component and the voltage of the diode when passing forward current. If this voltage level at the first input of the comparator, achieved during the discharge process, exceeds the voltage level at the second input of the comparator, then the first state of the comparison voltage is still maintained at the output. As a result, the control voltage changes, which leads to a change in the output voltage of the switching regulator. This change causes the voltage drop across the voltage-controlled component to change and, as a result, switches the comparison voltage level at the output of the comparator.

In another preferred embodiment of the invention, the control unit is implemented as a computer software product installed in a microcontroller. In this case, the voltage drop across the voltage controlled component is digitized using A/D conversion and made available to the microcontroller. The latter generates a control voltage in accordance with the processes presented in this description. This control voltage is converted into an analog voltage signal using digital-to-analog conversion and then supplied to the control input of the switching regulator. This allows flexible reprogramming of control parameters.

Another object of the invention is an optical meter for recognizing machine-readable security features on valuable documents. This optical meter contains at least one light emitter for illuminating the security feature. This light emitter, in particular the LED, is driven by a light emitter drive circuit of the type described above. In this case, the pulse signal drives the current source to generate cyclic pulse currents, which then also pass through the light-emitting load, cyclically turning it on and off. This cycling of the light-emitting load on and off is used to illuminate the aforementioned measured object. The optical meter may be part of a device for checking valuable documents.

Another object of the invention is a device for checking valuable documents containing a machine-readable security feature, which includes a zone for receiving valuable documents as measurement objects and an optical meter of the type described above. The device proposed in the invention checks a large number of measurement objects (valuable documents) in the shortest possible time. In particular, the speed of movement through the measurement zone is several meters per second. As a result, only a very short period of time, for example 0.02 s, is available for checking the measurement object, which is then exposed to several flashes of light. This requires a short turn-on and turn-off time of the light-emitting load, which is carried out using a pulse signal. In a preferred embodiment of the invention, the device for checking valuable documents further includes a detector for recording the response of the security feature in response to illumination and converting it into an electronic output signal. Compared to visual perception, this makes it possible to more accurately check the presence of a security feature and therefore improve protection against counterfeiting. In a preferred embodiment of the invention, the device for checking valuable documents also includes a processor that evaluates one property of a security feature (eg, authenticity, document class) depending on the output signal of the detector and outputs an evaluation result. This allows the verification device to be integrated into an industrial environment, such as a banknote processing machine, and allows for more accurate analysis of the security feature, thereby improving counterfeit protection. Moreover, the microprocessor of the light emitter driving circuit according to the invention is preferably also a processor of the device for checking valuable documents.

Another object of the invention is a method for driving a light-emitting load by means of a light-emitting circuit of the type described above. In this method, a pulse signal is first applied to the control terminal of the switching element for the purpose of connecting the control terminal of the voltage controlled component to a voltage source. In addition, the control unit removes the voltage drop across the voltage controlled component. In addition, the control unit supplies a control voltage that is regulated depending on the voltage drop across the voltage-controlled component. The switching regulator then receives a control voltage and produces a controlled output voltage to drive the light-emitting load, using the control voltage to regulate the output voltage level, the output voltage preferably decreasing linearly with the control voltage.

Brief description of drawings

Other embodiments and advantages of the invention are explained in more detail below with the help of the drawings, which show only examples of embodiments of the invention. Identical elements in the drawings are provided with the same reference symbols. These drawings are not to be considered exact or to scale, and depictions of individual items may be excessively large or overly simplified. The drawings show:

in fig. 1 is a schematic diagram of excitation of light emitters in the first embodiment of the invention,

in fig. 2 is a schematic diagram of excitation of light emitters in the second embodiment of the invention,

in fig. 3 is a first example of a switching circuit for a light emitter drive circuit according to the invention, based on the principle shown in FIG. 1,

in fig. 4 is a second example of a switching circuit for the light emitter excitation circuit proposed in the invention, based on the principle presented in FIG. 2,

in fig. 5 is a diagram of the sequence of operations (in the first embodiment example) of the method proposed in the invention for actuating a light-emitting load,

in fig. 6 is a first voltage/current timing diagram of selected signals in the light emitter driving circuit shown in FIG. 3,

in fig. 7 is a selected portion of the voltage/current timing diagram shown in FIG. 6,

in fig. 8 is a selected portion of the voltage/current timing diagram shown in FIG. 7,

in fig. 9 is a second timing diagram of signal voltages in the light emitter driving circuit shown in FIG. 3,

in fig. 10 is the first section of the voltage timing diagram shown in FIG. 9,

in fig. 11 is the second section of the voltage timing diagram shown in FIG. 9,

in fig. 12 is one of the sections of the voltage timing diagram shown in FIG. 9,

in fig. 13 is one of the sections of the voltage timing diagram shown in FIG. 12,

in fig. 14 is one of the sections of the voltage timing diagram shown in FIG. 12.

Description of embodiments of the invention

In fig. 1 shows a schematic diagram of excitation of light emitters in the first embodiment of the invention. Switching regulator N8 contains voltage input N8_1 for supplying input voltage U6. Switching regulator N8 contains voltage output N8_2 to output the regulated output voltage U5. Switching regulator N8 contains a control input N8_3 for supplying control voltage U4 in order to regulate the level of output voltage U5.

The voltage output N8_2 is connected to one of the terminals of the light-emitting load 3. In this example, the light-emitting load 3 is a light emitting diode (LED) V3. According to the invention, it is also possible to use several LEDs connected to each other in series or parallel as the light-emitting load 3. It is also possible to connect several series LED circuits in parallel (LED branches) or use other semiconductor light emitters based on the same operating principle. The anode of the light-emitting load 3 is connected to the voltage output N8_2.

In the excitation circuit of the light emitters, a current source 1 is provided. The term "current source" is used in all drawings regardless of the direction of current at the output of source 1 (terminals V1_1 and V1_2 of voltage controlled component V1). The term "current source" can be replaced by the term "current sink".

The current source 1 includes a switching element N3 and a voltage-controlled component V1, in this example a field-effect transistor (MOS). The first terminal V1_1 of the MOS is connected as a current output of the current source 1 to the cathode of the light-emitting load 3. The second terminal V12 of the MOS is connected to the first terminal of the current measuring resistor R1 (shunt). The second terminal of the current-measuring resistor R1 is connected to the reference potential.

The control pin V1_3 of the MOS is connected to the first pin N3_1 of switching element N3. The second terminal N3_2 of the switching element N3 is connected to the first terminal of the voltage source N2. The second terminal of the voltage source N2 is connected to the reference potential. The pulse signal U7 is supplied to the control terminal N3_3 of the switching element N3. This pulse signal U7, being a switching signal for switching element N3, is characterized by a pulse shaping interval in which switching element N3 switches to the first (closed) switching state, and a pulse pause interval in which switching element N3 switches to the second (open) switching state . The switching element N3 is, for example, an electronic switching element such as a transistor. In fig. 1, switching element N3 is shown in a second (open) switching state in which the MOS control terminal V1_3 is not connected to the first terminal of voltage source N2. In the first switching state (not shown) of the switch element N3, the control terminal V1_3 of the MOS is connected to the first terminal of the voltage source.

The first output V1_1 of the MOS V1 is connected to the first input 2_1 of the control unit 2. The second output V1_2 of the MOS V1 is connected to the second input 2_2 of the control unit 2. Thus, the collection of the voltage drop across the MOS V1 can be performed by the control unit 2. Output 2_3 of control unit 2 is connected to control input N8_3 of pulse regulator N8 to obtain control voltage U4, regulated depending on the voltage drop across MOS VI.

The N8 switching regulator is, for example, a standard step-down DC-DC converter, the function of which does not require detailed explanation. For example, the N8 switching regulator can be implemented using a combination of the Texas Instruments TPS541540 integrated circuit and a feedback resistor. The use of other integrated circuits is not excluded.

In fig. 1 shows the comparison unit 21 and the control voltage regulation unit 22 of the control unit 2, which are described in more detail in relation to FIG. 3.

The operating principle of the light emitter driving circuit shown in FIG. 1 is explained below. 1.

Switchable current source 1 can be connected and disconnected using the pulse signal U7. The output current level of current source 1 is set by voltage source N2. In this case, possible changes in the output current level must be synchronized with the pulse signal in such a way that, as a result, a cyclically changing sequence of current pulses passes through the light-emitting load.

The light-emitting load V3 is powered by a high-efficiency switching regulator N8 with an output voltage U5. Its input voltage U6 is a supply voltage of, for example, 24 V DC. This does not exclude other levels or types of input voltage U6, so that the switching regulator N8 can also be supplied with alternating current voltage, which is then rectified.

To ensure high efficiency operation of the current source 1, it is necessary that the voltage drop between the first terminal V1_1 and the second terminal V1_2 of the voltage controlled component V1 be as small as possible while in the first (open) switching state. If the voltage-controlled component V1 is a MOS, then the voltage drop between pins V1_1 and V1_2 is called the drain-to-source voltage (UDS), and the voltage drop between the inputs V1_3 and V1_2 is called the gate-to-source voltage (UGS). The MOS has a threshold voltage Vth of, for example, 1.8 V and is characterized in that the effective drain current, in particular the current through the light-emitting load, passes at UGS>Vth. The drain-source voltage preferably satisfies the condition UDS>UGS-Vth so that the drain current, in particular the current through the light-emitting load, is as independent of UDS as possible.

The control input N8_3 of the pulse regulator N8 is connected to the output 2_3 of control unit 2. The output voltage U5 of switching regulator N8 preferably decreases linearly with increasing control voltage U4. There may also be another relationship between U4 and U5. The values of U4 and U5 may represent a bijective mapping. Thus, the output voltage level of U5 can be adjusted using the control voltage level of U4.

The level of control voltage U4 is regulated by control unit 2.

In the first switching state of the switching element N3 (current source 1 is connected), the voltage drop across the MOS V1 is removed and the control voltage U4 is adjusted accordingly.

In the second switching state of switching element N3 (current source 1 is switched off), control voltage U4 is not regulated.

During operation of the light emitter excitation circuit (second and third operating phases - see below), a pulse signal U7 is supplied to switching element N3 for periodic (cyclic) connection and disconnection of current source 1. From this it follows that the light-emitting load 3 is turned on or off in accordance with the pulse signal U7. This generates, for example, flashes of light emitted onto a measurement object, such as a banknote, in order to obtain and evaluate a characteristic reaction to them. This makes it possible, for example, to check the authenticity of machine-readable features on a measurement object using a banknote verification system.

The increased power loss of the MOS in the second operating phase ("regulation phase" - see explanations to Fig. 6-14) in the excitation circuit of the light emitters must be taken into account when selecting components and thermal calculations of the printed circuit board.

In fig. 2 shows a schematic diagram of excitation of light emitters in the second embodiment of the invention. The operating principle of the light emitter excitation circuit in Fig. 2 corresponds to the principle of operation of the circuit in Fig. 1, so the description given for FIG. 1 is fully applicable to FIG. 2. Only the differences between FIG. 1 and fig. 2. Unlike FIG. 1, in fig. 2, the control unit 2 is not made with a comparison node 21 and a control voltage regulation node 22, but, alternatively, with an analog-to-digital converter (ADC) 23, a microcontroller 24 and a digital-to-analog converter (DAC) 25. This difference is explained in more detail in fig. 4. In the microcontroller 24, the voltage difference across the MOS is registered by obtaining the voltage value converted from analog to digital through the first pin V1_1 and the second pin V1_2, and setting the digital value of the control voltage corresponding to the digital value of the voltage drop. In the following DAC, the specified digital control voltage value is converted into an analog control voltage, which is then supplied to the switching regulator N8 as control voltage U4.

In fig. 3 shows the first example of a switching circuit for the light emitter excitation circuit proposed in the invention, based on the principle presented in FIG. 1. Description given for FIG. 1 is fully applicable to FIG. 3. Therefore, only the differences between FIG. 1 and fig. 3.

Unlike FIG. 1, current source 1 in FIG. 3 is a precision current source which also contains DAC N2 and operational amplifier N4.

The current source 1 also contains, as in FIG. 1, switching element N3 and voltage controlled component V1, shown here as a field effect transistor (MOS). The first terminal V1_1 of the MOS is connected as a current output of the current source 1 to the cathode of the light-emitting load 3. The light-emitting load is shown here as a series connection of LEDs V3 - Vn. Since in FIG. 3, the load current flows from the cathode of the light-emitting load to the terminal V1_1 of the current source 1, the term "current sink" is more appropriate from a purely theoretical point of view.

In one embodiment of the invention not shown in FIG. 3, the first terminal V1_1 of the voltage-controlled component V1 is connected to the output N8_2 of the switching regulator N8, the second terminal V1_2 of the voltage-controlled component V1 is connected to the anode of the light-emitting load 3, for example, the anode of the first LED Vn of all LEDs V3 - Vn connected in series, and the cathode of the LED V3 connected to the first terminal of current-measuring resistor R1.

In another embodiment of the invention, not shown in FIG. 3, the first terminal V1_1 of the voltage-controlled component V1 is connected to the output N8_2 of the switching regulator N8, the second terminal V1_2 of the voltage-controlled component V1 is connected to the first terminal of the current-sensing resistor R1, and the second terminal of the current-sensing resistor R1 is connected to the anode of the light-emitting load 3, such as the anode of the first LED Vn from all LEDs connected in series V3 - Vn. The cathode of LED V3 is connected to the reference potential.

One skilled in the art of light emitter drive circuits can easily implement these embodiments of the invention. Since in these embodiments the output current of the source 1 flows from the terminal V1_2 to the light-emitting load, the term "current source" is more appropriate from a purely theoretical point of view.

Since the topology of the "current source 1" is the same in all embodiments of the invention, and only the direction of the output current supplied to the light-emitting load 3 is changed, the term "current source" is used in the present description as a general one.

The second terminal V1_2 of MOS V1 is connected to the first terminal of the current measuring resistor R1 (shunt). The second terminal of the current-measuring resistor R1 is connected to the reference potential.

The control pin V1_3 of MOS V1 is connected to the output of operational amplifier N4. The positive input of the operational amplifier N4 is connected to the first terminal N3_1 of the switching element N3. The negative input of the operational amplifier N4 is connected to the first terminal of the current measuring resistor R1.

The second pin N3_2 of the switching element N3 is connected to the output of the voltage source N2, which in this case is a DAC. The DAC input is connected to microcontroller N1. In an alternative (not shown) embodiment, the second pin N3_2 of switch element N3 is connected to the analog output of microcontroller N1, wherein the DAC is an integral part of microcontroller N1.

The control terminal N3_3 of the switching element N3 is again supplied with a pulse signal U7. Pulse signal U7 is generated by microcontroller N1. This pulse signal U7 is characterized by a pulse shaping interval in which the switch element N3 switches to the first (closed) switching state, and a pulse pause interval in which the switching element N3 switches to the second (open) switching state. The switching element N3 is, for example, an electronic switching element such as a transistor. In fig. 3, switching element N3 is shown in a second (open) switching state in which the first (positive) input of operational amplifier N4 is not connected to the output of DAC N2. In one preferred embodiment of the invention (not shown), in the second switching state of the switching element N3, the first input of the operational amplifier N4 is connected to a reference potential, so that any available charges drain from the operational amplifier. As a result, the reference potential is also present at the output of the op-amp, so that no current flows through the light-emitting load.

In the not shown first (open) switching state of switching element N3, the first (positive) input of operational amplifier N4 is connected to the output of DAC N2.

As in FIG. 1, the first pin V1_1 of the MOS in FIG. 3 is also connected to the first input 21 of control unit 2. The second output V1_2 of the MOS is connected to the second input 2_2 of the control unit 2. Thanks to this, the voltage drop UDS on the MOS can be removed by the control unit 2. Output 2_3 of control unit 2 is connected to control input N8_3 of pulse regulator N8 to supply control voltage U4, regulated depending on the voltage drop across MOS V1.

Control unit 2 shown in FIG. 3, contains a comparison node 21, a control voltage regulation node 22 and a logical NAND gate D1.

Instead of the NAND gate D1, another logic gate can also be used to time the pulse signal U7 and the output signal of the comparison node 21 with each other.

Comparison unit 21 contains a comparator N5, the first (positive) input of which is connected to the anode of the diode V2. The cathode of the diode V2 is connected to the first terminal V1_1 of the MOS and represents the first input 2_1 of the control unit 2. The anode of diode V2 is also connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to the voltage source U2. The anode of diode V2 is also connected to the first terminal of storage capacitor C1.

The second output of the storage capacitor C1 is connected to the second output V1_2 of the MOS and represents the second input 2_2 of the control unit 2. The second terminal of the storage capacitor C1 is connected to the second terminal of the constant voltage source U1. The first output of the constant voltage source U1 is connected to the second (negative) input of the comparator N5.

The output of comparator N5 is connected to the first input D1_1 of the NAND gate D1. The second input D1_2 of the NAND gate D1 is connected to the output of the microcontroller N1, which produces a pulse signal U7. The output D1_3 of the AND-NOT logic gate D1 is connected to the control input of the switching element N6 of the control voltage regulation node 22. Switching element N6 is, for example, an analog field-effect transistor switch (MOS switch).

The first input terminal of the switching element N6 is connected to the first terminal of the resistor R3 of the control voltage regulation unit 22. The second terminal of the resistor R3 is connected to the voltage source U3 of the control voltage control unit 22. The second input terminal of the switching element N6 is connected to the first terminal of the resistor R4 of the control voltage control unit 22. The second terminal of resistor R4 is connected to the reference potential.

The output terminal of the switching element N6 is connected to the first terminal of the storage capacitor C2 of the control voltage control unit 22. The second terminal of storage capacitor C2 is connected to the reference potential.

As a result of the action, by applying the appropriate signal, the control output of the switching element N6 is connected to the first output of the storage capacitor C2, either the first output of the resistor R3, or the first output of the resistor R4.

Resistor R3 and storage capacitor C2 form the first RC circuit. Resistor R4 and storage capacitor C2 form the second RC circuit. The time constants of both RC circuits are selected in such a way that the functioning of the light emitter excitation circuit is ensured in all three operating phases (start-up phase, control phase, steady-state phase). In accordance with one of the recommendations for the selection of parameters (which is not limiting for the subject of the invention), the resistance R4 is significantly (in particular, at least 10 times) higher than the resistance R3, for example, the ratio R4/R3 is 60. This ensures only a slight change in the control voltage U4 during the pulse period.

The first output of the storage capacitor C2 of the control voltage regulation unit 22 is connected to the input of the amplifier stage N7. The output of the amplifier stage N7 provides the control voltage U4 and thus represents the output 2_3 of the control unit 2. In a preferred embodiment of the invention, the amplifier stage N7 has a gain of +1. This makes it possible to obtain a particularly simple circuit with a small number of electronic components.

The operating principle of the light emitter driving circuit shown in FIG. 1 is explained below. 3.

Switchable current source 1 can be connected and disconnected using the pulse signal U7. The output current level of current source 1 is set by voltage source N2, in this case the analog output of the DAC or microcontroller N1. In this case, possible changes in the output current level must be synchronized with the pulse signal in such a way that, as a result, a cyclically changing sequence of current pulses passes through the light-emitting load.

The light-emitting load V3 is powered by a high-efficiency switching regulator N8 with an output voltage U5. Its input voltage U6 is a supply voltage of, for example, 24 V DC.

To ensure high efficiency operation of the current source 1, it is necessary that the voltage drop between the first terminal V1_1 and the second terminal V1_2 of the voltage controlled component be as small as possible while in the first (open) switching state. For example, the voltage drop is approximately 1.5 V. In the adjusted state, the light emitter driving circuit in FIG. 3, the voltage between the first terminal V1_1 and the second terminal V1_2 of the voltage controlled component is set by the comparison unit 21, in particular based on the level of the constant voltage source U1.

The pulse regulator N8 is connected by its control input N8_3 to the output 2_3 of the control unit 2 and, therefore, to the output of the amplifier stage N7 of the control voltage regulation node 22. The output voltage U5 of the pulse regulator N8 decreases linearly, for example, when the control voltage U4 increases. Thus, the output voltage level of U5 can be adjusted using the control voltage level of U4. The level of control voltage U4 is regulated by control unit 2.

The pulse signal U7 is, for example, a binary signal and has a logic level "LOW" for switching switch element N3 to the second switching state and a logic level "HIGH" for switching switch element N3 to the first switching state. The specific voltage values for both levels, as well as the comparison of these levels with the switching states of the switching element N3, are not relevant to the invention.

In fig. 4 shows a second example of the implementation of the light emitter excitation circuit proposed in the invention, based on the principle presented in FIG. 2. To avoid unnecessary repetition, only differences from Fig. 1 are indicated. 3. Instead of the analog elements of the circuit shown in Fig. 3, the control loop in Fig. 4 is at least partially digital, the voltage drop being converted by an ADC 23 into a digital value that can be evaluated by the microcontroller 24. The microcontroller 24 then displays, in order to regulate the digital control voltage, the values output by the comparison node 21 and the control node 22 control voltage 22 shown in FIG. 1 and 3. The resulting digital control voltage is converted using the DAC 25 into an analog control voltage U4 and supplied to the control input 2_3 of the pulse regulator N8. The control unit 2 can be completely implemented in the form of a computer software product. Microcontroller N1 is preferably also a microcontroller 24 for regulating control voltage U4. In one embodiment, the DAC 25 and/or ADC 23 is part of the microcontroller 24. This allows the number of components to be reduced and power consumption to be reduced.

All excitation circuits for light emitters shown in Fig. 1-4 of this application have three temporary operating phases. The first operating phase is called the "start-up phase", the second - the "control phase", the third - the "steady state phase" (for more information, see Fig. 6-14). Below, the principle of operation of the light emitter excitation circuit proposed in the invention is explained in more detail with reference to a specific embodiment shown in FIG. 6-14.

In the startup phase, the required values of the input voltage and supply voltage are supplied to the corresponding components of the light emitter excitation circuit. In the case of the light emitter driving circuit shown in FIG. 3, in this first phase, the input voltage U6 is supplied to the switching regulator N8, the voltage U1 is supplied to the second input of the comparator N5, the voltage U2 is supplied to resistor R2, and the voltage U3 is supplied to resistor R3. In addition, the operating voltages required to power operational amplifier N4, comparator N5, amplifier N7, microcontroller N1 and DAC N2 are supplied. In this first phase, the control voltage U4 in each light emitter excitation circuit has an unregulated value, for example a value of 0 V, and the pulse signal U7 has a constant “LOW” level, as a result of which the switching element N3 switches to the second switching state for a long time, so that In this first phase, the current source 1 is permanently deactivated. In this case, the storage capacitor C1 of the comparison node 21 (see Fig. 3) is charged to the voltage level of the voltage source U2. The voltage level of the voltage source U2 exceeds the voltage level of the constant voltage source U1 at the negative input of the comparator N5. The (constant) logic level "LOW" of the pulse signal U7 at the second input D1_2 of the NAND gate D1 also maintains the output D1_3 of the NAND gate D1 at the logic level "HIGH". The HIGH signal at output D1_3 of the NAND gate D1 is applied to the control terminal of switch element N6 (in this case, an electronic switch) and switches switch element N6 to a state not shown in FIG. 3 and in which the first terminal of the resistor R4 is connected to the first terminal of the storage capacitor C2 of the control voltage regulation unit 22. As a result, the storage capacitor C2 is discharged or maintained in a discharged state, and the control voltage U4 decreases or remains at a minimum value. For example, if the minimum value of the control voltage U4 is 0 V, then the output voltage U5 is brought by the switching regulator N8 to the maximum value, which is usually 19 V DC.

If the pulse signal U7 first changes its logic state from logic "LOW" to logic "HIGH", then the second operating phase ("regulation phase") of the light emitter driving circuit shown in FIG. 1-4. In this case, the transition to the first switching state of the switching element N3 (current source 1 is connected) is carried out by means of a pulse signal U7. In this case, the voltage drop UDS across the MOS exceeds the difference between the DC voltage level U1 and the forward voltage Uf_V2 of diode V2 in the forward direction (Fig. 3). Thus, at the output of comparator N5 in FIG. 3, the original logic level "HIGH" is retained. The "HIGH" level of the comparator N5 and the "HIGH" level of the pulse signal U7 switch the output of the NAND gate D1 to the "LOW" logic level. This switching of the output of the NAND gate D1 affects the control output of switching element N6, causing the latter to switch (to the switching state shown in Fig. 3). Thus, the first terminal of resistor R3 is connected to the first terminal of capacitor C2, as a result of which storage capacitor C2 is charged through resistor R3. As the voltage across the storage capacitor C2 increases, the control voltage U4 also increases.

If, at the same time, a sufficient average current of, for example, 60 mA flows through the light-emitting load, then the output voltage U5 is reduced by the switching regulator N8 due to the negative proportionality coefficient between the control voltage U4 and the output voltage U5 in the light-emitting circuit shown in fig. 1-4. The voltage pulse sequence U7 and the input signal to the DAC N2 must be selected in such a way as to provide sufficient average current through the light-emitting load. As the output voltage of U5 decreases, the drain-to-source voltage UDS of the MOS decreases (UDS is the voltage drop between the first pin V1_1 and the second pin V1_2 of the MOS V1). If the voltage drop UDS (Fig. 3) is less than the difference between the DC voltage level U1 and the forward voltage Uf_V2 of diode V2, then the output of comparator N5 changes (throws) the comparison voltage from the first state (logical level "HIGH") to the second state (logical level "SHORT"). This flip switches the output D1_3 of the NAND gate D1 to the logic level "HIGH", causing switching element N6 to switch and connect the first terminal of resistor R4 to the first terminal of storage capacitor C2. As a result, the storage capacitor C2 is partially discharged again and the control voltage U4 is reduced. Both in the control phase and in the steady state phase of the light emitter driving circuit shown in FIG. 1-4, the pulse signal U7 is supplied to the switching element N3 for periodic (cyclic) connection and disconnection of current source 1. From this it follows that the light-emitting load 3 is turned on or off in accordance with the pulse signal. In this case, for example, flashes of light are generated, emitted to the measurement object in order to obtain and evaluate the characteristic reaction to them. This allows, for example, to verify the authenticity of machine-readable features on measurement objects.

During the period of each pulse (equal to the sum of the durations of the pulse itself and its pause), there is a slight charging and discharging of the storage capacitor C2 of the control voltage control unit 22 (Fig. 3). The average voltage on the storage capacitor C2 sets a stable value of the control voltage U4 and, accordingly, the output voltage U5 of the pulse regulator N8. This stable output voltage value of U5 ensures that current source 1 is controlled at the optimal operating point of the MOS current-voltage characteristic. The voltage value of the constant voltage source U1 determines the drain-source voltage UDS of the MOS in the steady state phase.

The second operating phase (regulation phase) ends when the average value of the control voltage U4 no longer increases monotonically over a long time, for example 10 pulse periods, in particular more than 5 ms, but only changes between two levels during this period of time. With the end of the regulation phase, the steady state phase begins - the actual operating phase of the light emitter excitation circuit.

Thus, using the control unit 2 of the light emitter excitation circuit shown in FIG. 1-4, a stable value of the output voltage U5 is achieved, which compensates for the nominal difference in the values of the forward voltage of the light emitters and fluctuations of this voltage during operation of the excitation circuit of the light emitters, caused by degradation or temperature fluctuations (heating/cooling) inside or outside the circuit, as well as voltage fluctuations pulse regulator N8. The increased power loss on the voltage controlled component V1 during the control phase of the light emitter drive circuit must be taken into account when selecting components and thermal design of the printed circuit board.

In fig. 5 is a flow chart (in a first embodiment) of the inventive method 100 for driving a light-emitting load by means of a light-emitting circuit of the type described above.

In a first step 101, a pulse signal is applied to the switching element to ensure that the control terminal of the voltage controlled component is connected to the voltage source during the pulse generation interval and not so connected during the pulse pause interval. In the next step 102, the control unit senses the voltage drop across the voltage controlled component. At step 103, using a comparison unit in the control unit, it is determined whether the voltage drop UDS exceeds the difference between the levels of the DC voltage U1 and the forward voltage Uf_V2 of the diode V2.

If the answer is "Yes", at step 103, the comparison voltage is switched to the first state (step 104). Then, in step 105, the control voltage is regulated (in this case upward) by the control unit 2, the control voltage being adjusted depending on the voltage drop across the voltage controlled component. In the next step 106, the control voltage is applied to the switching regulator, the output voltage of the switching regulator is reduced and output to drive the light emitting load, the output voltage preferably decreasing linearly with increasing control voltage. Reducing the output voltage results in a decrease in the voltage drop UDS.

If the answer is “No” at step 103, the comparison voltage is switched to the second state (step 107). Then, in step 108, the control voltage U4 is regulated (in this case downward) by the control unit 2, the control voltage being adjusted depending on the voltage drop across the voltage controlled component. In the next step 109, the control voltage is applied to the switching regulator, the output voltage of the switching regulator is increased and output to drive the light emitting load, the output voltage preferably increasing linearly as the control voltage decreases. Increasing the output voltage results in an increasing voltage drop UDS.

The method shown in the flowchart (FIG. 5) can be used as a method for operating (driving) any of the light emitter driving circuits shown in FIG. 1-4. In similar embodiments of the invention shown in FIGS. 1 and 3, all steps of the method are performed in parallel.

In fig. 6 is a first voltage/current timing diagram of selected signals in the light emitter driving circuit shown in FIG. 1-4, in particular in FIG. 3. Shown here is the characteristic of the regulated output voltage U5 of the pulse regulator N8 in the time interval from 0 to 4 seconds, the voltage characteristic at the first terminal V1_1 of MOS V1 in the time interval from 0 to 4 seconds, the voltage characteristic at the second terminal V1_2 of MOS V1 in the time interval from 0 to 4 seconds, characteristic of the control voltage U4 in the time interval from 0 to 4 seconds, characteristic of the voltage of the pulse signal U7 in the time interval from 0 to 4 seconds, characteristic of the voltage at the output D1_3 of logic gate D1 in interval from 0 to 4 seconds and the characteristic of the current through the current-measuring resistor R1 in the time interval from 0 to 4 seconds.

The voltage/current timing diagram shown in FIG. 6, is divided into three working phases. The time interval from 0 seconds to 0.4 seconds corresponds to the start-up phase mentioned above: U5 at 19 V, U4 at 0 V, U7 at a constant "LOW" level. Thus, current source 1 is deactivated in this operating phase, which is indicated by the value of 0 A of current I_R1 through current sense resistor R1. The current I_R1 corresponds to the current through the light-emitting load 3 and is therefore also called the light-emitting current in the following. According to FIG. 3, the “LOW” level of the pulse signal U7 results in a “HIGH” level at the output D13 of the NAND gate D1.

During this time period (start-up phase), the control voltage U4 of 0 V ensures that the switching regulator N8's regulated output voltage U5 reaches its maximum level of 19 V, due to the relationship (eg negative linear) between the voltages U4 and U5. Thus, the voltage drop between the first terminal V1_1 and the second terminal V1_2 of the voltage controlled component V1 (MOS) is maximum and in this first phase is, for example, 18 V. (Voltage characteristics were obtained by simulation. Due to the limitations of the simulation program the resulting voltage drop value is 1 V less. In the implemented circuit, the voltage drop is also 19 V.) Since the maximum drain-source voltage UDS is present in the startup phase, sufficient light emitter current can be ensured already during the formation of the first pulse (beginning of the regulation phase) regardless of selection of light-emitting load.

The second operating phase (control phase) begins with the first switching of the pulse signal U7 from the logic level "LOW" to the logic level "HIGH" at the time mark of 0.4 seconds. The current source 1 is activated in the pulse formation intervals of the pulse signal U7, as a result of which the light emitter current I_R1 is established, which is, for example, 1 A. Other current values are possible. The pulse signal U7 may be, for example, a burst signal and contain a predetermined number of individual pulses, also called bursts. An example of a pulse signal is shown in FIG. 8. The invention is not limited to the burst pulse signals shown in FIG. 8.

The second operating phase (regulation phase) ends at the time mark of 2.2 seconds, which can be seen from the end of the increase in control voltage U4 and which, in particular, is shown in Fig. 6 constant average voltage UDS (voltage difference at pins V1_1 and V1_2 of the MOS). In addition, the output D1_3 of the NAND gate D1 switches in the steady state phase at a lower frequency.

In fig. 7 shows the selected area (German: Bereichsauswahl - "Select area") shown in FIG. 6 of the voltage/current timing diagram, located between the time marks of 3.26 and 3.44 seconds (see also the designation "Site Selection" in Fig. 6). Shown here are the time characteristics of voltages and currents in the third operating phase (steady state phase). In this case, the voltage scale for U4 is increased 100 times and shifted to the indicated area of the diagram. In this representation, a slight increase and decrease in the control voltage U4 is clearly visible as a result of charging and discharging the storage capacitor C2 in accordance with FIG. 6, caused by switching output D13 of the NAND gate D1. Thus, in the time interval between the 3.3 and 3.41 second marks (that is, in the interval comprising approximately 5 packets), the control voltage of U4 is constantly reduced slightly, since the output D1_3 of the NAND gate D1 is constantly maintained at the logic level "HIGH". "despite the U7 pulse signal. This means that the first terminal of resistor R4 is connected to the first terminal of capacitor C2. The resulting time constant of the second RC circuit (formed from R4 and C2) significantly exceeds the interval of the U7 pulse signal packet. The repeated occurrence of the "LOW" level at the output D1_3 of the NAND gate D1 in the intervals between the time marks 3.28-3.3 seconds and 3.41-3.43 seconds leads to switching of the switching element N6 in such a way that the first terminal of the resistor R3 is connected to capacitor C2. This leads to charging of the storage capacitor C2 and, consequently, to an increase in the control voltage U4. As a result, U4 oscillates with low amplitude around the adjusted value.

In fig. 8 shows a selected section of the one shown in FIG. 7 of the voltage/current timing diagram, located between the time marks of 3.4 and 3.42 seconds (see also the designation "Site Selection" in Fig. 7). Thus, in FIG. 8, as in Fig. 7, shows the time characteristics of voltage and current in the third operating phase (steady state phase). In this case, the voltage scale for U4 is also increased 100 times and shifted to the indicated area of the diagram. Shown here as an example is a pulse signal U7 whose burst period is 21 milliseconds. A packet interval with this period length includes 30 individual pulses, each of which has a generation interval of 100 microseconds and a period duration of 500 microseconds. Therefore, the resulting pause of a single pulse is 400 microseconds. This sequence of 30 individual pulses is called a "burst", which is repeated at one pause interval.

In fig. Figure 8 shows the relationship between the pulse signal U7, the resulting voltage drop UDS (the difference between the voltage at the first pin V1_1 and the voltage at the second pin V1_2) and the current I_R1 through the current sense resistor R1. It can be seen that the last six individual pulses of the shown packet (the time interval between marks 3.412 and 3.415 seconds) cause the output D1_3 of the NAND gate D1 to be switched to another logical state, which leads to an increase in the control voltage U4.

In fig. 9 is a second voltage timing diagram of selected signals in the light emitter drive circuit shown in FIG. 1-4, in particular in FIG. 3. This shows the characteristic of the regulated output voltage U5 of the N8 pulse regulator in a time interval from 0 to 4 seconds, the voltage characteristic at the first terminal V1_1 of the MOS in the time interval from 0 to 4 seconds, the voltage characteristic at the second terminal V1_2 of the MOS in the time interval from 0 to 4 seconds 4 seconds and the characteristic of the control voltage U4 in the time interval from 0 to 4 seconds.

voltage diagram shown in Fig. 9, is also divided into three working phases. The time period from 0 seconds to 0.4 seconds corresponds to the startup phase mentioned above: U5 at 19 V, U4 at 0 V, U7 at a constant LOW level (not shown). Therefore, current source 1 is deactivated in this operating phase

During this interval (start-up phase), the control voltage U4 equal to 0 V ensures that the maximum level of the regulated output voltage U5 of the switching regulator N8 is 19 V, due to the relationship (for example, inversely proportional) between the voltages U4 and U5. Thus, the voltage drop between the first pin V1_1 and the second pin V1_2 of the voltage controlled component V1 (MOS) is maximum and in this first phase is also 19 V. (The voltage characteristic of U5 is shifted up by 0.4 V for better discrimination).

The second operating phase (control phase) begins with the first switching of the pulse signal U7 from the logical level "LOW" to the logical level "HIGH". Thus, the current source 1 is activated in the pulse generation intervals. The pulse signal U7 may be, for example, a burst signal and contain a predetermined number of individual pulses, also called bursts. Such a pulse signal is shown in Fig. 10-14.

The second operating phase in this operating mode ends at the time mark of 2.3 seconds, which can be seen from the end of the increase in control voltage U4 and which, in particular, is shown in Fig. 9 constant average voltage UDS (voltage difference at pins V1_1 and V1_2).

In fig. 10 shows the first section of the voltage timing diagram shown in FIG. 9. The location of this section is marked at the top of FIG. 10. The area shown in FIG. 10 is selected at the beginning of the second operating phase (control phase). It is obvious that there is a large voltage drop UDS (the difference between the voltages at pins V1_1 and V1_2), which corresponds to a large loss of power in the pulse generation interval. The voltage value V1_2 also has a constant amplitude even at the first pulses, so that in this interval the required light emitter current is provided.

In fig. 11 shows the second section of the voltage timing diagram shown in FIG. 9. The location of this section is marked at the top of FIG. 11. The area shown in FIG. 11 is selected at the beginning of the third operating phase (steady state phase).

In fig. 12 shows as an example a section of the voltage time diagram shown in FIG. 1 selected in the third operating phase (steady state phase). 9. Instead of the characteristic of the regulated output voltage U5 of the pulse regulator N8, the voltage characteristic at the output D1_3 of the NAND gate D1 is shown. The U4 voltage in this diagram was measured via AC coupling, so only the deviation from the average value is shown. As in FIG. 7, this shows the change in voltage U4 due to periodic charging and discharging of storage capacitor C2. For details, see the legend to FIG. 8.

In fig. 13 shows a section of the voltage timing diagram shown in FIG. 12. The location of this section is noted at the top of FIG. 13. Similar to Fig. 8, the pulse signal exemplified by V1_1 and V1_2 is displayed here as time-stretched. The U4 voltage in this diagram was measured via AC coupling, so only the deviation from the average value is shown. The last eight LOW pulses shown at output D1_3 of NAND gate D1 (FIG. 3), having a duration of approximately 4 microseconds, occur during a phase of the regulation process in which the voltage at C1 is almost identical to the voltage of the DC voltage source U1 . It can be seen that these last eight pulses with a logic level of "LOW" at the output D1_3 of the NAND gate D1 do not lead to a corresponding increase in the control voltage U4. The number of pulses with a "LOW" level at output D13 may vary due to the analogue control principle.

In fig. 14 shows a portion of the voltage timing diagram shown in FIG. 12. The location of this section is noted at the top of FIG. 14. The voltage difference UDS across the MOS is shown to be 1.44 V (difference between V1_1 and V1_2). This corresponds to the difference between the 2V DC voltage source U1 and the forward voltage of diode D2. This low voltage difference UDS results in minimal MOS power loss.

Within the scope of the invention, all described and/or depicted and/or claimed elements can be combined with each other in any way.

Claims (21)

1. Excitation circuit for light emitters, including: - a switching regulator (N8) containing a voltage input (N8_1) for supplying an input voltage (U6), a voltage output (N8_2) for outputting an adjustable output voltage (U5) intended to drive the light-emitting load (3), and an input (N8_3) control for supplying control voltage (U4), designed to regulate the level of output voltage (U5), - a current source (1) containing a switching element (N3) and a voltage-controlled component (V1) located in series with the light-emitting load (3), and a pulse signal (U7) is supplied to the control terminal (N3_3) of the switching element (N3), and in the pulse signal generation interval (U7), the switching element (N3) switches to the first switching state, in which the control terminal (V1_3) of the voltage-controlled component (V1) is connected to the voltage source (N2), and in the pause interval of the pulse signal (U7) the switching element element (N3) switches to a second switching state in which the control terminal (V1_3) of the voltage-controlled component (VI) is not connected to the voltage source (N2), - control unit (2), in which the first input (2_1) is connected to the first output (V1_1) of the voltage-controlled component (V1), the second input (2_2) is connected to the second output (V1_2) of the voltage-controlled component (V1), and the output ( 2_3) is connected to the control input (N8_3) of the switching regulator (N8) to supply control voltage (U4) to the switching regulator (N8), wherein the control voltage (U4) is adjusted depending on the voltage drop (UDS) between terminals (V1_1) and ( V1_2) voltage controlled component (V1). 2. The light emitter driving circuit according to claim 1, in which the control unit (2) contains a storage capacitor (C2) for increasing or decreasing the level of the control voltage (U4) depending on the voltage drop (UDS) across the voltage controlled component (V1), by which regulates the control voltage (U4). 3. The excitation circuit for light emitters according to one of the previous paragraphs, in which the control unit (2) contains a comparison unit (21), which at its output produces a comparison voltage, the level of which depends on the voltage drop (UDS) across the voltage-controlled component (V1), wherein the output of the comparison node (21) is connected to the input of the control voltage regulation node (22) of the control unit (2), which regulates the level of the control voltage (U4) depending on the comparison voltage, and the output of the control voltage regulation node (22) is connected to the input (N8_3 ) control of the pulse regulator (N8) to supply control voltage (U4). 4. The excitation circuit of light emitters according to claim 3, in which the control voltage (U4) is increased by the control voltage regulation unit (22), if the comparison voltage is at the first level, and the control voltage (U4) is reduced by the control voltage regulation unit (22), if the voltage comparison has a second level, different from the first. 5. Excitation circuit for light emitters according to one of paragraphs. 3 or 4, in which the comparison unit (21) contains a comparator (N5) and a constant voltage source (U1), the first input of the comparator (N5) is connected to the first terminal (V1_1) of the voltage-controlled component (V1), the second input of the comparator (N5 ) is connected to the first terminal of the constant voltage source (U1), and the second terminal of the constant voltage source (U1) is connected, as a second input (2_2) of the control unit (2), to the second terminal (V1_2) of the voltage-controlled component (V1). 6. The light emitter excitation circuit according to claim 5, in which in the line connecting the first terminal (V1_1) of the voltage-controlled component (V1) and the first input of the comparator (N5), a diode (V2) is provided, the anode of which is connected to the first input of the comparator ( N5), and the cathode is connected, as the first input (21) of the control unit (2), to the first output (V1_1) of the voltage-controlled component (V1). 7. The excitation circuit for light emitters according to claim 6, in which the first output of the storage capacitor (C1) of the comparison unit (21) is connected to the anode of the diode (V2), and the second output is connected to the second input (2_2) of the control unit (2). 8. Excitation circuit for light emitters according to one of paragraphs. 2-7, in which the storage capacitor (C2) of the control unit (2) is part of the first RC circuit, the time constant of which takes such a value that the highest rate of change of voltage of the storage capacitor is less than the ratio of the lowest rate of change of the output voltage and the proportionality coefficient of the pulse regulator . 9. The excitation circuit for light emitters according to claim 8, in which the storage capacitor (C2) of the control unit (2) is also part of the second RC circuit, the time constant of which takes such a value that the output voltage of the pulse regulator increases in pulse pauses only by a small amount size. 10. The light emitter excitation circuit according to claim 9, in which the first RC circuit or the second RC circuit is selected depending on the comparison voltage using the switching element (N6) of the control voltage regulation unit (22). 11. An optical meter for recognizing machine-readable security features on valuable documents, comprising at least one light emitter (V3) as a light-emitting load (3) for illuminating the security feature and a light emitter drive circuit according to one of the previous paragraphs for activating the light emitter (V3) . 12. A device for illuminating a security feature of a valuable document, containing a light emitter excitation circuit according to one of claims. 1-10 and light-emitting load (3). 13. A device for checking valuable documents, in particular banknotes containing a machine-readable security feature, containing an optical meter according to claim 11. 14. Method (100) for activating a light-emitting load (3) by means of a light-emitter excitation circuit according to one of claims. 1-10, including the following steps: - supplying (101) a pulse signal (U7) to the control terminal (N3_3) of the switching element (N3) to connect the control terminal (V1_3) of the voltage-controlled component (V1) to the voltage source (N2), - removal (102) of the voltage drop (UDS) between the terminals (V1_1) and (V1_2) of the voltage-controlled component (V1) by means of the control unit (2), - regulation (105, 108) of the control voltage (U4) by means of the control unit (2), wherein the control voltage (U4) is regulated depending on the voltage drop (UDS) on the voltage-controlled component (VI), - supplying a control voltage (U4) to a switching regulator (N8) and an adjustable output voltage output (U5) to drive the light-emitting load (3) using the control voltage (U4) to regulate (106, 109) the output voltage level (U5) , wherein the control voltage (U4) is preferably inversely proportional to the output voltage (U5).

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