RU2816836C1 - Coprocessor in cryptography processing systems - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: coprocessor in cryptography processing systems comprises an arithmetic and logical unit, a microcode generator, a second arithmetic and logical unit, a control unit, an interface and four multiplexers.

EFFECT: broader functional capabilities of the digital signal processor.

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Description

The technical field to which the invention relates.

The invention relates to computer technology and can be used in integrated devices, namely in digital signal processors with the VLIW (Very Long Instruction Word) command system, that is, in the command format with a large number of bits per word.

State of the art.

In known specialty processors, for example, according to US patent US4991169, blocks and assemblies are designed exclusively for a specific application. In another digital signal processor, known from US patent US8543635, to implement the transfer function (Z-transform), a sequence of adder-subtractors, delays (registers) is used to implement filter functions. The device, described in US patent US4821294, uses a code correlator, a down converter, and a separate tracking processor.

The closest to the proposed device is the processor described in RF patent No. 2694743 dated 02/08/2019 according to classification G06F 5/01 (2019.05); G06F 9/38 (2019.05); G06F 15/00 (2019.05).

This device (described in RF patent No. 2694743) is a digital-signal processor, includes: an analog-to-digital converter, a desimation filter, a test register in front of the operating part of the processor, a block of arithmetic and logical operations connected by the first inputs and outputs in series, and the input of the analog-to-digital The converter serves as the input of a digital signal processor, a reprogrammable memory, a coefficient memory block, a block of instructions, wherein the first output of the reprogrammable memory is connected to the first input of the coefficient memory block, the second output of the reprogrammable memory is connected to the second input of the analog-to-digital converter, the third output of the reprogrammable memory is connected to the first input of the block of instructions, and the first input-output of the reprogrammable memory is used to record and control the recorded information in the memory.

The problem solved by the invention is to expand the functionality of the digital signal processor.

Disclosure of the invention.

The technical result is to ensure the universality of the digital signal processor for its rapid reprogramming when implementing specific tasks.

To solve the problem and achieve a technical result, the claimed coprocessor in cryptography processing systems includes two arithmetic and logical units (ALU), a memory unit, a microcode generator, a control unit, an interface, and multiplexers. The output of the microcode generator (VLIW) is connected to the input (ALU1), to the input (ALU2), to the input of the memory unit, to the input of the interface, and the output of which is connected to the input of the microcode generator. The microcode generator inputs are connected to the outputs of ALU1 and ALU2, respectively. The outputs of ALU1 and ALU2 are connected to the inputs of the multiplexers. The input of the multiplexer is connected to the input of the multiplexer, the input of which is connected to the input of the multiplexer. The inputs of the multiplexers are connected. The multiplexer input is connected to the output of the memory block. The inputs of the multiplexers are combined, and the inputs of these multiplexers are interconnected. The inputs of the multiplexers are connected to the output of ALU2. The output of the memory block is connected to the input of the multiplexer, to the input of the multiplexer, to the input of the multiplexer and to the input of the interface, the input of which is connected to the output of the memory block. The output of the interface is connected to the inputs of the multiplexers and to the inputs of the multiplexers, respectively. Inputs/outputs connect the microcode generator and the control unit. The interface input/output provides connection to external devices. The outputs of the multiplexers are connected to the inputs of ALU 1, respectively, and the outputs of the multiplexers are connected to the inputs of ALU 2, respectively.

The advantages and features of the present invention are explained using an embodiment with reference to the figures.

Brief description of graphic materials.

The claimed device is illustrated in Fig. (1 and 2), on which:

- fig. 1 - Functional diagram of the coprocessor;

- fig. 2 - Algorithm for writing data from the ALU to RAM The functional diagram of the coprocessor (Fig. 1) contains two arithmetic and logical units (ALUs) 1 and 2, memory unit 3, microcode generator 4, control unit 5, interface 6, multiplexers 7, 8, 9, 10, AND and 12. The output of the microcode generator 13 (VLIW) is connected to input 14 (ALU1), to input 15 (ALU2), to input 16 of memory block 3, to input 17 of interface 6, and output 18 of which is connected to the input 19 of microcode generator 4. Inputs 20 and 21 of microcode generator 4 are connected to 22 and 23 outputs of ALU1 1 and ALU2 2, respectively. Outputs 24 and 25 of ALU1 1 and ALU2 2 are connected to inputs 26 and 27 of multiplexers 11 and 12, respectively. Input 28 of multiplexer 11 is connected to input 27 of multiplexer 12, input 29 of which is connected to input 26 of multiplexer 11. Inputs 30 and 31 of multiplexers 11 and 12 are connected. Input 32 of multiplexer 11 is connected to output 33 of memory block 3. Inputs 34 and 35 of multiplexers 8 and 10 are combined, and inputs 36 and 37 of these multiplexers are connected to each other. Inputs 38 and 39 of multiplexers 7 and 9 are connected to output 25 of ALU 2. Output 40 of memory unit 3 is connected to input 4 of Multiplexer 12, to input 42 of multiplexer 7, to input 43 of multiplexer 9 and to input 44 of interface 6, input 45 of which is connected to output 33 of memory block 3. Output 46 of interface 6 is connected to inputs 30 and 31 of multiplexers 11 and 12 and to inputs 36 and 37 of multiplexers 8 and 10, respectively. Inputs/outputs 47 and 48 connect the microcode generator 4 and the control unit 5. Input/output 49 of interface 6 provides connection with external devices. The outputs of multiplexers 7 and 8 are connected to inputs 50 and 51 of ALU 1, respectively, and the outputs of multiplexers 9 and 10 are connected to inputs 52 and 53 of ALU 2, respectively.

Implementation of the invention.

The digital signal processor (Fig. 1) operates as follows.

A command is received at input/output 49 from an external device, which appropriately generates control signals from output 18 of interface 6 to input 19 of microcode generator 4. Each command is converted into a sequence of multi-bit microcommands (VLIW) in accordance with the command algorithm, while the microcommand is divided into fields for each coprocessor block, which allows simultaneous operation of blocks and memory. These control signals from the microcode are supplied to inputs 14, 15, 16 and to input 17 of ALU1, ALU2, memory unit 3, to input 48 of control unit 5 and input 17 of interface 6, respectively. In ALU1 and ALU2 operations are performed in accordance with the operations table. For example, as presented in Table. 1. Shift operations are also performed in ALU1 and ALU2 (not presented in the description). In this case, the operands can be selected from different sources. Operand A for ALU 1 is determined through multiplexer 7 - it can be either a read operand from memory block 3 from output 40 to input 42 of multiplexer 7, or to input 38 from output 25 of ALU2, respectively. Operand B for ALU1 is determined through multiplexer 8 - in this case, it is either from output 33 of memory block 3 to input 34, or to input 36 from output 46 of interface 6. Similarly for ALU2 - operand A is determined through multiplexer 9 or from output 40 of memory block 3 to input 43 of multiplexer 9, or from output 25 of this ALU2 to input 39 and, accordingly, to input 52 of the operating part of ALU2. Operand B through multiplexer 10 from the output of interface 6 (output 46) to input 37 or from output 33 of memory block 3 is supplied to input 33 of ALU2. Operations in ALU1 and ALU2 are performed in parallel (if necessary, and the corresponding microinstruction). From outputs 22 (ALU1) and 23 (ALU2), the status of the registers (not shown in the figure) are sent to inputs 20 and 21 of microcode generator 4, respectively. Depending on the state of these register statuses, a conditional transition occurs in the subroutines. In this case, in control block 5, through inputs/outputs 47 and 48, the conditional transition in subroutines is controlled. The memory block is two-port - information can be received at inputs 54 and 55, coming from multiplexers 11 and 12, while through multiplexer 11 information comes from interface 6 to input 30, or from output 33 of the same memory block, or from output 24 of ALU1 to input 26, or from output 25 of ALU2 to input 28 of multiplexer 11. The inputs of multiplexer 12 - 27, 29, 31 and 41 receive data with the corresponding microcommand - from output 24 of ALU1, from output 25 of ALU2, from output 46 of the bis interface of output 40 memory block respectively.

Figure 2 shows the algorithm for controlling data writing to memory block 3 (RAM) using the instruction bus (micro-instructions):

- First, the operation permission signal and the first instruction containing the operation for ALU1(2) are set (circle number 1);

- Then, the result of the first instruction is written to the accumulator ALU1 and/or ALU2 and the second instruction is generated with a signal to write to memory block 3 (RAM) (circle number 2);

- Then, some other instruction is generated, the result of the second instruction is the recording of data from the ALU 1(2) battery into a cell of memory block 3 (RAM) and their appearance at the output of memory block 3 (RAM) (circle number 3).

Claims (8)

A coprocessor in cryptography processing systems, containing an arithmetic and logical unit, a microcode generator, characterized in that it contains: second arithmetic and logical block, control block, interface and four multiplexers, in this case, the output of the microcode generator is connected to the corresponding inputs of the first and second arithmetic and logical blocks, a memory block and an interface, the first input of which is connected to the first output of the memory block, to the first input of the first multiplexer of the first arithmetic block, the first input of the first multiplexer of the second arithmetic and logical block and the first input of the first multiplexer of the memory block, the second input of the interface is connected to the second output of the memory block, to the first input of the second multiplexer of the memory block, the first input of the second multiplexer of the second arithmetic and logical block and the second input of the second multiplexer of the second arithmetic and logical block, the output of which is connected to the second input of the first multiplexer of the first arithmetic and logical block block, the second input of the first multiplexer of the second arithmetic and logical block and the corresponding inputs of the first and second multiplexers of the memory block, the other inputs of which are connected to the output of the first arithmetic and logical block, the input-output of the microcode generator is connected to the corresponding input-output of the control unit, the second output of the interface is connected to the corresponding input of the microcode generator, and the input-output of the interface is an external input-output of the coprocessor.

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