RU2411575C1 - Connected portable coprocessor with varied system of commands and method of its application - Google Patents

Abstract

FIELD: information technologies. ^ SUBSTANCE: device comprises joined programmable logical integral circuit, microcontroller and controller of peripheral bus. Microcontroller is arranged with the possibility of analysis at the stage of initialisation of configuration pack received from central processor, and re-configuration of programmable logical internal circuit, and with the possibility to forward arguments of procedure call, included into composition of "execution request" pack received from central processor, to the inlet of programmable logical integral circuit. ^ EFFECT: higher efficiency of processor operation by simplification of integration of coprocessor activity control procedures into existing software of basic digital computer. ^ 3 cl, 3 dwg

Description

This invention relates to the field of computer technology, namely to plug-in portable coprocessors with a variable system of instructions and methods for their use, and can be used in digital computing systems, especially in low-power and portable ones, such as laptops, netbooks, laptop computers, etc. . From time to time, users of such devices need to perform a variety of resource-intensive, but at the same time well-parallelizable tasks (for example, in the course of performing specialized functions of graphic editors or cryptographic software). In this case, the lack of performance is especially felt.

The existing means of increasing the speed of well-parallelizable computing tasks provided by the graphic processors (GPUs) of high-level video adapters are in most cases unavailable, since in the vast majority of cases only low-cost (specialized) integrated GPU versions are used that do not have such functionality.

The instruction sets of modern central processors provide many extensions that allow for parallelism at the data level (the so-called SIMD - "single instruction, multiply data" instructions), focused on the requirements of multimedia applications, but their use is not so effective due to the impossibility of simultaneously processing really large data volumes (more than 10-15 "machine words"). In addition, the instructions provided by such extensions form an orthogonal set of basic commands, which makes it necessary to execute a large sequence of instructions to perform complex operations (for example, cryptographic transformation of a data block). The execution of such a set of operations requires a large amount of time, which leads only to a small increase in productivity due to parallelization, especially in the case of scalar organization of the computing pipeline of the central processor (such systems are often used in embedded and inexpensive digital computers), which does not provide additional execution units for instructions multimedia extensions.

To carry out complex, user-defined instructions, without the need for a central processor, coprocessors with a variable system of instructions are used.

Known tunable coprocessor, is shown in patent US 6298366 [1], designed to perform multiple operations of multiplication with accumulation, which contains several pairs of multipliers, several adders receiving the corresponding output data from the multipliers, and at least one secondary adder receiving the output data from primary adders. One multiplier from each pair has a fixed left shift block of the multiplication result. Another multiplier in each pair contains a right shift block of the multiplication result. At the output of the first multiplier is a multiplexer that transfers for further processing either the result of the multiplication after the shift, or a sign extension of the result. At the output of the second multiplier is a multiplexer that transfers for further processing either the result of the multiplication, or its version with a shift to the right, or one of the operands of the multiplication block. Data from the outputs of the multiplexers is fed to the primary set of adders. The intermediate result is then transmitted to the secondary summing unit.

The disadvantage of this coprocessor is that it lacks the possibility of using a general-purpose programmable logic integrated circuit (PLD). The process of reconfiguring the computing pipeline of the device proposed in the patent is limited due to the fixed structure of internal elements - only a small set of arithmetic operations can be organized into a single high-level instruction. The patent also does not indicate the possibility of organizing a coprocessor as an independent device connected to the peripheral bus of a digital computer.

US Pat. No. 6,467,009 [2] describes a reconfigurable coprocessor system comprising a processor and a programmable logic integrated circuit interconnected by an internal system bus and located on a single integrated circuit.

The disadvantage of this analogue is that the coprocessor system is located on a single integrated circuit (substrate) with a central processing unit (CPU) and an internal system bus. This makes the coprocessor a permanent element of the system, which significantly reduces its portability and makes it impossible to connect it only when necessary.

Closest to the claimed invention is the coprocessor described in patent application US 2008/0028186 [3] and intended for accelerated computation, which contains a user-programmable gate array (FPGA - Field Programmable Gate Array) and programmable logic integrated circuit (PLD - Programmable Logic Device), connected to the FPGA and designed to configure it. Long-term memory is connected to the PLD and is designed to store the initial stream of binary FPGA configuration data. After completing the initial configuration cycle, the FPGA gate array communicates directly with at least one microprocessor via a dedicated microprocessor bus. This coprocessor is selected as a prototype of the claimed invention.

The disadvantage of organizing a prototype coprocessor is the inability to connect it to the peripheral bus of a digital computer, which leads to the inability to achieve high portability and dynamic connection on demand. Moreover, the proposed direct connection “central processor - coprocessor” and “coprocessor - memory” via the microprocessor bus makes it impossible to use the invention for portable low-performance systems such as laptops or laptops (they do not allow the user to connect devices to the microprocessor bus from the outside).

The objective of the claimed invention is the creation of a plug-in portable coprocessor with a variable system of instructions designed to increase the speed of calculations, for example, by transferring well-parallelized tasks from the central processor of a digital computer to a coprocessor with a variable high-level system of commands, by simplifying the integration of procedures for controlling the activity of the coprocessor in an existing software solution of a basic digital computer, as well as improved functionality and usability use due to the possibility of connecting the coprocessor to the base digital computer, if desired, through one of the peripheral buses.

The technical result is achieved by creating a portable portable coprocessor with a variable system of instructions, containing interconnected programmable logic integrated circuit, a microcontroller and a peripheral bus controller, and the peripheral bus controller is configured to dynamically connect to a digital computer via a peripheral bus and with the possibility of data transfer between the coprocessor and the digital computer, while the microcontroller is configured to analyze a, at the initialization stage, the configuration package received from the central processor and the reconfiguration of the programmable logic integrated circuit or its part in accordance with the configuration package data, and at the program execution stage in a digital computer, when the procedure transferred to the coprocessor is necessary, the microprocessor is executed with the ability to submit arguments to the procedure call, which are part of the package "request execution", received from the central processor, to the input of the programmable log integrated circuit, with the possibility of initiating the execution of the programmable logic integrated circuit, with the ability to notify the central processor of the completion of the procedure, as well as the ability to obtain the results of the requested procedure from the outputs of the programmable logic integrated circuit and transmitting the packet of the results of the procedure to the central processor, this programmable logic integrated circuit is configured to perform the procedure under control a microprocessor element and with the possibility of feeding the execution results to the outputs associated with the microprocessor.

For a portable portable coprocessor to function with a variable system of commands, it is important that the “execution request” package contains the name of the procedure, a set of arguments, and a unique call identifier for cases when more than one command is in the queue for execution by the coprocessor.

The technical result is also achieved by developing a method of using a plug-in portable coprocessor with a variable system of commands. In accordance with the claimed method provides for the following operations:

- attach the coprocessor to the peripheral bus of a digital computer containing a central processor;

- initialization is performed, at the same time, at least one configuration packet of the programmable logic integrated circuit of the coprocessor is formed in the digital computer, which consists of the associated bit streams of the configuration of the programmable logic integrated circuit and the name of the procedure;

- send a configuration packet to the coprocessor through the central processor;

- analyze the configuration package by means of the microcontroller of the coprocessor and reconfigure the programmable logic integrated circuit or its part in accordance with the data of the configuration package;

- when executing a program in a digital computer, when it is necessary to perform the procedure transferred to the coprocessor from the digital computer, the following operations are performed:

by means of the central processor send to the coprocessor the package "request execution" from the application;

by means of the microcontroller of the coprocessor, the arguments of the procedure call are included, which are part of the package "request execution", received from the central processor, to the input of the programmable logic integrated circuit, initiate the execution of the procedure by the programmable logic integrated circuit;

by means of a programmable logic integrated circuit under the control of a microprocessor perform the procedure;

through the microcontroller notify the central processor of the completion of the procedure;

by means of the central processor send a packet "query results" to the coprocessor;

by means of the coprocessor microcontroller, the results of the requested procedure are obtained from the outputs of the programmable logic integrated circuit and the result package of the procedure is transmitted to the central processor,

however, in the operations described above, data is transferred between the processor and the coprocessor on the peripheral bus via the peripheral bus controller.

For a better understanding of the claimed invention the following is a detailed description with the corresponding drawings.

Figure 1. A portable coprocessor circuit with a variable instruction system made in accordance with the invention.

Figure 2. Functional diagram of a portable coprocessor with a variable system of commands from the side of a digital computer, made according to the invention.

Figure 3. Functional diagram of a portable coprocessor with a variable instruction system from the coprocessor side, made according to the invention.

The coprocessor 100 consists of three main elements (Fig. 1): peripheral bus interface controller 101 (PBIC - Peripheral bus interface controller), which allows the central processor to communicate with peripheral bus 104, microcontroller 102 (MD - Microcontroller device), which is responsible for reconfiguring a programmable logic integrated circuit and processing input and output data packets, and programmable logic integrated circuit 103 (PLD - Programmable Logic Device), which can be performed in the form of CPLD, FPGA, etc. and is responsible for parallel, using or not the computing pipeline approach, the execution of a variable set of instructions in accordance with a given connection of internal logic elements.

The claimed portable coprocessor with a variable system of instructions is used as follows (Fig.1-3). First, a coprocessor 100 is connected to the peripheral bus 104 of the digital computer. Before setting the task for execution by the coprocessor 100, initialization is performed, and the following operations are performed. Potentially parallelizable blocks of program code are converted into a package (file) of the configuration of the programmable logic integrated circuit 103 of the coprocessor using one of the following methods: by translating the application code from a high-level programming language (PL - programming language) to the hardware organization description language (HDL - hardware description language) and then into the bitstream settings of the programmable logic integrated circuit 103; by writing HDL code manually based on the required algorithm and using the HDL translator, or through available software. The configuration package (file) contains the bit stream for setting the programmable logic integrated circuit, namely, information about the connection of the internal digital elements necessary for the correct execution of the requested procedure. If the application requires the implementation of several different procedures using the coprocessor 100, then several configuration files or one combined configuration file containing the description of all necessary procedures are sequentially generated.

Then the application sends through the central processor the generated configuration package, consisting of the mapped configuration bitmaps of the programmable logic integrated circuit and the procedure names, to the coprocessor (using the access to the peripheral bus 104 provided by the operating system or a manually written subroutine) (step 200).

Having received the configuration packet through the peripheral bus 104 of the digital computer using PBIC, the microcontroller 102 analyzes it and configures the programmable logic integrated circuit 103 or part of it in accordance with the received data (step 304). From this moment on, the programmable logic integrated circuit 103 or its part can execute the required set of commands (procedures) independently.

Upon further execution of the program, when it is necessary to execute the procedure passed to the coprocessor 100, the application sends the “execution request” packet to the coprocessor 100 through the central processor (the “execution request” packet contains the procedure name, a set of arguments, and a unique call identifier) (step 202).

The microcontroller 102 analyzes the “request for execution” packet and schedules its execution by a pre-configured programmable logic integrated circuit 103 (step 306).

After completing the requested procedure using the programmable logic integrated circuit 103, the microcontroller 102 notifies the requestor (source application) using the commands provided by the peripheral bus protocol 104 (for example, using a system interrupt) (step 306).

Then, the application can request the results of the procedure call from the coprocessor 100 using the “request results” package (step 204). The execution results are returned by the coprocessor 100 via the peripheral bus 104 using the “execution results” packet, which contains the unique call identifier obtained at the execution request stage and the results of the procedure call (step 307). After receiving the results of the execution, the central processor proceeds to the execution of the following procedures using these results (step 206).

The claimed invention provides an additional increase in computational performance for tasks that can be executed in parallel (which often arise, for example, during the performance of specialized functions of graphic editors or cryptographic software).

Due to the simplified interaction protocol for the effective use of the inventive device, only a small change in the code of the source software product is required, therefore, many software manufacturers can adapt their products to support the coprocessor.

It should be noted that the above embodiment of the invention is set forth mainly to illustrate the invention, and it is clear to those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and meaning of the present invention disclosed in the attached claims.

Claims (3)

1. A portable portable coprocessor with a variable system of instructions, containing interconnected programmable logic integrated circuit, a microcontroller and a peripheral bus controller, the peripheral bus controller being configured to dynamically connect to a digital computer via a peripheral bus and with the possibility of data transfer between the coprocessor and digital computer, while the microcontroller is configured to analyze at the stage of initialization of the configuration package, received from the central processor, and reconfiguring the programmable logic integrated circuit or part thereof in accordance with the configuration package data, the microprocessor being configured to supply, at the program execution stage in a digital computer, when it is necessary to execute the procedure passed to the coprocessor, the procedure call arguments included in the composition of the package "request execution", received from the central processor, to the input of a programmable logic integrated circuit, with the possibility of initiating the execution of the procedure by a programmable logic integrated circuit, with the possibility of notifying the central processor of the completion of the procedure, as well as the possibility of obtaining the results of the requested procedure from the outputs of the programmable logic integrated circuit and transmitting the packet of the results of the procedure to the central processor, while the programmable logic integrated circuit is executed with the ability to perform the procedure under the control of the microprocessor and with the possibility of filing a cut ltats run on outputs associated with a microprocessor. 2. A plug-in portable coprocessor with a variable system of instructions according to claim 1, characterized in that the “execution request” package contains the name of the procedure, a set of arguments, and a unique call identifier required if more than one command is in the queue for the execution of the coprocessor. 3. A method of using a plug-in portable coprocessor with a variable system of commands, which consists in the following operations: attach the coprocessor to the peripheral bus of a digital computer containing a central processor; perform initialization, forming at the same time in a digital computer, at least one configuration package of the programmable logic integrated circuit of the coprocessor, which consists of matched bit streams of the configuration of the programmable logic integrated circuit and the name of the procedure; send a configuration packet to the coprocessor via the central processor; analyze the configuration package by means of the coprocessor microcontroller and reconfigure the programmable logic integrated circuit or part thereof in accordance with the data of the configuration package; when executing a program in a digital computer, when it is necessary to carry out the procedure transferred to the coprocessor from the digital computer, the following operations are performed: send the “execution request” packet from the application to the coprocessor using the central processor; submit, by means of the coprocessor microcontroller, the arguments of the procedure call, which are part of the “execution request” packet received from the central processor, to the input of the programmable logic integrated circuit and initiate the execution of the procedure by the programmable logic integrated circuit; performing the procedure by means of a programmable logic integrated circuit under the control of a microprocessor; notify the central processor via the microcontroller of the completion of the procedure; send to the coprocessor by means of the central processor a packet "query results"; receive, by means of a coprocessor microcontroller, the results of the requested procedure from the outputs of the programmable logic integrated circuit and transmit the packet of the results of the procedure to the central processor, while in the above operations, data is transferred between the processor and the coprocessor via the peripheral bus via the peripheral bus controller.

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