RU2804442C1 - Semiconductor device and method for its manufacture - Google Patents

Abstract

FIELD: semiconductors.

SUBSTANCE: semiconductor device and a method for its manufacture. The semiconductor device comprises an active region located in a semiconductor substrate and including a central region and a peripheral region surrounding the central region; the first stressed layer formed in the peripheral region by the method of penetration and including at least the first subsection, the second subsection, the third subsection, and the fourth subsection, while the first subsection and the third subsection are separately located on two sides of the central region in the first direction, and the second subsection and the fourth subsection are separately located on the other two sides of the central region in the second direction, the first direction being different from the second direction; and a shutter located on the active area, extending in the first direction and covering at least a part of the central area, at least a part of the first subsection, and at least a part of the third subsection.

EFFECT: improvement of the semiconductor operation.

10 cl, 16 dwg

Description

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is made based on Chinese Patent Application No. 202110610067.7 and claims the benefit of that application filed June 1, 2021, the disclosure of which is incorporated by reference in its entirety herein.

TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, a semiconductor device and a method for manufacturing the same.

BACKGROUND OF THE ART

[0003] With the continuous reduction in the size of microelectronic devices, low mobility of silicon material has become a major factor that limits the performance of microelectronic devices.

[0004] It has been discovered that carrier mobility can be improved by placing stressed layers in semiconductor substrates. However, if the location of the stressed layer is different, the carrier mobility is different. Consequently, the method of arranging the stressed layer to obtain higher carrier mobility is becoming a research topic for semiconductor device manufacturers.

DISCLOSURE OF THE INVENTION

[0005] Embodiments of the present disclosure provide a semiconductor device comprising: an active region, a first stressed layer, and a gate.

[0006] The active region is located in the semiconductor substrate and includes a central region and a peripheral region surrounding the central region.

[0007] The first stress layer is formed in the peripheral region by an insertion method, wherein the first stress layer includes at least a first sub-section, a second sub-section, a third sub-section and a fourth sub-section. The first sub-region and the third sub-region are separately located on two sides of the central region in the first direction, and the second sub-region and the fourth sub-region are separately located on the other two sides of the central region in the second direction. The first direction is different from the second direction.

[0008] The gate is located on the active region, extends in a first direction, and covers at least a portion of the central region, at least a portion of the first subregion, and at least a portion of the third subregion.

[0009] Embodiments of the present disclosure further provide a method for manufacturing a semiconductor device, including the following steps.

[0010] Providing a semiconductor substrate and forming in the semiconductor substrate an active region including a central region and a peripheral region surrounding the central region.

[0011] Forming a first stressed layer in a peripheral region by an insertion method, wherein the first stressed layer includes at least a first sub-section, a second sub-section, a third sub-section and a fourth sub-section. The first sub-region and the third sub-region are separately located on two sides of the central region in the first direction, and the second sub-region and the fourth sub-region are separately located on the other two sides of the central region in the second direction. The first direction is different from the second direction.

[0012] Forming on the active region a gate extending in a first direction and covering at least a portion of the central region, at least a portion of the first subregion, and at least a portion of the third subregion.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In FIG. 1A and 1B are schematic diagrams of a known semiconductor device.

[0014] In FIG. 2A-2C are schematic diagrams of a semiconductor device according to one embodiment of the present disclosure.

[0015] In FIG. 3 is a schematic diagram of a central region and a peripheral region according to one embodiment of the present disclosure.

[0016] In FIG. 4 is a schematic diagram of a semiconductor device having an annular first stressed layer, according to one embodiment of the present disclosure.

[0017] In FIG. 5A-5B are schematic diagrams of a semiconductor device having a second stressed layer, according to one embodiment of the present disclosure.

[0018] In FIG. 6 is a schematic diagram of a semiconductor device having a first source/drain expansion region and a second source/drain expansion region, according to one embodiment of the present disclosure.

[0019] In FIG. 7 is a flow diagram of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0020] In FIG. 8A-8E are schematic diagrams showing a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

IMPLEMENTATION OF THE INVENTION

[0021] The exemplary embodiments presented in the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure may be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided to facilitate a more complete understanding of the present disclosure and to provide the full scope of protection of the present invention to those skilled in the art.

[0022] In the following description, numerous specific details are set forth in order to provide a more complete understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be made without one or more of these details. In other examples, certain technical features known in the art are not described to avoid confusion with the present disclosure, i.e. not all features of the actual embodiments are described herein, and known functions and structures are not described in detail.

[0023] In the accompanying drawings, the dimensions of layers, regions, elements and their relative sizes may be enlarged for clarity. Like reference numerals denote like elements throughout the specification.

[0024] Of course, when an element or layer is referred to as being "on", "adjacent to", "connected to" or "attached to" other elements or layers, it may be directly placed on or adjacent to other elements or layers , connected to or attached to other elements or layers, or intermediate elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly attached to" other elements or layers, it means that there are no intermediate elements or layers. It will be appreciated that while the terms "first", "second", "third" and the like may be used to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts shall not be limited by these terms. These terms are used only to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Thus, without departing from the descriptions of the present disclosure, the first element, component, region, layer or portion discussed below may be represented as a second element, component, region, layer or portion. When a second element, component, region, layer, or portion is discussed, it does not mean that the first element, component, region, layer, or portion is necessarily present in the present disclosure.

[0025] Spatial relationship terms such as, for example, “below...”, “under...”, “lower,” “below...”, “above...”, “upper,” etc. may be used herein for ease of description to describe the relationship between one element or feature shown in the drawings and other elements or features. Of course, in addition to the orientations shown in the drawings, spatial relationship terms are intended to include various orientations of devices in use and operation. For example, if the device in the drawings is inverted, elements or features described as "below" or "under" or "down" relative to other elements will be located "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both orientations, i.e. "above" and "below". The device may be oriented in other ways (rotated 90° or other orientations), and spatial descriptors used herein are interpreted accordingly.

[0026] The term used herein is intended to describe specific embodiments only and is not intended to be used as a limitation of the present disclosure. When used herein, singular indicators such as “a/an,” “one,” and “said” are exclusively intended to include the plural unless the context clearly indicates otherwise. It should also be understood that the terms “consists of” and/or “includes” as used in this specification define the presence of the described features, integers, steps, operations, elements, components and/or groups. As used herein, the term “and/or” includes any and all combinations of the respective items listed.

[0027] It is known that introducing a tensile force into the channel of an electronic field-effect transistor based on a metal-oxide-semiconductor (n-MOS) structure can improve the mobility of electrons in the channel, and introducing a compressive force into the channel of a p-type field-effect transistor can improve based metal-oxide-semiconductor (p-MOS) structure can improve hole mobility in the channel.

[0028] In FIG. 1A and 1B are schematic diagrams of a known semiconductor device provided in the prior art. In FIG. 1B is a cross-sectional view of the device shown in FIG. 1A, taken along the dotted line A-A’. As shown in FIG. 1A-1B, the semiconductor device includes a semiconductor substrate 1 that includes an active region 11. The active region 11 is formed by a gate dielectric layer 16, a gate 12, and side walls 17. The active region 11 includes source/source regions 131 and 132. drain. Gate 12, gate dielectric layer 16, side walls 17, and source/drain regions 131 and 132 constitute the MOSFET.

[0029] In the active region 11, stress areas 141, 142 are further formed, which are located on both sides of the gate 12, to apply a voltage to the channel under the gate 12 to increase the mobility of carriers in the channel.

[0030] However, the carrier mobility in the channel of a known semiconductor device cannot meet the development needs of modern integrated circuit technology.

[0031] Accordingly, the following technical solutions are proposed in embodiments of the present disclosure.

[0032] Embodiments of the present disclosure provide a semiconductor device including an active region, a first stressed layer, and a gate. The active region is located in the semiconductor substrate and includes a central region and a peripheral region surrounding the central region. The first stressed layer is formed in the peripheral region by an insertion method, the first stressed layer including at least a first sub-section, a second sub-section, a third sub-section and a fourth sub-section. The first sub-region and the third sub-region are separately located on two sides of the central region in the first direction, and the second sub-region and the fourth sub-region are separately located on the other two sides of the central region in the second direction. The first direction is different from the second direction. The gate is located on the active region, extends in a first direction, and covers at least a portion of the central region, at least a portion of the first subregion, and at least a portion of the third subregion.

[0033] The first stress layer provided by embodiments of the present disclosure creates stress in both directions, i.e. in the first direction and the second direction, respectively, on the channel below the gate. Thus, with the first stressed layer provided by embodiments of the present disclosure, the mobility of carriers in the channel can be further improved compared to a structure in which stress is generated in only one direction according to the prior art.

[0034] In light of the above objectives, and to make the features and advantages of the present disclosure more obvious and understandable, specific methods for making the present disclosure are described in detail below with reference to the accompanying drawings. While embodiments of the present disclosure are described in detail, the schematic diagram in part is not enlarged to overall scale for convenience of description, but is a simple example and is intended to limit the scope of protection of the present disclosure.

[0035] In FIG. 2A-2C are schematic diagrams of a semiconductor device according to one embodiment of the present disclosure. In FIG. 2A is a top view of a semiconductor device, FIG. 2B is a cross-sectional view of the device of FIG. 2A taken along the dotted line A-A', and in FIG. 2C is a cross-sectional view of the device of FIG. 2A along the dotted line B-B'. As shown in FIG. 2A-2C, the semiconductor device includes an active region 21 located in a semiconductor substrate, in which the active region 21 includes a central region 211 and a peripheral region 212 surrounding the central region 211. The first stressed layer 24 is formed in the peripheral region 212 by an insertion method. . The first stress layer 24 includes at least a first subsection 241, a second subsection 242, a third subsection 243, and a fourth subsection 244. The first subsection 241 and the third subsection 243 are located separately on two sides of the central region 211 in a first direction, and the second subsection 242 and the fourth sub-area 244 are located separately on the other two sides of the central area 211 in the second direction. The first direction is different from the second direction.

[0036] The semiconductor device further includes a gate 22 located on the active region 21. The gate 22 extends in a first direction and covers at least a portion of the central region 211, at least a portion of the first subregion 241, and at least a portion of the third subregion 243.

[0037] It should be understood that the portions of the first subsection 241 and the third subsection 243 covered by the gate 22 constitute part of the channel; wherein the first subsection 241 and the third subsection 243 apply a voltage to the channel region in a first direction. According to one embodiment, the first direction is parallel to the channel width direction (B-B' direction).

[0038] The second subsection 242 and the fourth subsection 244 apply a voltage to the channel region in a second direction. According to one embodiment, the second direction is parallel to the direction of the length of the channel (direction A-A').

[0039] In some embodiments, the second subsection 242 and the fourth subsection 244 are symmetrically located on either side of the gate 22.

[0040] The semiconductor substrate material may be single crystal silicon (Si), silicon on dielectric (SOI), or other materials such as Group III-V compounds such as gallium arsenide may be used.

[0041] The semiconductor substrate further includes a narrow gap insulation structure (not shown), which may be multiple. A plurality of narrow gap insulation structures form an active region 21 in the semiconductor substrate.

[0042] A gate dielectric layer 26 is connected between the gate 22 and the semiconductor substrate. The material of the gate dielectric layer 26 may be, for example, but is not limited to silicon dioxide. Any material that can be used as a gate dielectric layer can be applied to embodiments of the present disclosure.

[0043] In some embodiments, the gate 22 includes side walls 27 on both sides thereof, the material of which may be, but is not limited to, silicon dioxide, silicon nitride. Any material that can be used as a gate dielectric layer can be applied to embodiments of the present disclosure.

[0044] In some embodiments, the central region 211 is rectangular. In FIG. 3 is a schematic diagram of a central region and a peripheral region according to one embodiment of the present disclosure. As shown in the drawing, the central region 211 includes a first set of parallel side edges 211_1 parallel to the first direction and a second set of parallel side edges 211_2 parallel to the second direction. It should be noted that in some other embodiments, the central region 211 may also have other shapes, such as circular, elliptical, or other polygonal shapes in addition to rectangular.

[0045] In some specific embodiments, the first sub-region 241 and the third sub-region 243 are symmetrical along the centerline of the first set of parallel side edges 211_1, and the second sub-region 242 and the fourth sub-region 244 are symmetrical along the centerline of the second set of parallel side edges 211_2.

[0046] In some embodiments, the first sub-region 241, the second sub-region 242, the third sub-region 243, and the fourth sub-region 244 are connected in series to form a ring structure surrounding the central region 211, as shown in FIG. 4.

[0047] Specifically, both ends of the first subsection 241 are respectively in contact with and connected to one end of the second subsection 242 and one end of the fourth subsection 244, and both ends of the third subsection 243 are respectively in contact with the other end of the second subsection 242 and the other the end of the fourth subsection 244 and connected to them. The first stressed layer 24 having a ring structure can apply voltage in both directions to the entire channel region, which can further optimize the performance of the semiconductor device compared to the first stress layer having a non-ring structure.

[0048] According to one embodiment, the first stressed layer 24 includes a silicon-germanium layer. In this case, the voltage generated by the first stress layer 24 applied to the channel is a compressive voltage, wherein the semiconductor substrate is an n-type substrate and the semiconductor device is a p-MOS transistor. It should be understood that the first stressed layer 24 may also be made of other stressed materials such as silicon carbide and the like.

[0049] In one embodiment, the first stressed layer 24 is formed using, but not limited to, an epitaxial growth process. The first stressed layer 24 may also be formed using other processes such as doping a semiconductor substrate.

[0050] In some embodiments, the semiconductor device further includes a second stress layer 29 located in the central region 211. In FIG. 5A-5B show schematic diagrams of a semiconductor device having a second stressed layer in accordance with one embodiment of the present disclosure. In FIG. 5B is a sectional view of FIG. 5A taken along the dotted line A-A'. As shown in FIG. 5A-5B, a second stress layer 29 is formed in the central region 211. The second stress layer 29 further increases the carrier mobility in the channel and thus improves the performance of the semiconductor device.

[0051] In a specific embodiment, the thickness of the first stress layer 24 is greater than the thickness of the second stress layer 29. In a more specific embodiment, the thickness of the first stress layer is 5-10 times, for example eight times, the thickness of the second stress layer.

[0052] In one embodiment, the second stress layer 29 and the first stress layer 24 are formed in the same processing step.

[0053] In some embodiments, at least a portion of the edges of the second stress layer 29 are connected to the edges of the first stress layer 24. In a more specific embodiment, all of the edges of the second stress layer 29 are connected to the first stress layer 24.

[0054] In one embodiment, the material of the second stress layer 29 is the same as, but is not limited to, the material of the first stress layer 24. The material of the second stressed layer 29 may also be different from the material of the first stressed layer 24.

[0055] In one embodiment, the second stressed layer 29 includes a silicon-germanium layer. In this case, the voltage generated by the second stress layer applied to the channel is a compressive voltage, wherein the semiconductor substrate is an n-type substrate and the semiconductor device is a p-MOS transistor.

[0056] In one embodiment, the second stressed layer 29 is formed using, but is not limited to, an epitaxial growth process. The second stressed layer 29 may also be formed using other processes such as doping the semiconductor substrate.

[0057] Again as shown in FIG. 2B, the semiconductor device further includes a first source/drain region 231 and a second source/drain region 232, which can be formed in the active region 21 by doping.

[0058] In some embodiments, the first source/drain region 231 is at least partially coincident with the fourth subregion 244, and the second source/drain region 232 is at least partially coincident with the second subregion 242. In a particular implementation, the first source/drain region 231 completely coincides with the fourth subregion 244, and the second source/drain region 232 completely coincides with the second subregion 242.

[0059] In some embodiments, the semiconductor device further includes a first source/drain expansion region 281 having a doping depth less than the doping depth of the first source/drain region 231, as shown in FIG. 6. The first source/drain expansion region 281 is located between the channel below the gate 22 and the first source/drain region 231 and is at least partially coincident with the fourth subregion 244. The first source/drain expansion region 281 may reduce the contact area between the first source/drain region 231. drain and channel to reduce leakage current in the channel.

[0060] In some embodiments, the semiconductor device further includes a second source/drain expansion region 282 having a doping depth less than the doping depth of the second source/drain region 232, as shown in FIG. 6. The second source/drain expansion region 282 is located between the channel below the gate 22 and the second source/drain region 232 and is at least partially coincident with the second sub-region 242. The second source/drain expansion region 282 may reduce the contact area between the second source/drain region 232. drain and channel to reduce leakage current in the channel.

[0061] Embodiments of the present disclosure further provide a method for manufacturing a semiconductor device. As shown in FIG. 7, the method includes the following steps.

[0062] At step 701, a semiconductor substrate is provided, and an active region is formed in the semiconductor substrate, including a central region and a peripheral region surrounding the central region.

[0063] At step 702, a first stress layer is formed in the peripheral region by an embedding method, which includes at least a first subsection, a second subsection, a third subsection, and a fourth subsection. The first sub-region and the third sub-region are separately located on two sides of the central region in the first direction, and the second sub-region and the fourth sub-region are separately located on the other two sides of the central region in the second direction. The first direction is different from the second direction.

[0064] At step 703, a gate is formed on the active region that extends in a first direction and covers at least a portion of the central region, at least a portion of the first subregion, and at least a portion of the third subregion.

[0065] A method for manufacturing a semiconductor device according to embodiments of the present disclosure will be described in more detail below with reference to FIG. 8A-8E.

[0066] First, as shown in FIG. 8A, step 701 is performed to provide a semiconductor substrate and form an active region 21 including a central region 211 and a peripheral region 212 surrounding the central region 211 in the semiconductor substrate.

[0067] According to one embodiment, formation of the active region 21 in the semiconductor substrate includes the following step.

[0068] A narrow gap insulation structure (not shown) is formed in the semiconductor substrate to create an active region 21.

[0069] The semiconductor substrate material may be single crystal silicon (Si), silicon on dielectric (SOI), or other materials such as Group III-V compounds such as gallium arsenide may be used.

[0070] In some embodiments, the central region 211 is rectangular. As shown in FIG. 8A, the center region 211 includes a first set of parallel side edges 211_1 parallel to the first direction and a second set of parallel side edges 211_2 parallel to the second direction. It should be noted that in some other embodiments, the central region 211 may also have other shapes, such as circular, elliptical, or other polygonal shapes in addition to rectangular.

[0071] Then, as shown in FIG. 8B, step 702 is performed to form the first stressed layer 24 by embedding in the peripheral region 212.

[0072] In one embodiment, formation of the first stress layer 24 includes the following step.

[0073] A first groove is formed in the peripheral region 212, and a first stressed layer is formed in the first groove using an epitaxial growth process.

[0074] It should be understood that the first stressed layer 24 may also be formed by another method, such as by doping a semiconductor substrate.

[0075] In one embodiment, the first stress layer 24 includes at least a first subsection 241, a second subsection 242, a third subsection 243, and a fourth subsection 244. The first subsection 241 and the third subsection 243 are located separately on two sides of the central region in a first direction , and the second subsection 242 and the fourth subsection 244 are located separately on the other two sides of the central region in the second direction. The first direction is different from the second direction.

[0076] In one embodiment, the first sub-region 241 and the third sub-region 243 are symmetrical along the centerline of the first set of parallel side edges 211_1, and the second sub-region 242 and the fourth sub-region 244 are symmetrical along the centerline of the second set of parallel side edges 211_2.

[0077] In some embodiments, the first sub-region 241, the second sub-region 242, the third sub-region 243 and the fourth sub-region 244 are connected in series to form a ring structure surrounding the central region 211. Specifically, both ends of the first sub-region 241 are respectively in contact with one end of the second sub-section 242 and one end of the fourth sub-section 244 and connected to them, and both ends of the third sub-section 243 are respectively in contact with the other end of the second sub-section 242 and the other end of the fourth sub-section 244 and connected to them. The first stressed layer 24 having a ring structure can apply voltage in both directions to the entire channel region, which can further optimize the performance of the semiconductor device compared to the first stress layer having a non-ring structure.

[0078] According to one embodiment, a method for manufacturing a semiconductor device further includes forming a second stressed layer 29 in a central region 211, as shown in FIG. 8C.

[0079] According to one embodiment, the formation of the second stressed layer 29 includes the following step.

[0080] A second groove is formed in the central region, and a second stressed layer is formed in the second groove by an epitaxial growth process.

[0081] It should be understood that the second stressed layer 29 may also be formed by another method, such as by doping the semiconductor substrate.

[0082] Then, as shown in FIG. 8D, step 703 is performed to form on the active region 21 a gate 22 that extends in a first direction and covers at least a portion of the central region 211, at least a portion of the first subregion 241, and at least a portion of the third subregion 243.

[0083] In one embodiment, the gate 22 also covers at least a portion of the second stress layer 29.

[0084] The method for manufacturing a semiconductor device further includes the following step: after forming the gate 22, doping the active region 21 on both sides of the gate 22 to form a first source/drain region 231, a first source/drain expansion region 281, a second source/drain region 232 drain and a second source/drain expansion region 282, as shown in FIG. 8E.

[0085] In one embodiment, the first source/drain region 231 and the first source/drain expansion region 28 are at least partially coincident with the fourth subregion 244, and the second source/drain region 232 and the second source/drain expansion region 282 are at least partially coincident. coincide with the second subsection 242.

[0086] According to one embodiment, a method for manufacturing a semiconductor device further includes the step of forming side walls on both sides of the gate 22, as shown in FIG. 8E.

[0087] The above descriptions are merely preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims (10)

1. A semiconductor device comprising: an active region located in a semiconductor substrate, comprising a central region and a peripheral region surrounding the central region; a first stressed layer formed in a peripheral region by an insertion method, wherein the first stressed layer comprises at least a first sub-region, a second sub-region, a third sub-region and a fourth sub-region, wherein the first sub-region and the third sub-region are separately located on two sides of the central region in a first direction, and the second sub-section and the fourth sub-section are separately located on the other two sides of the central region in a second direction, the first direction being different from the second direction; a gate located on the active region, extending in a first direction and covering at least a portion of the central region, at least a portion of the first subregion, and at least a portion of the third subregion; and a second stressed layer located in the central region, wherein the thickness of the first stressed layer is greater than the thickness of the second stressed layer. 2. The semiconductor device of claim 1, wherein the central region is rectangular and includes a first set of parallel side edges parallel to the first direction and a second set of parallel side edges parallel to the second direction, the first sub-region and the third sub-region being symmetrical along the centerline of the first a set of parallel side edges, and the second sub-section and the fourth sub-section are symmetrical along the center line of the second set of parallel side edges. 3. The semiconductor device according to claim 1, wherein the first sub-region, the second sub-region, the third sub-region and the fourth sub-region of the first stressed layer are connected in series to form a ring structure surrounding the central region, and both ends of the first sub-region are respectively in contact with one end the second sub-section and one end of the fourth sub-section and connected to them, and both ends of the third sub-section are respectively in contact with the other end of the second sub-section and the other end of the fourth sub-section and connected to them. 4. The semiconductor device according to claim 1, wherein the second subsection and the fourth subsection are symmetrically arranged on both sides of the gate, the first stressed layer comprises a silicon germanium layer, and the first strained layer is formed using an epitaxial growth process. 5. Semiconductor device according to claim 1, in which the thickness of the first stressed layer is 5-10 times greater than the thickness of the second stressed layer. 6. The semiconductor device of claim 1, comprising a first source/drain region and a second source/drain region, wherein the first source/drain region is at least partially coincident with the fourth subregion, and the second source/drain region is at least partially coincident with second sub-section; a first source/drain expansion region having a doping depth less than the doping depth of the first source/drain region, wherein the first source/drain expansion region is located between the channel below the gate and the first source/drain region and is at least partially coincident with the fourth subregion; and a second source/drain expansion region having a doping depth less than the doping depth of the second source/drain region, wherein the second source/drain expansion region is located between the channel below the gate and the second source/drain region and is at least partially coincident with the second subregion . 7. The semiconductor device according to claim 1, comprising a narrow-gap insulation structure located in a semiconductor substrate to form an active region. 8. A method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate and forming an active region in the semiconductor substrate, the active region comprising a central region and a peripheral region surrounding the central region; forming a first stressed layer in a peripheral region by an insertion method, wherein the first stressed layer comprises at least a first sub-section, a second sub-section, a third sub-section and a fourth sub-section, wherein the first sub-section and the third sub-section are separately located on two sides of the central region in a first direction, and the second the sub-section and the fourth sub-section are separately located on the other two sides of the central region in a second direction, the first direction being different from the second direction; forming a gate on the active region, wherein the gate extends in a first direction and covers at least a portion of the central region, at least a portion of the first subregion, and at least a portion of the third subregion; and forming a second stressed layer in the central region, wherein the thickness of the first stressed layer is greater than the thickness of the second stressed layer. 9. The method of manufacturing a semiconductor device according to claim 8, wherein forming a first stressed layer in a peripheral region by an implantation method includes: forming a first groove in a peripheral region and forming a first stressed layer in the first groove using an epitaxial growth process; and wherein forming the second stressed layer includes: forming a second groove in the central region and forming a second stressed layer in the second groove using an epitaxial growth process. 10. The method of manufacturing a semiconductor device according to claim 8, further comprising: doping an active region on both sides of the gate to form a first source/drain region, a first source/drain expansion region, a second source/drain region, and a second source/drain expansion region, where wherein the first source/drain region and the first source/drain expansion region at least partially coincide with the fourth subregion, and the second source/drain region and the second source/drain expansion region at least partially coincide with the second subregion, and wherein an active region is formed in the semiconductor substrate includes: formation of a narrow-gap insulation structure in the semiconductor substrate to form an active region.

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