JP2007053336A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MISFET which improves the mobility of carriers without deteriorating a gate insulating film. <P>SOLUTION: In the MISFET, a portion 25a formed on an element separating region of a gate electrode 5 contains an impurity that changes a lattice constant. A stress in a direction of improving carrier mobility is applied to a channel region, where a starting point of stress application is determined to be the portion 25a of the gate electrode 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure of a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof capable of improving the driving force of a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  2. Description of the Related Art In recent years, as semiconductor integrated circuit devices are highly integrated, highly functional, and speeded up, a technique has been proposed that positively applies stress to the channel region of a MISFET to improve mobility.

  FIG. 11A is a perspective view showing the direction and type of stress that improves carrier mobility in an N-channel MISFET, and FIG. 11B improves carrier mobility in a P-channel MISFET. It is a perspective view which shows the direction and kind of stress.

  The N-channel MISFET shown in FIG. 11A is formed on a substrate 201 having a P-type semiconductor region with a <110> channel orientation (meaning that the channel direction is a <110> direction), and the substrate 201. A gate insulating film 202, a gate electrode 203 formed on the gate insulating film 202, and N-type source / drain regions 204 formed in regions of the substrate 201 located on both sides of the gate electrode 203. ing. As shown in the figure, the mobility of the N-channel MISFET is improved by the extension stress 205 applied in the channel direction, the extension stress 206 applied in the gate width direction, and the substrate method among the stresses on the channel region. This is compressive stress 207 applied in the linear direction.

  On the other hand, a <110> channel orientation P-channel MISFET shown in FIG. 11B includes a substrate 301 having an N-type semiconductor region, a gate insulating film 302 formed on the substrate 301, and a gate insulating film 302. It has a formed gate electrode 303 and a P-type source / drain region 304 formed in a region of the substrate 301 located on both sides of the gate electrode 303. As shown in the figure, in the P channel MISFET, the carrier mobility is improved by compressive stress 305 applied in the channel direction, tensile stress 306 applied in the gate width direction among stress applied to the channel region, and This is an extension stress 307 applied in the normal direction of the substrate. In this specification, “channel direction” refers to the direction in which carriers travel in the channel region (gate length direction), and “gate width direction” refers to the direction perpendicular to the channel direction and the gate electrode extends in the MISFET. Each shall mean.

  As one of the methods for applying these stresses, the channel layer of the N channel MISFET is stretched by being composed of epitaxially grown SiGe, so that the tensile stress in the channel direction and the gate width direction is applied to the channel region of the N channel MISFET. A method of applying a voltage is known. However, this method has a disadvantage that the process becomes too complicated as compared with the conventional manufacturing process (see Non-Patent Document 1).

  FIG. 12 is a perspective view showing an N-channel MISFET having a <100> channel orientation (meaning that the channel direction is the <100> direction). When the silicon substrate is used, the movement of the MISFET is shown. It also describes the direction of stress on the channel where the degree of improvement increases. As shown in the figure, in the case of an N-channel MISFET with a <100> channel orientation, the carrier mobility is improved with respect to the channel by extension stress applied in the channel direction, compression stress applied in the gate width direction, and This is compressive stress applied in the normal direction of the substrate. The direction of stress in the gate width direction for improving mobility is different from that shown in FIG. Further, in a P-channel MISFET with a <100> channel orientation, stress applied to the channel does not significantly affect the carrier mobility.

  13A and 13B are diagrams showing a conventional N-channel MISFET, where FIG. 13A is a top view and FIG. 13B is a cross-sectional view taken along the line XX in FIG.

13 includes a substrate 101 having a P-type semiconductor region, an STI (Shallow Trench Isolation) 103 formed on the substrate 101, an active region 102 composed of the substrate 101 surrounded by the STI 103, and an active region. A gate insulating film 104 formed on the region 102; a gate electrode 105 formed on the gate insulating film 104; and an N-type source region formed in a region located on both sides of the gate electrode 105 in the active region 102. And a drain region 106. As shown in the figure, the entire gate electrode 105 is formed by a relatively simple technique in which the entire gate electrode 105 formed on the STI 103 and the active region 102 is uniformly doped with impurities that do not directly affect carrier generation. In-film compressive stress 107 is contained. Since the in-film compressive stress 107 contained in the gate electrode 105 attempts to release the compressive stress, an expansion action occurs to the outside. For this reason, a method is known in which compressive stress 108 in the substrate normal direction is applied to the channel region in the substrate 101 via the gate insulating film 104, and tensile stress is applied in the channel direction and the gate width direction. (Non-patent document 2).
Low Power Device Technology with SiGe Channel, HfSiON, and Poly-Si Gate, Howard C.-H.Wang et al, 2004 IEDM Tech.Dig. Gate stack optimization for 65nm CMOS Low Power and High Performance platform, B. Duriez1 at al, 2004 IEDM Tech.Dig.

  However, the conventional manufacturing method has a problem that the gate insulating film is deteriorated because a large amount of impurities that do not directly affect carrier generation are doped in the gate electrode on the channel region.

  Therefore, an object of the present invention is to provide a semiconductor device including a MISFET in which carrier mobility is improved without deteriorating a gate insulating film, and a manufacturing method thereof.

  In order to achieve the above object, a first semiconductor device according to the present invention is formed on an active region formed by an element isolation region formed in a substrate, an active region formed of a substrate surrounded by the element isolation region, and A gate insulating film, a gate electrode provided from above the gate insulating film to the element isolation region, and a first conductivity type formed in a region located on both sides of the gate electrode in the active region. The gate electrode has a first portion located on the element isolation region and a second portion located on the active region, the first portion of the gate electrode being a gate Compared with the second part of the electrode, it contains a greater stress.

  With this configuration, the first portion of the gate electrode located on the element isolation region can arbitrarily contain compressive stress or tensile stress, and the carrier mobility is improved in accordance with the conductivity type of the MISFET. Stress can be applied to the channel region. Further, since the first part of the gate electrode is located on the element isolation region, the stress intensity of the first part can be arbitrarily set without affecting the gate insulating film.

  In the first semiconductor device, the first portion of the gate electrode includes a second impurity that changes a lattice constant of the gate electrode.

  In this configuration, since the first portion of the gate electrode is located on the element isolation region, the gate insulating film is not deteriorated even when a high-concentration second impurity is introduced. Therefore, a strong stress can be applied to the channel.

  In the first semiconductor device, the second portion of the gate electrode contains a second impurity having a lower concentration than the first portion of the gate electrode.

  In the first semiconductor device, the second impurity is an impurity having no conductivity type.

  In the first semiconductor device, the first impurity is an n-type impurity, and the second impurity is an impurity that increases the lattice constant of the gate electrode.

  In the first semiconductor device, the gate electrode is made of polysilicon, and the second impurity is germanium.

  In the first semiconductor device, the first impurity is an n-type impurity, and the second impurity is an impurity having the same conductivity type as the first impurity.

  In the first semiconductor device, the first impurity is a p-type impurity, and the second impurity is an impurity that decreases the lattice constant of the gate electrode.

  In the first semiconductor device, the gate electrode is made of polysilicon, and the second impurity is carbon.

  A second semiconductor device of the present invention includes a substrate on which an active region is formed, an element isolation region formed on the substrate and surrounding the active region, a gate insulating film formed on the active region, and the gate A gate electrode provided on the insulating film; an impurity diffusion region including a first impurity having a conductivity type formed in a region of the active region located on both sides of the gate electrode; Alternatively, it further includes a dummy gate electrode including a second impurity which is provided above and faces the gate electrode with one of the impurity diffusion regions interposed therebetween and which changes a lattice constant inherent in the constituent material.

  With this configuration, the dummy gate electrode can arbitrarily contain a compressive stress or an extension stress, and it is possible to apply a stress in a direction in which the carrier mobility is improved according to the conductivity type of the MISFET to the channel region. . Further, since the dummy gate electrode is provided apart from the gate insulating film of the MISFET, the second impurity having a higher concentration can be introduced into the dummy gate electrode than when the impurity is introduced into the gate electrode. Therefore, it becomes possible to apply a stronger stress to the channel region of the MISFET, and the carrier mobility can be further improved.

  In the first method for manufacturing a semiconductor device of the present invention, a step (a) of forming an element isolation region on a substrate and a step of forming a gate insulating film on an active region made of a substrate surrounded by the element isolation region (b) ), A step (c) of forming a gate electrode from above the gate insulating film to the element isolation region, and a first portion of the gate electrode located on the element isolation region is activated in the gate electrode. Impurity diffusion including a first impurity having a conductivity type in the step (d) of adding a larger stress than the second portion located on the region and the region located on both sides of the gate electrode in the active region And (e) forming a region.

  By this method, a compressive stress or an extension stress can be arbitrarily contained in the first portion of the gate electrode located on the element isolation region, and the carrier mobility is improved in accordance with the conductivity type of the MISFET. A MISFET in which stress is applied to the channel region can be manufactured.

  In the first method of manufacturing a semiconductor device, in step (d), a second impurity that changes the lattice constant of the gate electrode is selectively implanted into the first portion of the gate electrode, thereby forming the gate electrode. A larger stress is contained than in the second part.

  In the first method for fabricating a semiconductor device, in the step (c), a second impurity having a dose amount smaller than the dose amount of the second impurity implanted in the step (d) is applied to the patterned gate electrode. Has been injected.

  In the first method for manufacturing a semiconductor device, the second impurity is an impurity having no conductivity type.

  In the first method for fabricating a semiconductor device, the first impurity is an n-type impurity, and the second impurity is an impurity that increases the lattice constant of the gate electrode.

  In the first method for fabricating a semiconductor device, the first impurity is a p-type impurity, and the second impurity is an impurity that decreases the lattice constant of the gate electrode.

  According to a second method of manufacturing a semiconductor device of the present invention, a step (a) of forming an element isolation region surrounding the active region on a substrate having an active region, and forming a gate insulating film and a gate electrode on the active region And forming a dummy gate electrode including a first impurity that changes the lattice constant of the constituent material at least above or above a part of the active region and on the side of the gate electrode. And (d) impurity diffusion including a second impurity having a conductivity type in a region located on both sides of the gate electrode including a region between the gate electrode and the dummy gate electrode in the active region. And (d) forming a region.

  According to this method, the dummy gate electrode can arbitrarily contain compressive stress or tensile stress, and it is possible to apply stress in the direction in which the carrier mobility is improved according to the conductivity type of the MISFET to the channel region. become. Further, since the dummy gate electrode is provided apart from the gate insulating film of the MISFET, the second impurity having a higher concentration can be introduced into the dummy gate electrode than when the impurity is introduced into the gate electrode.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to apply the stress in the direction of improving the carrier mobility to the channel region while suppressing the deterioration of the gate insulating film. The stress that improves carrier mobility is compressive stress in the substrate normal direction in the N-channel type MISFET and tensile stress in the substrate normal direction in the P-channel type MISFET.

(First embodiment)
Hereinafter, a semiconductor device including an N-channel MISFET according to a first embodiment of the present invention will be described with reference to the drawings.

  1A and 1B are diagrams showing an N-channel MISFET according to a first embodiment of the present invention, where FIG. 1A is a top view, FIG. 1B is a cross-sectional view taken along a line AA in FIG. c) is a perspective view.

  1 includes a substrate 1 having a P-type semiconductor region (not shown), an element isolation region 3 made of STI formed on the substrate 1, and a substrate 1 surrounded by the element isolation region 3. Of the active region 2, the gate insulating film 4 provided on the active region 2, the gate electrode 5 provided on the element isolation region 3 from the gate insulating film 4, and the active region 2 An impurity diffusion region (source region or drain region) 6a including an n-type impurity provided in regions located on both sides of the gate electrode 5 is provided. The impurity diffusion region 6a may be an LDD region or an extension region.

  The gate electrode 5 is made of polysilicon containing n-type impurities, for example. The substrate 1 is made of a semiconductor such as silicon. Of the gate electrode 5, a portion 25 a provided on the element isolation region 3 has a lattice constant larger than that of the material (silicon) constituting the gate electrode 5 and germanium (Ge) that does not affect carrier generation. And tin (Sn) have been introduced. On the other hand, Ge is not introduced into the portion 25 b provided on the active region 2 in the gate electrode 5.

The gate insulating film 4 is made of SiO ₂ or other insulator and has a thickness of about 2 nm, for example. Since the gate insulating film 4 is usually very thin, the stress applied from the gate electrode 5 in the substrate normal direction is directly transmitted to the channel region.

  In the N-channel MISFET of this embodiment, Ge or Sn is introduced as a substance for increasing the lattice constant in the portion 25a of the gate electrode 5 located on the element isolation region 3 as described above. Therefore, as shown in FIGS. 1B and 1C, an in-film compressive stress 27 is generated in the portion 25a of the gate electrode 5 into which Ge or Sn is introduced. The portion 25a having the in-film compressive stress 27 corresponds to a portion 25b provided on the active region 2 in the element isolation region 3 or the gate electrode 5 (a portion into which a substance that increases the lattice constant is not introduced). Apply compressive stress. The portion 25b of the gate electrode 5 is distorted by receiving compressive stress from the portions 25a on both sides, and applies a compressive stress 29 in the substrate normal direction to the channel region. By this compressive stress 29, the carrier mobility of the MISFET of this embodiment which is an N channel type is greatly improved. Note that the above-described channel region means a region of the substrate 1 that is sandwiched between two impurity diffusion regions (source region and drain region) 6 a and is located immediately below the gate electrode 5.

  As shown in FIG. 1C, when a compressive stress 29 is applied to the channel region, an extension stress 31 in the channel direction and an extension stress 33 in the gate width direction are generated in the channel region. In the <110> channel orientation MISFET, both of the extension stresses 31 and 33 improve the carrier mobility of the N-channel MISFET. Therefore, in the MISFET of this embodiment, a very large mobility can be obtained. In the MISFET having the <100> channel orientation, the extension stress 31 can improve the carrier mobility.

  In addition, in the N-channel MISFET of this embodiment, impurities such as Ge and Sn that change the lattice constant are not introduced into the portion 25b of the gate electrode 5 that is located immediately above the gate insulating film 4. Therefore, in the N-channel MISFET of this embodiment, the gate insulating film which does not cause a problem when Ge is introduced into the entire gate electrode as shown in FIG. 13 does not occur. Further, since the concentration of impurities such as Ge and Sn contained in the portion 25a of the gate electrode 5 located on the element isolation region 3 can be increased without worrying about deterioration of the gate insulating film 4, the channel region A stronger compressive stress 29 can be applied.

Impurities such as Ge and Sn can be selectively introduced only into the portion 25a of the gate electrode 5 by ion implantation, for example. The dose when Ge is implanted into the gate electrode made of polysilicon can be set to 1 × 10 ¹⁵ cm ⁻² or more, for example.

  The impurity introduced into the portion 25a of the gate electrode 5 is not limited to Ge or Sn, but may be any material that can increase the lattice constant of the gate electrode 5. In particular, it is preferable to use a substance belonging to the same family as the material of the gate electrode in the periodic table because it does not affect the generation of carriers.

(Second Embodiment)
2A and 2B are diagrams showing a P-channel MISFET according to a second embodiment of the present invention, in which FIG. 2A is a top view, FIG. 2B is a cross-sectional view taken along the line BB in FIG. c) is a perspective view.

  A P-channel MISFET shown in FIG. 2 includes a substrate 1 having an N-type semiconductor region (not shown), an element isolation region 3 made of STI formed on the substrate 1, and a substrate 1 surrounded by the element isolation region 3. Of the active region 2, the gate insulating film 4 provided on the active region 2, the gate electrode 5 provided on the element isolation region 3 from the gate insulating film 4, and the active region 2 An impurity diffusion region (source region or drain region) 6b including a p-type impurity is provided in a region located on both sides of the gate electrode 5. The impurity diffusion region 6b may be an LDD region or an extension region.

  The gate electrode 5 is made of polysilicon containing a p-type impurity, for example. The substrate 1 is made of a semiconductor such as silicon. Of the gate electrode 5, the portion 41 a provided on the element isolation region 3 has carbon (C) that has a lattice constant smaller than that of the material (silicon) constituting the gate electrode 5 and does not affect carrier generation. Etc. have been introduced. On the other hand, carbon is not introduced into the portion 41 b provided on the active region 2 in the gate electrode 5.

  In the P-channel MISFET of this embodiment, carbon is introduced as a substance for reducing the lattice constant in the portion 41a located on the element isolation region 3 in the gate electrode 5 as described above. Therefore, as shown in FIGS. 2B and 2C, an in-film extensional stress 43 is generated in the portion 41a of the gate electrode 5. The portion 41a having the in-film extension stress 43 is in contrast to the element isolation region 3 or the portion 41b provided on the active region 2 of the gate electrode 5 (the portion into which the substance for reducing the lattice constant is not introduced). Apply stretching stress. The portion 41b of the gate electrode 5 is distorted by receiving an extension stress from the portions 41a on both sides, and an extension stress 45 in the substrate normal direction is applied to the channel region. For example, in the <110> channel orientation MISFET, the carrier stress of the P channel type MISFET of this embodiment is greatly improved by the extension stress 45.

  As shown in FIG. 2C, when the extension stress 45 is applied to the channel region, a compressive stress 47 in the channel direction and a compressive stress 49 in the gate width direction are generated in the channel region. Of these two compressive stresses, the compressive stress 47 in the channel direction contributes to the improvement of mobility. For this reason, the P-channel MISFET of this embodiment can greatly improve the carrier mobility compared to the P-channel MISFET when no stress is applied to the channel region.

  In addition, in the P-channel type MISFET of this embodiment, impurities such as carbon that change the lattice constant are not introduced into the portion 41b of the gate electrode 5 located immediately above the gate insulating film 4. Therefore, in the P-channel type MISFET of this embodiment, the gate insulating film which causes a problem when carbon is introduced into the entire gate electrode does not deteriorate. Further, since the concentration of impurities such as carbon contained in the portion 41a of the gate electrode 5 located on the element isolation region 3 can be increased without worrying about deterioration of the gate insulating film 4, the channel region is stronger. An extension stress 45 can be applied.

Impurities such as carbon can be selectively introduced only into the portion 41a of the gate electrode 5 by ion implantation, for example. The dose when carbon is implanted into the gate electrode made of polysilicon can be set to 1 × 10 ¹⁵ cm ⁻² or more, for example.

  The impurity introduced into the portion 41a of the gate electrode 5 is not limited to carbon, but may be any material that can reduce the lattice constant of the gate electrode 5. In particular, it is preferable to use a substance belonging to the same family as the material of the gate electrode in the periodic table because it does not affect the generation of carriers.

(Third embodiment)
3A and 3B are diagrams showing an N-channel MISFET according to a third embodiment of the present invention, in which FIG. 3A is a top view, FIG. 3B is a cross-sectional view taken along the line CC in FIG. c) is a perspective view.

  As shown in FIG. 3, the N-channel MISFET of this embodiment includes a substrate 1 having a P-type semiconductor region (not shown), an element isolation region 3 made of STI formed on the substrate 1, and an element isolation region. 3, an active region 2 made of a substrate 1 surrounded by 3, a gate insulating film 4 provided on the active region 2, and a gate electrode 5 provided over the gate insulating film 4 over the element isolation region 3. And an impurity diffusion region 6a that is provided in a region located on both sides of the gate electrode 5 in the active region 2 and includes an n-type impurity.

  In the portion 51 a provided on the element isolation region 3 of the gate electrode 5, Ge, Sn, or the like that has a lattice constant larger than that of the material (silicon) constituting the gate electrode 5 and does not affect the generation of carriers. Has been introduced. Further, unlike the N-channel type MISFET of the first embodiment, the portion 51b provided on the active region 2 of the gate electrode 5 is doped with impurities such as Ge and Sn at a lower concentration than the portion 51a. Yes. Therefore, a strong in-film compressive stress 54 is generated in the portion 51a of the gate electrode 5, and a weak in-film compressive stress 55 is generated in the portion 51b than in the portion 51a. Therefore, the compressive stress 29 in the substrate normal direction is applied to the channel region by the in-film compressive stress 54 of the portion 51a of the gate electrode 5 and the in-film compressive stress 55 of the portion 51b. Therefore, compared with the configuration of the first embodiment shown in FIG. 1, in the configuration of the present embodiment, the in-film compressive stress 55 of the portion 51b of the gate electrode 5 is further applied, so that a large compressive stress 29 can be applied. it can. In the channel region, as shown in FIG. 3C, the compressive stress 29 causes an extension stress 31 in the channel direction and an extension stress 33 in the gate width direction. The compression stress 29 and the extension stresses 31 and 33 are stresses that improve the carrier mobility of the N-channel MISFET in the <110> channel orientation N-channel MISFET. For this reason, in the N-channel MISFET of this embodiment, the carrier mobility is much higher than when no stress is applied to the channel region.

An impurity that increases the lattice constant is introduced into the portion 51 b of the gate electrode 5 provided on the active region 2 to an extent that does not deteriorate the gate insulating film 4. When Ge is introduced into the portion 51b by ion implantation, the dose is preferably about 1 × 10 ¹⁴ cm ⁻² or less. On the other hand, Ge is ion-implanted into the portion 51 a provided on the element isolation region 3 in the gate electrode 5 with a dose amount of about 1 × 10 ¹⁵ cm ⁻² which is one order larger than the portion 51 b.

Impurities that change the lattice constant of the gate electrode, although slightly different depending on the material, are considered not to deteriorate the gate insulating film if ion implantation is performed at a dose of about 1 × 10 ¹⁵ cm ⁻² or less. Since the N-channel MISFET of this embodiment is manufactured with a dose amount of Ge or the like of 1 × 10 ¹⁵ cm ⁻² or less, deterioration of the gate insulating film 4 is prevented while improving carrier mobility. Yes.

In a surface channel transistor in which carriers run in the vicinity of the interface with the gate insulating film in the substrate or a buried channel transistor in which the channel is embedded in the substrate, the donor (n-type impurity) or It is necessary to introduce an acceptor (p-type impurity). At that time, the magnitude of stress applied to the channel region can be adjusted by adjusting the amount and type of the donor and acceptor mixed therein. Specifically, when the gate electrode 5 is made of n ⁺ Si, the phosphorus (P) concentration is increased in the portion 51b provided on the active region 2 to keep the arsenic (As) concentration small. As has a larger lattice constant than Si, and can be introduced into the gate electrode 5 in the same manner as Ge to increase the lattice constant of the introduced portion. On the other hand, in the portion 51a provided on the element isolation region 3 in the gate electrode 5, a method of increasing the As concentration and decreasing the P concentration can be considered. As described above, a method of adjusting the amount or type of impurities that act as an acceptor or a donor may be used in combination with a method of mixing an element that can increase the lattice constant.

(Fourth embodiment)
As a fourth embodiment of the present invention, a method for manufacturing an N-channel MISFET according to the first embodiment will be described. 4A to 4D are cross-sectional views illustrating a method for manufacturing an N-channel MISFET according to the fourth embodiment.

First, as shown in FIG. 4A, a p-type impurity such as boron (B) is ion-implanted into a substrate 1 made of a p-type semiconductor substrate (or a p-type semiconductor layer provided on the substrate 1). A p-type well 7 is formed in 1. At this time, the implantation energy is 300 keV, and the dose is 1 × 10 ¹³ cm ⁻² . Next, a p-type impurity (B or the like) is ion-implanted into a part of the p-type well 7 at an implantation energy of 150 keV and a dose of 1 × 10 ¹³ cm ⁻² to form a punch-through stopper. Further, a p-type impurity (such as B) is implanted into a portion of the substrate 1 which becomes a channel region by an implantation energy of 20 keV and a dose of 5 × 10 ¹² cm ⁻² . Next, an element isolation region 3 made of STI surrounding the active region 2 made of the substrate 1 (the active region 2 shown in FIG. 1A) is formed on the substrate 1 (p-type well 7) by a known method.

Next, as shown in FIG. 4B, a gate insulating film 4 having a thickness of 2 nm is formed on the substrate 1 (p-type well 7) by thermal oxidation, and then on the element isolation region 3 and the gate insulating film 4. A polysilicon film having a thickness of 150 nm is formed. Then, P ions are implanted into the polysilicon film under conditions of an implantation energy of 10 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . Subsequently, the polysilicon film is patterned by etching using a resist to form a gate electrode 5 extending from the gate insulating film 4 to the element isolation region 3.

Next, as shown in FIG. 4C, the gate electrode 5 has an opening on a portion 25 a located immediately above the element isolation region 3, and a portion located on the gate electrode 5 immediately above the active region 2. A resist 20 covering 25b is formed on the substrate. Thereafter, Ge is implanted into the portion 25a of the gate electrode 5 under the conditions of an implantation energy of 200 keV and a dose of 1 × 10 ¹⁵ cm ^{−2 using} the resist 20 as an implantation mask. When forming the resist 20 used for the implantation of Ge, the resist is misaligned by covering with a resist from the edge of the active region to a portion slightly entering the element isolation region 3 in order to obtain a margin for alignment. Also, Ge can be prevented from being implanted into the active region 2. In this way, Ge can be implanted with relatively high energy.

Next, as shown in FIG. 4D, As that is an n-type impurity is implanted into a region located on both sides of the gate electrode 5 in the active region 2 of the substrate 1 with an implantation energy of 30 keV and a dose amount of 5 × 10. Implantation is performed under the condition of ¹⁵ cm ⁻² to form an N-type impurity diffusion region (N-type impurity diffusion region 6a shown in FIGS. 1A and 1C). This N-type impurity diffusion region becomes an LDD region, an extension region, or a source region and a drain region.

  By the above method, the N-channel MISFET according to the first embodiment can be manufactured relatively easily.

  In the ion implantation step shown in FIG. 4C, Ge may be implanted a plurality of times under a plurality of energy conditions in order to make the impurity distribution of Ge uniform within the portion 25a. Further, even if As or Sn is implanted instead of Ge, the in-film compressive stress 27 can be generated in the portion 25a. At least two of these As implantation, Ge implantation, and Sn implantation may be combined. Further, Ge implantation into the portion 25a of the gate electrode 5 is performed after patterning the polysilicon film, but may be performed before patterning the polysilicon film. For example, immediately after the polysilicon film is formed or in the polysilicon film. It may be performed after P implantation.

(Fifth embodiment)
As a fifth embodiment of the present invention, a method for manufacturing an N-channel MISFET according to the third embodiment will be described. 5A to 5D are cross-sectional views showing a method for manufacturing an N-channel MISFET according to the fifth embodiment.

  First, as shown in FIG. 5A, after the p-type well 7, the element isolation region 3, and the punch-through stopper are formed on the substrate 1 by the same method as in the fourth embodiment, Make an injection.

Next, as shown in FIG. 5B, a gate insulating film 4 having a thickness of 2 nm is formed on the substrate 1 (p-type well 7) by thermal oxidation, and then on the element isolation region 3 and the gate insulating film 4. A polysilicon film having a thickness of 150 nm is formed. Then, P ions are implanted into the polysilicon film under conditions of an implantation energy of 10 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . Subsequently, Ge is implanted into the polysilicon film under conditions of an implantation energy of 100 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . Thereafter, the polysilicon film is patterned by etching using a resist to form the gate electrode 5.

Next, as shown in FIG. 5C, the gate electrode 5 has an opening in a portion 51 a located immediately above the element isolation region 3, and a portion 51 b located in the gate electrode 5 immediately above the active region 2. A resist 20 covering the substrate is formed on the substrate. Thereafter, Ge is implanted into the portion 51a of the gate electrode 5 under the conditions of an implantation energy of 200 keV and 1 × 10 ¹⁵ cm ^{−2 using} the resist 20 as an implantation mask. As a result, a small in-film compressive stress 55 is generated in the portion 51b of the gate electrode 5 containing low concentration Ge, and a large in-film compressive stress 54 is generated in the portion 51a of the gate electrode 5 containing high concentration Ge. By the action of the in-film compressive stress 55 and the in-film compressive stress 54, a compressive stress 29 in the substrate normal direction is applied to the channel region.

Next, as shown in FIG. 5D, n, which is an n-type impurity, is implanted into the active region 2 of the substrate 1 on both sides of the gate electrode 5 at an implantation energy of 30 keV and a dose of 5 × 10. Implantation is performed under the condition of ¹⁵ cm ⁻² to form an N-type impurity diffusion region (N-type impurity diffusion region 6a shown in FIGS. 3A and 3C). This N-type impurity diffusion region becomes an LDD region, an extension region, or a source region and a drain region.

  With the above method, the N-channel MISFET according to the third embodiment can be manufactured relatively easily.

  In the step shown in FIG. 5C, As or Sn may be implanted instead of Ge, and at least two of Ge implantation, As implantation, and Sn implantation may be combined.

  Further, Ge implantation into the portion 51a of the gate electrode 5 is performed after patterning the polysilicon film, but may be performed before patterning the polysilicon film. For example, immediately after the polysilicon film is formed or the polysilicon film It may be performed after P is injected into the substrate.

(Sixth embodiment)
FIG. 6A is a perspective view showing a semiconductor device according to the sixth embodiment. FIGS. 6B and 6C are a top view of a dummy transistor in the semiconductor device of this embodiment, and DD. It is sectional drawing in a location. The semiconductor device of this embodiment includes a dummy gate electrode that includes an impurity that opposes the gate electrode and changes the lattice constant.

  As shown in FIGS. 6A to 6C, the semiconductor device of this embodiment includes an N-channel type MISFET 90 and a dummy gate electrode 15 provided adjacent to the MISFET 90. In the example shown in FIG. 6, dummy transistors 95 each having a dummy gate electrode 15 facing the gate electrode 5 of the MISFET 90 with the impurity diffusion region 6 a interposed therebetween are disposed on both sides of the MISFET 90.

  That is, the semiconductor device of this embodiment includes an element isolation region 3 made of STI formed on a substrate 1 having a P-type semiconductor region (not shown) and an active region made of a substrate 1 surrounded by the element isolation region 3. 2, a gate insulating film 4 provided on the active region 2, a gate electrode 5 provided on the element isolation region 3 from above the gate insulating film 4, and the gate electrode 5 of the active region 2. Impurity diffusion region (source region or drain region) 6a containing n-type impurities, a dummy gate insulating film 4a provided at least partially on the active region 2, and dummy gate insulation And a dummy gate electrode 15 provided over the element isolation region 3 from above each of the films 4a.

  The gate electrode 5 and the dummy gate electrode 15 are made of, for example, polysilicon containing n-type impurities. Further, it is made of a semiconductor such as silicon.

  A feature of the semiconductor device of this embodiment is that a substance that does not affect carrier generation is introduced into the dummy gate electrode 15 to reduce the lattice constant of the material constituting the dummy gate electrode 15. On the other hand, the substance is not introduced into the gate electrode 5. For example, carbon (C) is preferably used as the material introduced into the dummy gate electrode 15, but other materials may be used as long as the above-described conditions are satisfied. “To make the lattice constant of the material constituting the dummy gate electrode 15 small” means “to make the lattice constant of the dummy gate electrode 15 smaller than when no impurity is introduced”.

  In the MISFET of this embodiment, a substance for reducing the lattice constant is introduced into the dummy gate electrode 15. Therefore, as shown in FIG. 6A, an intra-film extension stress 70 is generated in the dummy gate electrode 15, and an extension stress 45 in the substrate normal direction is applied from the substrate 1 toward the dummy gate electrode 15. Due to the extension stress 45, a compressive stress 72 is applied to a portion of the substrate 1 located below the dummy gate electrode 15. In other words, the compressive stress 72 is the extension stress 71 in the channel direction applied to the channel of the MISFET 90. Therefore, the carrier mobility of the N channel type MISFET 90 is greatly improved.

  Furthermore, in the semiconductor device of this embodiment, impurities such as C that change the lattice constant are not introduced into the gate electrode 5 of the MISFET 90. Therefore, in the semiconductor device of this embodiment, the gate insulating film is not deteriorated, which becomes a problem when impurities are introduced into the gate electrode. Further, the influence of the introduced impurity on the gate insulating film 4 can be reduced as compared with the first embodiment in which the impurity is introduced into the portion of the gate electrode 5 provided on the element isolation region 3. Therefore, the concentration of impurities such as C contained in the dummy gate electrode 15 can be increased without worrying about deterioration of the gate insulating film 4, and a stronger extension stress 71 in the channel direction can be applied to the channel region. .

Impurities such as C can be introduced into the dummy gate electrode 15 by ion implantation, for example. The dose when C is implanted into the dummy gate electrode 15 made of polysilicon can be, for example, 1 × 10 ¹⁵ cm ⁻² or more.

  The impurity introduced into the dummy gate electrode 15 is not limited to C, but may be any material that can reduce the lattice constant of the dummy gate electrode 15. In particular, it is preferable that the material is the same as the material of the gate electrode in the periodic table because it does not affect the generation of carriers in the MISFET 90.

  The dummy gate insulating film 4a and the dummy gate electrode 15 only have to be provided at least partially on the active region 2, and a part thereof is provided on the element isolation region 3, and the impurity diffusion region 6a is provided on the dummy gate electrode 15. Even when it is formed only on one side, the extension stress 71 can be applied to the channel of the MISFET 90.

  6 shows an example in which the dummy gate electrode 15 is provided so as to face the channel direction (gate length direction) when viewed from the MISFET 90, but the dummy gate electrode 15 facing only one side as seen from the MISFET 90 is provided. It may be done.

  In the semiconductor device according to the present embodiment, since the extension stress in the gate length direction is applied to the channel of the MISFET 90, the mobility of the MISFET such as the <110> channel orientation and the <100> channel orientation can be improved.

  In the semiconductor device of this embodiment, an impurity such as C may be introduced only into the dummy gate electrode 15, but the impurity is also introduced into a portion of the impurity diffusion region of the MISFET 90 located near the dummy gate electrode 15. May be. In this case, it is preferable to use an impurity having no conductivity type. In this case, in-film extension stress is generated in the portion where the impurities are implanted, and the extension stress in the channel direction is applied to the channel of the MISFET 90, so that the carrier mobility can be further improved. In this way, when C is introduced into the dummy gate electrode 15, C may be introduced into the impurity diffusion region in the vicinity thereof, so that it is not necessary to perform mask alignment strictly, and manufacturing is facilitated. .

  In the semiconductor device of this embodiment, an impurity such as Ge or Sn that increases the lattice constant of polysilicon may be further introduced into the portion of the gate electrode 5 provided on the element isolation region 3.

(Seventh embodiment)
As a seventh embodiment of the present invention, a method for manufacturing a semiconductor device according to a sixth embodiment will be described. 7A to 7E are cross-sectional views showing a method for manufacturing a MISFET according to the seventh embodiment.

First, as shown in FIG. 7A, p-type impurities such as boron (B) are ion-implanted into a p-type substrate 1 (or a p-type semiconductor layer provided on the substrate 1). A p-type well 7 is formed. At this time, the implantation energy is, for example, 300 keV, and the dose is 1 × 10 ¹³ cm ⁻² . Next, a p-type impurity is implanted into a part of the p-type well 7 at an implantation energy of 150 keV and a dose of 1 × 10 ¹³ cm ⁻² to form a punch-through stopper. A p-type impurity (such as B) is implanted at an implantation energy of 20 keV and a dose of 5 × 10 ¹² cm ⁻² . Next, an element isolation region 3 surrounding an active region (not shown) is formed by a known method.

Next, as shown in FIG. 7B, a gate insulating film 4 having a thickness of 2 nm is formed on the substrate 1 (p-type well 7) by thermal oxidation, and then a polysilicon film having a thickness of 150 nm is formed on the substrate 1. (Gate material film) 18 is formed. Then, P ions are implanted into the polysilicon film 18 under conditions of an implantation energy of 10 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² .

  Subsequently, as shown in FIG. 7C, the polysilicon film 18 and the gate insulating film 4 are patterned by etching using a resist, and the gate electrode 5 extending from the gate insulating film 4 to the element isolation region 3 Then, dummy gate electrodes 15 disposed on both sides of the gate electrode 5 are formed. Further, a portion of the gate insulating film 4 located under the gate electrode 5 is left, and a portion of the gate insulating film 4 located under the dummy gate electrode 15 is left as the dummy gate insulating film 4a.

Next, after forming at least a resist 20 opening the dummy gate electrode 15 on the substrate, C is implanted into the dummy gate electrode 15 of the dummy transistor 95 under the conditions of an implantation energy of 200 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 7 (d), As is ion-implanted into regions located on both sides of the gate electrode 5 in the substrate 1 under conditions of an implantation energy of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . Impurity diffusion region 6a is formed.

  According to the above method, as shown in FIG. 7E, the in-film extension stress 70 is generated in the dummy gate electrode 15 and the extension stress 45 in the substrate normal direction is applied to the dummy gate electrode 15. it can. As a result, an extension stress in the channel direction can be applied to the channel region of the MISFET. Thus, according to the manufacturing method of the present embodiment, the MISFET described in the sixth embodiment can be manufactured relatively easily. It should be noted that an impurity other than C that reduces the lattice constant of the polysilicon film 18 may be introduced in the same manner as described above.

  In the ion implantation step shown in FIG. 7C, C may be implanted under a plurality of conditions in order to make the C distribution uniform within the dummy gate electrode 15. In this embodiment, C is implanted after the patterning of the polysilicon film 18, but it may be performed before the patterning of the polysilicon film 18 or before the P ion implantation into the polysilicon film 18. You may go.

-First modification of this embodiment-
As a first modification of the seventh embodiment of the present invention, a method of implanting C ions into the polysilicon film 18 before patterning will be described.

  8A to 8E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modification of the seventh embodiment.

  First, as shown in FIGS. 8A and 8B, the gate insulating film 4 and the polysilicon film 18 are sequentially formed on the substrate 1 by the same method as in the seventh embodiment, and P is applied to the polysilicon film 18. Ion implantation.

Next, as shown in FIG. 8C, after a resist 20 is formed on the polysilicon film 18 that opens at least a portion of the polysilicon film 18 that becomes the dummy gate electrode 15, an implantation energy of 200 keV and a dose of 1 are formed. C is implanted into the exposed portion of the polysilicon film 18 under the condition of × 10 ¹⁵ cm ⁻² . At this time, it is preferable to make the opening formed in the resist 20 larger than the portion formed as the dummy gate electrode 15 in consideration of the displacement of the resist 20.

  Next, as shown in FIG. 8D, after the resist 20 is removed, another resist is formed on the polysilicon film 18, and the gate electrode 5, the gate insulating film 4, and the gate electrode 5 are formed using this resist. The dummy gate electrode 15 and the dummy gate insulating film 4a disposed on both sides of the substrate are formed. Next, As is ion-implanted using the gate electrode 5 and the dummy gate electrode 15 as a mask, an impurity diffusion region 6a is formed.

  The semiconductor device according to the sixth embodiment can also be manufactured by the procedure as described above.

-Second modification of this embodiment-
9A to 9E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second modification of the seventh embodiment. In this modification, a method for manufacturing a semiconductor device in which C is introduced not only into the dummy gate electrode 15 but also into a part of the impurity diffusion region 6a of the MISFET will be described.

  First, as shown in FIGS. 9A and 9B, the gate insulating film 4 and the polysilicon film 18 are sequentially formed on the substrate 1 by the same method as in the seventh embodiment, and P is applied to the polysilicon film 18. Ion implantation.

  Next, as shown in FIG. 9C, the polysilicon film 18 and the gate insulating film 4 are patterned by etching using a resist, and the gate electrode 5, the gate insulating film 4 having a predetermined shape, and a dummy gate are formed. An electrode 15 and a dummy gate insulating film 4a are formed. Subsequently, a resist 20 that opens the dummy gate electrode 15 on the substrate 1 and a portion of the substrate 1 between the gate electrode 5 and the dummy gate electrode 15 and close to the dummy gate electrode 15 is formed on the substrate 1. To do. Then, C is ion-implanted using the resist 20 to introduce C into the dummy gate electrode 15 and a region of the substrate 1 located in the vicinity (downside) of the dummy gate electrode 15. Here, a portion including C in the substrate 1 is referred to as a tensile impurity region 66.

  Next, as shown in FIG. 9D, after removing the resist 20, As ions are implanted using the gate electrode 5 as a mask, and impurity diffusion regions are formed in regions of the substrate 1 located on both sides of the gate electrode 5. 6a is formed. Of the impurity diffusion region 6a, the tensile impurity region 66 provided below the dummy gate electrode 15 is a part of the impurity diffusion region 6a.

  In the semiconductor device manufactured as described above, as shown in FIG. 9E, the tensile energy region 66 applies tensile stress to the channel region of the MISFET after the thermal diffusion of the impurity. Therefore, according to the method according to this modification, an N-channel MISFET with improved carrier mobility can be manufactured.

(Eighth embodiment)
FIG. 10A is a perspective view showing a semiconductor device according to the eighth embodiment, and FIGS. 10B and 10C are a top view of a dummy transistor in the semiconductor device of this embodiment, and EE. It is sectional drawing in a location. The semiconductor device according to the present embodiment includes a P-channel type MISFET 90 and a dummy transistor that is disposed on both sides of the MISFET 90 and has a dummy gate electrode into which an impurity causing stress is introduced.

  The P-channel type MISFET 90 includes a gate insulating film 4, a gate electrode 5 containing p-type impurities, an impurity diffusion region 6b containing p-type impurities formed in regions of the substrate 1 located on both sides of the gate electrode 5, and have.

  The semiconductor device of this embodiment basically has the same configuration as the semiconductor device according to the sixth embodiment, but has the following characteristics.

  As the substrate 1 of the dummy transistor 95 and the MISFET 90, <110> channel orientation, <100> channel orientation, and the like are used.

  The dummy transistor 95 has a dummy gate insulating film 4b provided at least partially on the active region 2, and a dummy gate electrode 15 provided on the dummy gate insulating film 4b. The dummy gate electrode 15 is introduced with a substance that increases the lattice constant of the material (eg, polysilicon) of the dummy gate electrode 15 and does not affect carrier generation in the MISFET 90. Here, as the impurity introduced into the dummy gate electrode 15, Ge or Sn is particularly preferable, but other substances such as As and Ga may be used.

  Therefore, an in-film compressive stress 80 is generated inside the dummy gate electrode 15. The in-film compressive stress 80 causes a compressive stress 39 in the substrate normal direction in a region of the substrate 1 located below the dummy gate electrode 15, and compressive stress 73 in the channel direction (from the dummy transistor 95 in the channel region of the MISFET 90. The same as the extension stress 74 when viewed).

  The compressive stress 73 increases the carrier mobility when the substrate 1 is a silicon substrate whose main surface is a crystal plane other than the (100) plane, for example. Therefore, in the semiconductor device of this embodiment, the carrier mobility is improved in the MISFET 90 and the performance is improved.

  As described above, the MISFET of the present invention is used in various electronic devices.

It is a figure which shows the N channel type MISFET which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the AA location of Fig.1 (a), (c) is a perspective view FIG. It is a figure which shows P channel type MISFET concerning the 2nd Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the BB location of Fig.2 (a), (c) is a perspective view. FIG. It is a figure which shows the N channel type MISFET which concerns on the 3rd Embodiment of this invention, (a) is a top view, (b) is sectional drawing in CC location of Fig.3 (a), (c) is a perspective view. FIG. (A)-(d) is sectional drawing which shows the manufacturing method of MISFET which concerns on the 4th Embodiment of this invention. (A)-(d) is sectional drawing which shows the manufacturing method of MISFET based on the 5th Embodiment of this invention. It is a figure which shows the semiconductor device which concerns on the 6th Embodiment of this invention, (a) is a perspective view, (b) is a top view, (c) is sectional drawing in DD location of FIG.6 (b). It is. (A)-(e) is sectional drawing which shows the manufacturing method of MISFET which concerns on the 7th Embodiment of this invention. (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st modification of 7th Embodiment. (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd modification of 7th Embodiment. It is a figure which shows the semiconductor device which concerns on the 8th Embodiment of this invention, (a) is a perspective view, (b) is a top view, (c) is sectional drawing in the EE location of FIG.10 (b). It is. (A) is a perspective view showing the direction and type of stress for improving carrier mobility in an N-channel type MISFET, and (b) shows the direction and type of stress for improving carrier mobility in a P-channel type MISFET. It is a perspective view shown. It is a perspective view which shows N channel type MISFET produced using the silicon substrate which makes a (100) plane the main surface. It is a figure which shows the conventional N channel type MISFET, (a) is a top view, (b) is sectional drawing in the XX location of Fig.13 (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Active region 3 Element isolation region 4 Gate insulating film 4a, 4b Dummy gate insulating film 5 Gate electrode 6a Impurity diffusion region containing n-type impurity 6b Impurity diffusion region containing p-type impurity 7 P-type well 15 Dummy gate electrode 18 Polysilicon film 20 Resist 25a, 41a, 51a Portion of gate electrode on element isolation region 25b, 41b, 51b Portion of gate electrode on active region 27, 54, 55 In-film compressive stress 29, 39 47, 49, 71, 73 Compressive stress 31, 33, 45, 74 Extension stress 43, 70 In-film extension stress 66 Tensile impurity region 90 MISFET
95 Dummy transistor

Claims (32)

A substrate on which an active region is formed;
An element isolation region formed on the substrate and surrounding the active region;
A gate insulating film formed on the active region;
A gate electrode provided from above the gate insulating film to the element isolation region;
An impurity diffusion region including a first impurity having a conductivity type formed in a region located on both sides of the gate electrode in the active region,
The gate electrode has a first portion located on the element isolation region and a second portion located on the active region,
The semiconductor device in which the first portion of the gate electrode includes a greater stress than the second portion of the gate electrode.   The semiconductor device according to claim 1, wherein the first portion of the gate electrode includes a second impurity that changes a lattice constant of the gate electrode.   3. The semiconductor device according to claim 2, wherein the second portion of the gate electrode contains the second impurity at a lower concentration than the first portion of the gate electrode.   The semiconductor device according to claim 2, wherein the second impurity is an impurity having no conductivity type. The first impurity is an n-type impurity;
The semiconductor device according to claim 2, wherein the second impurity is an impurity that increases a lattice constant of the gate electrode. The gate electrode is made of polysilicon,
6. The semiconductor device according to claim 2, wherein the second impurity is germanium. The first impurity is an n-type impurity;
The semiconductor device according to claim 2, wherein the second impurity is an impurity having the same conductivity type as the first impurity. The first impurity is a p-type impurity;
The semiconductor device according to claim 2, wherein the second impurity is an impurity that reduces a lattice constant of the gate electrode. The gate electrode is made of polysilicon,
9. The semiconductor device according to claim 2, wherein the second impurity is carbon.   A dummy gate electrode provided on or above the substrate, facing the gate electrode across one of the impurity diffusion regions, and including a third impurity that changes a lattice constant inherent in the constituent material; The semiconductor device according to claim 1, wherein: The first impurity is an n-type impurity;
The semiconductor device according to claim 10, wherein the third impurity is an impurity that reduces a lattice constant of the dummy gate electrode. The dummy gate electrode is made of polysilicon,
The semiconductor device according to claim 11, wherein the third impurity is carbon. The first impurity is a p-type impurity;
The semiconductor device according to claim 10, wherein the third impurity is an impurity that increases a lattice constant of the dummy gate electrode. The dummy gate electrode is made of polysilicon,
The semiconductor device according to claim 13, wherein the third impurity is germanium or tin.   15. The semiconductor device according to claim 10, wherein the third impurity is contained in a region located below the dummy gate electrode in the impurity diffusion region. .   16. The semiconductor device according to claim 10, wherein the dummy gate electrode is provided above or above the element isolation region and the active region. A substrate on which an active region is formed;
An element isolation region formed on the substrate and surrounding the active region;
A gate insulating film formed on the active region;
A gate electrode provided on the gate insulating film;
An impurity diffusion region formed in a region located on both sides of the gate electrode in the active region and including a first impurity having a conductivity type;
A dummy gate electrode provided on or above the substrate, facing the gate electrode across one of the impurity diffusion regions, and including a second impurity that changes the original lattice constant of the constituent material; Semiconductor device. The first impurity is an n-type impurity;
The semiconductor device according to claim 17, wherein the second impurity is an impurity that reduces a lattice constant of the dummy gate electrode. The first impurity is a p-type impurity;
The semiconductor device according to claim 17, wherein the second impurity is an impurity that increases a lattice constant of the dummy gate electrode. A step (a) of forming an element isolation region on the substrate;
Forming a gate insulating film on the active region made of the substrate surrounded by the element isolation region;
Forming a gate electrode from above the gate insulating film over the element isolation region;
A step (d) of adding a larger stress to the first portion of the gate electrode located on the element isolation region than the second portion of the gate electrode located on the active region;
And (e) forming an impurity diffusion region containing a first impurity having a conductivity type in a region located on both sides of the gate electrode in the active region.   In the step (d), a second impurity that changes a lattice constant of the gate electrode is selectively implanted into the first portion of the gate electrode to thereby form the second portion of the gate electrode. 21. The method of manufacturing a semiconductor device according to claim 20, further comprising a greater stress than that of the semiconductor device.   In the step (c), the patterned second gate electrode is implanted with the second impurity having a dose smaller than the dose of the second impurity implanted in the step (d). The method of manufacturing a semiconductor device according to claim 21.   23. The method of manufacturing a semiconductor device according to claim 21, wherein the second impurity is an impurity having no conductivity type. The first impurity is an n-type impurity;
24. The method of manufacturing a semiconductor device according to claim 21, wherein the second impurity is an impurity that increases a lattice constant of the gate electrode. The first impurity is a p-type impurity;
24. The method of manufacturing a semiconductor device according to claim 21, wherein the second impurity is an impurity that reduces a lattice constant of the gate electrode. A step (f) of forming a dummy gate electrode including a third impurity that changes a lattice constant inherent to the constituent material on a side of the gate electrode;
26. The method of manufacturing a semiconductor device according to claim 20, wherein in the step (e), the impurity diffusion region is formed between the dummy gate electrode and the gate electrode. Forming an element isolation region surrounding the active region on a substrate having the active region (a);
A step (b) of forming a gate insulating film and a gate electrode on the active region;
Forming a dummy gate electrode including a first impurity that changes a lattice constant of a constituent material at least above or above a part of the active region and on a side of the gate electrode; and
Forming an impurity diffusion region containing a second impurity having a conductivity type in a region located on both sides of the gate electrode including a region between the gate electrode and the dummy gate electrode in the active region ( and d) a semiconductor device manufacturing method. The step (c)
Forming a gate material film above the substrate (c1);
Patterning the gate material film to form the dummy gate electrode on the side of the gate electrode (c2);
A step (c3) of introducing the first impurity that changes the lattice constant of the gate material film into at least the dummy gate electrode,
28. The method of manufacturing a semiconductor device according to claim 27, wherein the step (c2) is performed simultaneously with the step (b). In the step (c3), the first impurity is also introduced into a portion of the active region that is located between the gate electrode and the dummy gate electrode and in the vicinity of the dummy gate electrode, thereby forming a tensil impurity region. Forming,
29. The method of manufacturing a semiconductor device according to claim 28, wherein in the step (d), the impurity diffusion region is formed in the active region including the tensil impurity region. The step (c)
Forming a gate material film above the substrate (c4);
Introducing the first impurity that changes the lattice constant of the gate material film into a part of the gate material film (c5);
Patterning the gate material film to form the dummy gate electrode containing the first impurity (c6),
The step (c6) is performed simultaneously with the step (b), and the gate electrode formed in the step (b) is implanted with the first impurity in the step (c5) of the gate material film. 28. The method of manufacturing a semiconductor device according to claim 27, wherein the method comprises a portion that is not provided. The second impurity is an n-type impurity;
31. The method of manufacturing a semiconductor device according to claim 27, wherein the first impurity is an impurity that reduces a lattice constant of the gate material film. The second impurity is a p-type impurity;
31. The method of manufacturing a semiconductor device according to claim 27, wherein the first impurity is an impurity that increases a lattice constant of the gate material film.

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