RU2803406C1 - High-speed fuzzy inference device based on area ration defuzzifier (modification 2) - Google Patents

Abstract

FIELD: computing devices.

SUBSTANCE: invention can be used in information processing devices based on fuzzy logic. The device contains a generator block for generating a control signal CSGGU, a fuzzification block for the first incoming variable BFIV1, a fuzzification block for the second incoming variable BFIV2, a BI implication block, and a high-speed defuzzifier BD.

EFFECT: increase of speed of the device and generation and transformation of input data into a single clear value at the output of a fuzzy logic system.

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Description

The invention relates to the field of computing devices and software algorithms and can be used in information processing systems and devices built on the basis of fuzzy logic.

A defuzzification device is known based on the area ratio method [RF Patent No. 2 701 841, G06E 3/00, G06N 7/02 (analogue)].

A sign of an analog that coincides with the existing claimed device is the use of fuzzy logic in the fuzzy-logical inference algorithm, and the presence of a defuzzification stage in its structure.

The disadvantage of the described device is the low data processing speed.

A high-speed defuzzifier using triangular membership functions is known [RF Patent No. 2 760 632, G06F 3/00, G06N 7/02 (prototype)].

A feature of the prototype that coincides with the existing claimed device is the use of defuzzification in the structure of the fuzzy inference algorithm to obtain the resulting value.

Disadvantages of this prototype: the complexity of the defuzzifier device, due to the presence of a 5-layer analyzer, which increases the execution time of operations, thereby reducing performance; absence of fuzzification and fuzzy implication operations, i.e. absence of all fuzzy logic inference blocks.

The technical objective of the invention is to increase the computational performance of the defuzzification process to 130 ns and simplify the structure of the device.

The technical problem is solved by eliminating the 5-layer analyzer from the defuzzifier, which makes it possible to increase the computational performance of the defuzzification process and simplify the structure of the device.

The technical result of a high-speed fuzzy logic inference device based on an area ratio defuzzifier (Modification 2) is the generation and transformation of input data into a single clear value at the output of the fuzzy logic system.

The invention is illustrated by drawings: FIG. 1 - High-speed fuzzy logic inference device based on a defuzzifier for the ratio of areas of membership functions (Modification 2); fig. 2 - Control signal generator block; fig. 3 - Fuzzification block of the first input variable; fig. 4 - Fuzzification block of the second input variable; fig. 5 - Triangular function generation block; fig. 6 - Implication block; fig. 7 - Defuzzification block; fig. 8 - Triangular membership function; fig. 9 - Simulation results in the ISE Design v program. 14.7, written in the VHDL programming language.

A high-speed fuzzy logic inference device based on a defuzzifier for the ratio of areas of membership functions (Modification 2) (Fig. 1) contains a generator block for generating a control signal BGUS 1, a fuzzification block of the first input variable BFVP1 2, a fuzzification block of the second input variable BFVP2 3, an implication block BI 4, fast DB defuzzifier 5.

The generator block for generating the control signal BGUS 1 (Fig. 2) contains a block of input variables (control signals coming from various types of sensors) “a” 1.1 and “b” 1.3, counters CLCK 1.2, 1.4, amplifiers GAIN 1.5, 1.6, adders ADD 1.7, 1.8.

Connections in BGUS 1 are defined as follows. The output of the variable block “a” 1.1 is connected to the first input of the adder ADD1 1.7. Exit

counter CLCK1 1.2 is connected to the input of the amplifier GAIN1 1.5. The output of the amplifier GAIN1 1.5 is connected to the second input of the adder ADD1 1.7. The output of the variable block “b” 1.3 is connected to the first input of the adder ADD2 1.8. The output of the counter CLCK2 1.4 is connected to the input of the amplifier GAIN2 1.6. The output of the amplifier GAIN2 1.6 is connected to the second input of the adder ADD2 1.8. The output signals “A” and “B” of the block from blocks ADD1 1.7 and ADD2 1.8 are output from BGUS 1 and are connected to the inputs of BFVP1 2 and BFVP2 3, respectively.

The fuzzification block of the first input variable BFVP1 2 (Fig. 3) contains blocks of variables “a1” 2.1, “a2” 2.2, “a3” 2.3, “a4” 2.4, “a5” 2.5, a block for generating the first triangular function BFTF1 2.6, a formation block the second triangular function BFTF2 2.7, the block for generating the third triangular function BFTF3 2.8.

The connections in BFVP1 2 are defined as follows. The variable block “a1” 2.1 is connected to the input of the block BFTF1 2.6. The variable block “a2” 2.2 is connected to the inputs of the blocks BFTF1 2.6 and BFTF2 2.7. The variable block “a3” 2.3 is connected to the inputs of the blocks BFTF1 2.6, BFTF2 2.7 and BFTF3 2.8. The variable block “a4” 2.4 is connected to the inputs of the blocks BFTF2 2.7 and BFTF3 2.8. The variable block “a5” 2.5 is connected to the input of the block BFTF3 2.8. Input signal “A” is connected to the inputs of the blocks BFTF1 2.6, BFTF2 2.7, BFTTF3 2.8. Signals “A1”, “A2”, “A3” coming from BFTF1 2.6, BFTF2 2.7, BFTF3 2.8, respectively, are coming out of BFVP1 2 and are connected to the first 3 inputs of BI 3.

The block for generating the first triangular function BFTF1 2.6 (Fig. 5) contains comparators CMP 2.6.1÷2.6.4, subtractors SUB 2.6.5÷2.6.8, block OR 2.6.9, block AND 2.6.10, dividers DIV 2.6.11 , 2.6.12, constant “0” 2.6.13, SWITCH keys 2.6.14,2.6.15.

Connections in BFTF1 2.6 are defined as follows. The variable “a1” is connected to the second input of the comparator CMP1 2.6.1, the second input of the comparator CMP3 2.6.3, the second input of the subtractor SUB1 2.6.5 and the second

subtractor house SUB2 2.6.6. The variable “a2” is connected to the second input of the comparator CMP4 2.6.4, the first input of the subtractor SUB2 2.6.6 and the second input of the subtractor SUB4 2.6.8. Variable “a3” is connected to the second input of the comparator CMP2 2.6.2, the first input of the subtractor SUB3 2.6.7 and the first input of the subtractor SUB4 2.6.8. Input signal “A” is connected to the first input of the comparator CMP1 2.6.1, the first input of the comparator CMP2 2.6.2, the first input of the comparator CMP3 2.6.3, the first input of the comparator CMP4 2.6.4, the first input of the subtractor SUB1 2.6.5, the second input of the subtractor SUB3 2.6.7. The output signals “<” and “=” of the comparator CMP1 2.6.1 are interconnected and connected to the first input of the OR 2.6.9 block. The output signals “>” and “=” of the comparator CMP2 2.6.2 are interconnected and connected to the second input of the OR 2.6.9 block. The output signals “>” and “=” of the comparator CMP3 2.6.3 are interconnected and connected to the first input of the AND block 2.6.10. The output signals “<” and “=” of the CMP4 2.6.4 comparator are interconnected and connected to the second input of the AND 2.6.10 block. The output signal of the subtractor SUB1 2.6.5 is connected to the first input of the divider DIV1 2.6.11. The output signal of the subtractor SUB2 2.6.6 is connected to the second input of the divider DIV1 2.6.11 The output signal of the subtractor SUB3 2.6.7 is connected to the first input of the divider DIV2 2.6.12. The output signal of the subtractor SUB4 2.6.8 is connected to the second input of the divider DIV2 2.6.12. The output signal of the OR 2.6.9 block is connected to the second input (>0) of the SWITCH2 2.6.15 key. The output signal of the AND 2.6.10 block is connected to the second input (>0) of the SWITCH2 2.6.14 key. The output signal of the divider DIV1 2.6.11 is connected to the first input (True) of the SWITCH1 2.6.14 key. The output signal of the divider DIV2 2.6.12 is connected to the third input (False) of the SWITCH1 2.6.14 key. The output signal of the constant “0” 2.6.13 is connected to the first input (True) of the SWITCH2 key 2.6.15. The output signal of the SWITCH1 2.6.14 key is connected to the third input (False) of the SWITCH2 2.6.15 key. The “A1” signal is the output signal of the BFTF1 2.6 block, which comes out of the SWITCH2 2.6.15 key.

The block for generating the second triangular function BFTF2 2.7 (Fig. 5) contains comparators SMR 2.7.1÷2.7.4, subtractors SUB 2.7.5÷2.7.8, block OR 2.7.9, block AND 2.7.10, dividers DIV 2.7.11 , 2.7.12, constant “0” 2.7.13, SWITCH keys 2.7.14, 2.7.15. Connections in BFTF2 2.7 are defined similarly to the BFTF1 2.6 block.

The block for generating the third triangular function BFTF3 2.8 (Fig. 5) contains comparators SMR 2.8.1÷2.8.4, subtractors SUB 2.8.5÷2.8.8, block OR 2.8.9, block AND 2.8.10, dividers DIV 2.8.11 , 2.8.12, constant “0” 2.8.13, SWITCH keys 2.8.14, 2.8.15. Connections in BFTF3 2.8 are defined similarly to the BFTF1 2.6 block.

The fuzzification block of the second input variable BFVP2 3 (Fig. 4) contains blocks of variables “b1” 3.1, “b2” 3.2, “b3” 3.3, “b4” 3.4, “b5” 3.5, a block for generating the first triangular function BFTF1 3.6, a formation block the second triangular function BFTF2 3.7, the block for generating the third triangular function BFTF3 3.8. Connections in BFVP2 3 are determined similarly to the block BFVP1 2.

The block for generating the first triangular function BFTF1 3.6 (Fig. 5) contains comparators SMR 3.6.1÷3.6.4, subtractors SUB 3.6.5÷3.6.8, block OR 3.6.9, block AND 3.6.10, dividers DIV 3.6.11 , 3.6.12, constant “0” 3.6.13, SWITCH keys 3.6.14, 3.6.15. Connections in BFTF1 3.6 are defined similarly to the BFTF1 2.6 block.

The block for generating the second triangular function BFTF2 3.7 (Fig. 5) contains comparators SMR 3.7.1÷3.7.4, subtractors SUB 3.7.5÷3.7.8, block OR 3.7.9, block AND 3.7.10, dividers DIV 3.7.11 , 3.7.12, constant “0” 3.7.13, SWITCH keys 3.7.14, 3.7.15. Connections in BFTF2 3.7 are defined similarly to the BFTF1 2.6 block.

The block for generating the third triangular function BFTF3 3.8 (Fig. 5) contains comparators SMR 3.8.1÷3.8.4, subtractors SUB 3.8.5÷3.8.8, block OR 3.8.9, block AND 3.8.10, dividers DIV 3.8.11 , 3.8.12, constant “0” 3.8.13, SWITCH keys 3.8.14, 3.8.15.

Connections in BFTF3 3.8 are defined similarly to the BFTF1 2.6 block.

The implication block BI 4 (Fig. 6) contains blocks MIN 4.1÷4.9 and blocks MAX 4.10÷4.12.

Relationships in BI 4 are defined as follows. Input signal “A1” is connected to the first input of the MIN1 4.1 block, to the first input of the MIN2 4.2 block, and to the first input of the MIN3 4.3 block. Input signal “A2” is connected to the first input of the MIN4 4.4 block, to the first input of the MIN5 4.5 block, to the first input of the MIN6 4.6 block. Input signal “A3” is connected to the first input of the MIN7 4.7 block, to the first input of the MIN8 4.8 block, to the first input of the MIN9 4.9 block. Input signal “B1” is connected to the second input of the MIN1 4.1 block, to the second input of the MIN4 4.4 block, to the second input of the MIN7 4.7 block. Input signal “B2” is connected to the second input of the MIN2 4.2 block, to the second input of the MIN5 4.5 block, to the second input of the MIN8 4.8 block. Input signal “B3” is connected to the second input of the MIN3 4.3 block, to the second input of the MIN6 4.6 block, to the second input of the MIN9 4.9 block. The output signal from the MIN2 4.2 block is connected to the first input of the MAX1 4.10 block. The output signal from the MIN3 4.3 block is connected to the first input of the MAX2 4.11 block. The output signal from the MIN4 4.4 block is connected to the second input of the MAX1 4.10 block. The output signal from the MIN5 4.5 block is connected to the second input of the MAX2 4.11 block. The output signal from the MIN6 4.6 block is connected to the first input of the MAX3 4.12 block. The output signal from the MIN7 4.7 block is connected to the third input of the MAX2 4.11 block. The output signal from the MIN8 4.8 block is connected to the second input of the MAX3 4.12 block. Signals “M1”, “M2”, “M3”, “M4”, “M5” coming from blocks MIN1 4.1, MAX1 4.10, MAX2 4.11, MAX3 4.12, MIN9 4.9 are coming from block BI 4 and are connected to the inputs of BD 5.

The high-speed defuzzifier block DB 5 contains adders ADD 5.1, 5.8, variable block “n” 5.2, divider DIV 5.3, variable block “Ymax” 5.4, variable block “Ymin” 5.5, multiplier MUL 5.6, subtractor SUB 5.7.

Relationships in DB 5 are defined as follows. Input signals “M1”, “M2”, “M3”, “M4”, “M5” are connected to the inputs of the adder ADD1 5.1. The output signal of the adder ADD1 5.1 is connected to the first input of the divider DIV 5.3. The output signal of the variable block “n” 5.2 is connected to the second input of the divider DIV 5.3. The output signal of the DIV 5.3 divider is connected to the first input of the MUL 5.6 multiplier. The output signal of the variable block “Ymax” 5.4 is connected to the first input of the subtractor SUB 5.7. The output signal of the variable block “Ymin” 5.5 is connected to the second input of the subtractor SUB 5.7 and the first input of the adder ADD2 5.8. The output signal of the SUB 5.7 subtractor is connected to the second input of the MUL 5.6 multiplier. The output signal of the MUL 5.6 multiplier is connected to the second input of the ADD2 5.8 adder. The “MAR2” signal comes out of the adder ADD2 5.8. The output signal “MAR2” of the DB block 5 is the output signal of a high-speed fuzzy logic inference device based on an area ratio defuzzifier (Modification 2).

The operating principle of a high-speed fuzzy logic inference device based on an area ratio defuzzifier (Modification 2) consists of four steps. Signals of two variables “A” and “B” are generated in block 1 of the BGUS. Next, variable “A” enters block 2 of BFVP1, and variable “B” is transferred to block 3 of BFVP2. In block 2 of BFVP1 the first three triangular functions “A1”, “A2”, “A3” are generated, and in block 3 of BFVP2 the second three triangular functions “B1”, “B2”, “B3” are generated. Each of the triangular membership functions has the form similar to Fig. 8. Triangular functions “A1”, “A2”, “A3”, “B1”, “B2”, “B3” are transferred to block 4 BI, where they are implicated. As a result, at the output of block 4 BI, 5 variables “M1”, “M2”, “M3”, “M4”, “M5” are transmitted to block 5 DB. In block 5 of the database, the defuzzification process occurs, during which the resulting variable “MAR2” is calculated. The output of the result variable “MAR2” in a high-speed fuzzy logic inference device based on an area ratio defuzzifier (Modification 2) is carried out in four steps:

Step 1. Generating input variables by counters:

where clck ₁ is the signal from block 1.2, gain ₁ is the signal from block 1.5, clck ₂ is the signal from block 1.4, gain ₂ is the signal from block 1.6, a is the signal from block 1.1, b is the signal from block 1.3 (signals “a” ", "b" - signals from real sensors received from control systems) (Fig. 2).

Step 2. Formation of a triangular membership function according to the formula:

where s is the input signal A or B coming from block 1 (Fig. 1, Fig. 3, Fig. 4), x, y, z are value signals stored in blocks 2.1÷2.5 and 3.1÷3.5. The variables x, y, z are selected depending on the required form of the triangular membership function shown in Fig. 8. As a result of this operation, three output signals “A1”, “A2” and “A3” are formed at the output of the BFVP1 block, and “B1”, “B2”, and “B3” are formed at the output of the BFVP2 block. An example of their calculation is presented below (step 2).

Step 3. Signals “A1”, “A2”, “A3”, “B1”, “B2”, “B3” come from the outputs of the BFVP1, BFVP2 blocks to the inputs of the BI block. The process of implication of input variables is calculated according to established fuzzy rules:

The output signals of the block are M1, M2, M3, M4, M5, and the variable M1 is calculated in block 4.1, M2 is calculated in block 4.10, M3 is calculated in block 4.11, M4 is calculated in block 4.12, M5 is calculated in block 4.9.

Step 4. Defuzzification process. Determination of the output value after defuzzification based on the area ratio method according to formula (9):

where M _i is the value of the signal M from block 4, n is the number of fuzzy membership functions, Y _max is the signal from block 5.4, Y _min is the signal from block 5.5.

To find the difference between Y _max and Y _min , input signals Y _max and Y _min are supplied to the inputs of the subtraction block SUB 5.7. To calculate equation (9), ten-bit values Y _min n Y _max are supplied to the input of the SUB 5.7 subtractor. The input of the multiplier MUL 5.6 is supplied with the value of the output of the subtractor SUB 5.7, which determines the value of the domain of definition of the output membership function, and the second input of the multiplier MUL 5.6 is supplied with D, obtained at the output of the divider DIV 5.3. The output of the MUL 5.6 multiplier is connected to the input of the ADD2 5.8 adder. The value Y _min is supplied to the second input of the adder ADD2 5.8. At the output of the ADD2 5.8 adder, the ten-bit output value after defuzzification is calculated based on the MAR2 area ratio method.

An example of numerical simulation of the operation of a high-speed fuzzy logic inference device based on an area ratio defuzzifier (Modification 2).

Step 1. The control signal is calculated using formulas (1) and (2). Let clck ₁ ,clck ₂ =6, gain ₁ =4, gain ₂ =0.02, a=20, b=0.4. Then:

A=6 * 4+20=44.

B=6 * 0.02+0.4=0.52.

Step 2. Next, using formula (3), the triangular sections of the membership function are calculated. Taking into account that a ₁ =20, a ₂ =40, a ₃ =60, a ₄ =80, a ₅ =100, b ₁ =0.4, b ₂ =0.5, b ₃ =0.6, b ₄ =0.7, b ₅ =0.8, A=44, B=0.52, then to process the membership functions the following calculation is performed:

Cases A2, A3, B1, B2, B3 are considered similarly.

Step 3. The process of implication of input variables according to established fuzzy rules according to formulas (4), (5), (6), (7), (8):

Step 4. Determine the output value after defuzzification based on the area ratio method according to formula (9). Let n=5, Y _max =250, Y _min =210:

A simulation was carried out in the ISE Designer program written in the VHDL programming language, showing the performance of the defuzzification device based on the area ratio method is about 130 ns (Fig. 9).

Thus, a high-speed fuzzy logic inference device based on a defuzzifier for the ratio of areas of membership functions (Modification 2) allows you to determine a single value after defuzzification and provides increased performance by simplifying the structure of the defuzzifier.

Claims (1)

A high-speed fuzzy logic inference device based on a defuzzifier for the area ratio of membership functions, containing a defuzzification block, characterized in that it contains a control signal generator block, the outputs of which are connected to the inputs of the fuzzification block of the first input variable and the fuzzification block of the second input variable, three outputs of which are connected to six inputs of the implication block, the five outputs of which are connected to the five inputs of the defuzzification block, containing adders ADD1 and ADD2, variable block “n”, divider DIV, variable block “Y _max ”, variable block “Y _min ”, subtractor SUB, multiplier MUL, in this case, the outputs of the implication block are connected to the inputs of the adder ADD1, the output of which is connected to the first input of the divider DIV, the second input of which is connected to the output of the variable block "n", and the output is connected to the first input of the multiplier MUL, the output of the variable block "Y _max " is connected to the first input of the subtractor SUB, the output of the variable block "Y _min " is connected to the second input of the subtractor SUB and the first input of the adder ADD2, the output of the subtractor SUB is connected to the second input of the multiplier MUL, the output of which is connected to the second input of the adder ADD2, the output of which is the output of the defuzzification block and is the output of the device.