RU2800491C1 - Display module and electronic device - Google Patents

Abstract

FIELD: display technologies.

SUBSTANCE: invention provides a display module and an electronic device. The display module includes a display, a display drive circuit, and at least one group of drivers; the display includes M rows of subpixels arranged in a matrix; each group of exciters includes M gating circuits; the Nth gating circuit is configured to: receive the first initial voltage Vinit1 and the second initial voltage Vinit2 from the display drive circuit, output the second initial voltage Vinit2 to the second electrode of the first reset transistor and the first electrode of the voltage modulation transistor, and output the first initial voltage Vinit1 to the second electrode of the first reset transistor and the first electrode of the voltage modulation transistor; and the first initial voltage Vinit1 satisfies at least one of the following conditions: Vinit1> Vinit2 and Vinit1> (ELVSS+Voled), where ELVSS is the voltage output to the second supply voltage input pin, and Voled is the voltage drop across the light emitting component.

EFFECT: reduced flickering of the display that occurs when the display shows an image with a low refresh rate.

10 cl, 23 dwg, 2 tbl

Description

The field of technology to which the invention belongs

The present application relates generally to the field of display technologies and in particular to a display module and an electronic device.

State of the art

With the continuous development of display technologies, an electronic device such as a mobile phone can display both a dynamic image and a static image. When some dynamic images are displayed, it is necessary to increase the image refresh rate (namely, the number of times the image is updated per second) to reduce dynamic blurring. However, when a static image, such as an idle image, is displayed, the relatively high refresh rate causes an increase in the power consumption of the electronic device. To reduce power consumption, a relatively low refresh rate can be used when the electronic device displays a static image. However, in this case, display flicker occurs on the electronic device and the display effect is reduced.

The essence of the invention

Embodiments of the present application provide a display module and an electronic device for reducing the occurrence of display flicker when the display is displaying an image at a low refresh rate.

To solve the above problem in the embodiments of the present application, the following technical solutions are used.

According to a first aspect of embodiments of the present application, a display module is provided, including a display, a display drive circuit, and at least one group of drivers. The display includes M rows of subpixels arranged in a matrix, and the pixel circuit of each subpixel includes a first compensation transistor, a second compensation transistor, a voltage modulation transistor, a drive transistor, a first reset transistor, a first capacitor, and a light emitting component, where M≥2 , and M is a positive integer. The first electrode of the first compensation transistor is connected to the second electrode of the second compensation transistor and the second electrode of the voltage modulation transistor, the second electrode of the first compensation transistor is connected to the gate of the drive transistor, and the first electrode of the output of the first capacitor is connected to the first electrode of the first reset transistor; the first electrode of the second compensation transistor is connected to the second electrode of the drive transistor and the anode of the light emitting component, and the gate of the first compensation transistor and the gate of the second compensation transistor are configured to receive the gate signal N; the first electrode of the voltage modulation transistor is connected to the second electrode of the first reset transistor, and the gate of the voltage modulation transistor is configured to receive a light emission control signal; the second output of the first capacitor is connected to the first input of the supply voltage; the first electrode of the drive transistor is connected to a first supply voltage input or a data voltage output port of the display drive circuit; the gate of the first reset transistor is configured to receive the gate signal N-1; and the cathode of the light emitting component is connected to the second supply voltage input terminal, where 1≤N≤M and N is a positive integer. The first electrode is a source and the second electrode is a drain, or the first electrode is a drain and the second electrode is a source, the first supply voltage input terminal is configured to input the first supply voltage, and the data voltage output port is configured to output the data voltage. Each driver group includes M gating circuits; The ^N'th gate circuit is connected to the second electrode of the first reset transistor in the ^N'th subpixel row pixel circuit and to the first electrode of the voltage modulation transistor in the ^N'th subpixel row pixel circuit; The N ^-th gate circuit is additionally connected to the display drive circuit and configured to: receive the first initial voltage Vinit1 and the second initial voltage Vinit2 from the display drive circuit, output the second initial voltage Vinit2 to the second electrode of the first reset transistor and the first electrode of the voltage modulation transistor, when the pixel circuit is in a reset phase and a data voltage write phase, and outputting the first initial voltage Vinit1 to the second electrode of the first reset transistor and the first voltage electrode of the modulation transistor when the pixel circuit is in the light emitting phase; and the first initial voltage Vinit1 satisfies at least one of the following conditions: Vinit1>Vinit2 and Vinit1>(ELVSS+Voled), where ELVSS is the voltage output to the second supply voltage input pin and Voled is the voltage drop across the light emitting component. The reset phase is the phase in which the first reset transistor is turned on, the data voltage writing phase is the phase in which the data voltage is applied to the first electrode of the drive transistor, and the light emission phase is the phase in which the light emitting component emits light.

According to the display module provided in the embodiments of the present application, the leakage current of the first reset transistor and the leakage current of the compensation transistor are reduced, so that when using a low refresh rate, the possibility of display flickering caused by a relatively large voltage drop at the gate of the drive transistor in the light emission phase is reduced. due to leakage current. In particular, for the first reset transistor and the compensation transistor, the leakage current of the first reset transistor and the leakage current of the compensation transistor can be reduced by reducing the source-to-drain voltage of the first reset transistor and the source-to-drain voltage of the compensation transistor. Since the source-drain of the first compensation transistor and the source-drain of the second compensation transistor are connected in series, the leakage current of the first compensation transistor directly affects the leakage current obtained after the combination of the first compensation transistor and the second compensation transistor. A relatively high first initial voltage Vinit1 is supplied in the light emitting phase in order to reduce the source-to-drain voltage of the first reset transistor M1 and the source-to-drain voltage of the first compensation transistor. Thus, the leakage current of the first reset transistor and the leakage current of the first compensation transistor are reduced separately, which reduces the problem of display flickering in the light emitting phase.

In an exemplary implementation, the display further includes M first initial voltage lines, each gating circuit includes a first gating transistor and a second gating transistor, the display drive circuit includes at least one first signal output and at least one second signal output, the first signal terminal outputs the first initial voltage Vinit1, and the second signal terminal outputs the second initial voltage Vinit2. The second electrode of the first gating transistor in the ^N th gating circuit and the second electrode of the second gating transistor in the N ^th gating circuit are connected to the first electrode of the voltage modulation transistor in the pixel circuit of the N ^th row of subpixels and the second electrode of the first reset transistor M1 in the pixel circuit N ^{- th} row of subpixels through the N ^th first line of the initial voltage. The first electrode of the first gate transistor is connected to the first signal terminal, and the first electrode of the second gate transistor is connected to the second signal terminal. The gate of the first gating transistor is configured to receive a light emission control signal, and the gate of the second gating transistor is configured to receive a phase-inverted light emission control signal, where the light emission control signal starts to operate in the light emission phase and ceases to operate out of the light emission phase. This implementation provides a possible implementation of the gating scheme.

In an exemplary implementation, the display further includes M second initial voltage lines, and the pixel circuit further includes a second reset transistor. The first electrode of the second reset transistor is connected to the light emitting component, the second electrode of the second reset transistor in the pixel circuit of the N ^th row of sub pixels is connected to the second signal terminal of the display drive circuit through the N ^th second initial voltage line, and the gate of the second reset transistor is connected to the gate of the first transistor reset. The first start voltage or the second start voltage is output from the left side and the right side, respectively, to the second electrode of the first reset transistor in the same subpixel row. Thus, the problem of signal attenuation can be effectively reduced.

In an exemplary implementation, at least one driver group includes a first driver group and a second driver group, and the first driver group and the second driver group are located to the left and right of the display area, respectively. Both the N ^-th gate circuit in the first driver group and the N ^-th gate circuit in the second driver group are connected to the second electrode of the first reset transistor in the N ^-th subpixel row pixel circuit and the first electrode of the voltage modulation transistor in the N ^-th row pixel circuit. subpixels.

In an exemplary implementation, the display module includes a substrate, a pixel circuit, a display drive circuit, and a driver array are located on the substrate, and the substrate material includes a glass substrate, a flexible material, or an elastic material. The substrate material in the present application is not limited.

In a possible implementation, the values of the first initial voltage Vinit1 may be in the range Vinit1>0V.

In an exemplary implementation, the pixel circuit further includes a data recording transistor, a first electrode of the data recording transistor is configured to receive a data voltage outputted by a data voltage output port of the display drive circuit, a second electrode of the data recording transistor is connected to the first electrode of the drive transistor, a gate of the data recording transistor configured to receive the gate signal N, and the channel width of the data recording transistor is less than or equal to 2 μm. The channel width of the data writing transistor is reduced, and the leakage current of data written in the transistor can be reduced, so that by using a low refresh rate, the possibility of display flickering caused by a relatively large voltage drop of the drive transistor gate voltage in the light emission phase due to leakage current is reduced. .

In an exemplary implementation, the channel width of at least one of the first reset transistor, the first compensation transistor, the second compensation transistor, and the voltage modulation transistor is less than or equal to 2 µm. The leakage currents of transistors can be reduced by reducing the channel width of these transistors, so that by using a low refresh rate, the possibility of display flickering caused by a relatively large voltage drop at the gate of the drive transistor in the light emitting phase due to leakage current is reduced.

According to a second aspect, a display module is provided, including a display and a display drive circuit. The display includes M rows of subpixels arranged in a matrix, the pixel circuit of each subpixel includes a data recording transistor, a compensation transistor, a drive transistor, a first reset transistor, a first capacitor, and a light emitting component, where M≥2, and M is a positive integer number. The first electrode of the data recording transistor is configured to receive the data voltage outputted by the data voltage output port of the display drive circuit, the second electrode of the data recording transistor is connected to the first electrode of the drive transistor, and the gate of the data recording transistor is configured to receive the gate signal N; the first electrode of the compensation transistor is connected to the second electrode of the drive transistor and the light emitting component, the second electrode of the compensation transistor is connected to the gate of the drive transistor, the first terminal of the first capacitor, and the first electrode of the first reset transistor, and the gate of the compensation transistor is configured to receive the gate signal N; the second output of the first capacitor is connected to the first input of the supply voltage; the gate of the first reset transistor is configured to receive the gate signal N- 1; and the second electrode of the first reset transistor is configured to receive the initial voltage Vinit, where 1≤N≤M, and N is a positive integer. The first electrode is a source and the second electrode is a drain, or the first electrode is a drain and the second electrode is a source, the first supply voltage input terminal is configured to input the first supply voltage, and the data voltage output port is configured to output the data voltage. The channel width of at least one of the first reset transistor, the compensation transistor, and the data write transistor is less than 2 µm.

According to the display module provided in embodiments of the present application, the leakage current of the first reset transistor, the leakage current of the compensation transistor, and the leakage current of the data recording transistor can be reduced by reducing the channel width of at least one of the first reset transistor, the compensation transistor, and the transistor data recording, so that when using a low refresh rate, the possibility of display flickering caused by a relatively large voltage drop at the gate of the drive transistor in the light emitting phase is reduced by reducing the leakage current.

According to a third aspect, an electronic device is provided including a display module according to the first aspect or the second aspect. For the technical effect of this implementation, one should refer to the content in the first aspect or the second aspect. The details are not re-described here.

Brief description of the drawings

Fig. 1a is a schematic block diagram of an electronic device according to some embodiments of the present application;

fig. 1b is a schematic block diagram of the display (Fig. 1a);

fig. 1c is a method for connecting a data line and a display drive circuit according to an embodiment of the present application;

fig. 1d is another way of connecting the data line and display drive circuit according to an embodiment of the present application;

fig. 2a is a schematic block diagram of a pixel circuit according to an embodiment of the present application;

fig. 2b, fig. 2c and FIG. 2d is a schematic representation of equivalent circuits for cases where the pixel circuit is in the first phase, respectively. , second phase and third phase ;

fig. 3 is a schematic representation of the control signal timings of the pixel circuit shown in FIG. 2a;

fig. 4 is a comparative chart of image frame duration at 60 Hz and 30 Hz according to some embodiments of the present application;

fig. 5 is a comparative chart of gate voltages and gate-source voltages of a drive transistor at 60 Hz and 30 Hz, according to some embodiments of the present application;

fig. 6 is a schematic representation of the current-voltage characteristic of a transistor according to some embodiments of the present application;

fig. 7a is a schematic representation of the relationship between leakage current and display flicker when displaying a low gray level image according to some embodiments of the present application;

fig. 7b is a schematic representation of the relationship between leakage current and display flicker when displaying an image with a medium or high gray level according to some embodiments of the present application;

fig. 8a is a schematic block diagram of a display module according to an embodiment of the present application;

fig. 8b is a schematic block diagram of another display module according to an embodiment of the present application;

fig. 9a is a schematic block diagram of another display module according to an embodiment of the present application;

fig. 9b is a schematic block diagram of another display module according to an embodiment of the present application;

fig. 10 is a schematic representation of the time sequence of a signal according to an embodiment of the present application;

fig. 11a is a schematic representation of the equivalent circuit of the display module in the first phase shown in FIG. 8a according to an embodiment of the present application;

fig. 11b is a schematic representation of the equivalent circuit of the display module in the second phase shown in FIG. 8a according to an embodiment of the present application;

fig. 11c is a schematic representation of the equivalent circuit of the display module in the third phase shown in FIG. 8a according to an embodiment of the present application; And

fig. 12 is a schematic representation of the relationship between leakage current and channel width according to an embodiment of the present application.

Detailed description of the invention

The following is a description of the technical solutions presented in the embodiments of the present application with reference to the accompanying drawings presented in the embodiments of the present application. It is clear that the described embodiments are only a part and not all of the embodiments of the present application.

As used herein, the terms "first" and "second" are for the purpose of description only and should not be understood as an indication or meaning of relative importance or an implicit indication of the number of said technical features. Thus, a feature limited to the term "first" or "second" may explicitly or implicitly include one or more of these features. In the description of the present application, unless otherwise indicated, "many" means two or more than two.

In addition, in this application, orientation terms such as "top", "bottom", "left" and "right" are defined with respect to the orientation of the components shown in the accompanying drawings. It should be understood that these orientation terms are relative terms and are used for relative description and explanation, and may vary accordingly, in accordance with the change in the position in which the component is located in the accompanying drawings.

All transistors in embodiments of the present application are P-type transistors. The first electrode of the transistor is the source (source, s) and the second electrode of the transistor is the drain (drain, d). When the gate (gate, g) of the transistor receives a low voltage level, the transistor is in the open state, and when the gate g of the transistor receives a high voltage level, the transistor is in the off state. Similarly, for an N-type transistor, the first electrode of the transistor is the drain d and the second electrode is the source s. When the gate (gate, g) of the transistor receives a high voltage level, the transistor is in the open state, and when the gate g of the transistor receives a low voltage level, the transistor is in the off state.

Embodiments of the present application provide an electronic device. The electronic device includes, for example, a television, a mobile phone, a tablet computer, a personal digital assistant (PDA), and an on-board computer. The specific shape of the electronic device is not specifically limited in the embodiments of the present application. For ease of description, the following uses an example in which the electronic device is a mobile phone for description.

As shown in FIG. 1a, the electronic device 01 includes a display module 11 and a housing 12. Additionally, the electronic device 01 may include a middle frame 13.

In a possible implementation, a printed circuit board (PCB) or flexible printed circuit (flexible printed circuit, FPC) may be installed on the housing 12, and the application processor (AP) is located on the PCB or FPC. The display module 11 may be mounted on the housing 12 and connected to a PCB or FPC.

In another possible implementation, the PCB or FPC may be mounted on the middle frame 13 and the display module 11 may be mounted on the middle frame 13 and connected to the PCB or FPC. The housing 12 is mounted on the other side of the middle frame 13. In the present application, this embodiment is used as an example, but is not intended to be limiting.

The display module 11 may include at least one display 10 and a display drive circuit 40 .

Display 10 may include a substrate. In some embodiments of the present application, the substrate material may include a glass substrate or a flexible material. The flexible material may be flexible glass or polyimide (PI). Alternatively, in some other embodiments of the present application, the substrate material may further include an elastic material. The amount of deformation of the elastic material may be greater than or equal to 5%. For example, the elastic material may be polydimethylsiloxane (polydimethylsiloxane, PDMS). In this case, the display 10 may be a flexible display that can be stretched and bent. The flexible display electronic device 01 may be referred to as a portable mobile phone or a portable tablet computer. Alternatively, the substrate material may alternatively include a material with a relatively hard texture such as hard glass or sapphire. In this case, the display 10 is a hard display.

In an exemplary implementation, the display module may have two displays 10, the two displays 10 being respectively located on two sides of the middle frame 13. In other words, one display 10 is integrated into the housing 12 or directly replaces the housing 12. use both the front surface and the back surface of the electronic device.

As shown in FIG. 1b, the display 10 includes an active display area (AA) 100 and a non-display area 101 located around the AA area 100.

The area 100 AA is used to display an image. The AA area 100 includes M rows of sub pixels 20 arranged in a matrix, where M≥2 and M is a positive integer. The pixel circuit 201, which is configured to control the sub-pixel 20 to perform display, is located in the sub-pixel 20. A sub-pixel may also be referred to as a sub-picture or sub-pixel. In this embodiment of the present application, subpixels 20 arranged in a row in the horizontal X direction are referred to as subpixels in the same row, and subpixels 20 arranged in a column in the vertical Y direction are referred to as subpixels in the same column.

The display drive circuit 40 may be set in the non-display area 101 . The display drive circuit 40 is configured to drive the display 10 to display an image. For example, the display driver circuit 40 may be a display driver integrated circuit (DDIC). The display drive circuit 40 includes at least one data voltage output port VO and at least one first signal output O1.

The data voltage output port VO of the display driving circuit 40 is connected to the pixel circuit 201 of at least one column of subpixels 20 via a data line (data line, DL), and the data voltage output port VO is configured to output the data voltage Vdata. The first signal terminal O1 of the display driving circuit 40 is connected to the pixel circuit 201 of each row of subpixels 20. The first signal terminal O1 is configured to output the initial voltage Vinit. For example, the initial Vinit voltage could be -4V.

As shown in FIG. 1c, the data voltage output terminal VO of the display drive circuit 40 can be connected to the data line DL using a multiplexer (MUX). The MUX may select, as required, only some data lines DL in a period of time to separately receive the data voltage Vdata output from the data voltage output terminal VO of the display driving circuit 40 .

When the size of the display 10 is relatively large and the number of lines of subpixels 20 is relatively large, the number of lines of DL data provided on the display 10 also increases. As shown in FIG. 1d, the electronic device 01 may include a plurality of multiplexers and a plurality of display drive circuits 40. The data voltage output terminal VO of one display driving circuit 40 is connected to some data lines DL using an appropriate multiplexer.

The workflow of the pixel circuit 201 includes three phases shown in FIG. 3: first phase , second phase and third phase . First phase may be called the reset phase, the second phase may be referred to as the data voltage write phase, and the third phase may be called the light emission phase.

Since the sub-pixels 20 in the display 10 are scanned and emit light line by line, the pixel circuits 201 are also gated line by line. Each pixel circuit 201 can be controlled using a gate signal N, a gate signal N-1, and a light emission control signal EM, which are shown in FIG. 3. The gate signal N-1 is used to control the pixel circuit 201 in the sub-pixels 20 in the (N-1) ^th row to enter the second phase. and driving the pixel circuit 201 in the subpixels 20 in the N ^th row to enter the first phase , the gate signal N is used to control the pixel circuit 201 in the subpixels 20 in the N ^th row to enter the second phase , and the light emission control signal EM is used to control the pixel circuit 201 in the subpixels 20 in the N ^th row to enter the third phase , where 1≤N≤M, and N is a positive integer.

In FIG. 2a shows the pixel circuit of the 7T1C structure (namely, seven transistors (transistor, T) and one capacitor (capacitance, C)). The pixel circuit 201 includes at least a first reset transistor M1, a data write transistor M2, a compensation transistor M3, a drive transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, a second reset transistor M7, a first capacitor Cst, and a light emitting component. L.

For example, the light emitting component L may be an organic light-emitting diode (OLED), and the display 10 may be an OLED display. Alternatively, the light emitting component L may be a micro light emitting diode (mirco LED), and the display 10 may be a micro LED display. The present application uses an example in which the light emitting component L is an OLED, but the present invention is not intended to be limited to this.

The gate of the first reset transistor M1 is configured to receive the gate signal N-1. The first electrode (e.g., source) of the first reset transistor M1 is connected to the second electrode (e.g., drain d) of the compensation transistor M3, the gate g of the drive transistor M4, and the first terminal of the first capacitor Cst (e.g., the bottom plate of the first capacitor Cst in Fig. 2a) . The second electrode (eg drain d) of the first reset transistor M1 is connected to the second electrode (eg drain d) of the second reset transistor M7 and is configured to receive the initial voltage Vinit.

The first electrode (eg, source s) of the data recording transistor M2 is configured to receive the data voltage Vdata output from the data voltage output port VO of the display driving circuit 40 . The second electrode (eg, drain d) of the data recording transistor M2 is connected to the second electrode (eg, drain d) of the second light-emitting drive transistor M6 and the first electrode (eg, source s) of the drive transistor M4. The gate g of the data recording transistor M2 is configured to receive the gate signal N.

The first electrode (eg, source s) of the compensation transistor M3 is connected to the second electrode (eg, drain d) of the drive transistor M4 and the first electrode (eg, source s) of the first light emitting transistor M5. The gate g of the compensation transistor M3 is configured to receive the gate signal N.

The second electrode (eg drain d) of the second light emitting transistor M5 is connected to the anode (anode a) of the light emitting component L (eg OLED) and the first electrode (eg source s) of the second reset transistor M7. The gate g of the first light emitting driving transistor M5 is configured to receive a light emission control signal EM. The cathode (cathode, c) of the light emitting component L is connected to the second supply voltage input terminal (capable of outputting the second supply voltage ELVSS).

The first electrode (e.g., source s) of the second drive light-emitting transistor M6 is connected to the first supply voltage input terminal and the second terminal of the first capacitor Cst (e.g., the top plate of the first capacitor Cst shown in Fig. 2a) to receive the first supply voltage ELVDD, input from the first input pin of the supply voltage. The gate g of the second light-emitting drive transistor M6 is configured to receive the light emission control signal EM.

The gate g of the second reset transistor M7 is connected to the gate g of the first reset transistor M1 and is configured to receive the gate signal N-1.

Based on the structure of the pixel circuit 201 shown in FIG. 2a, the three phases shown in FIG. 3 in FIG. 2b, fig. 2c and FIG. 2d. For clarity of description, the "×" sign is added to the closed transistor, and the "×" sign is not added to the open transistor.

First phase (reset phase):

As shown in FIG. 2b, when the gate signal N-1 is at a low voltage level, the first reset transistor M1 and the second reset transistor M7 are turned on. The initial voltage Vinit is supplied to the gate g of the drive transistor M4 via the first reset transistor M1 to reset the gate g of the drive transistor M4. In addition, the initial voltage Vinit is transmitted to the anode A of the light emitting component L (for example, OLED) through the second reset transistor M7 to reset the light emitting component L (for example, OLED).

In this case, both the anode voltage Va a of the light emitting component L (for example, OLED) and the gate voltage Vg4 of the drive transistor M4 are equal to the initial voltage Vinit. As shown in Table 1, the drain-to-source voltage Vsd1 of the first reset transistor M1 is equal to the on-state voltage drop, which is about 0.1V, and the drain-to-source voltage of the compensation transistor M3 is Vsd3=Vinit -(ELVSS+Voled) . Vth_M4 is the threshold voltage of the drive transistor M4 and Voled is the voltage drop across the light emitting component L (eg OLED).

In the first phase the gate voltage g of the drive transistor M4 and the anode voltage a on the light emitting component L (for example, OLED) can be reset to the initial voltage Vinit,

so that the previous image frame does not remain energized at the gate g of the drive transistor M4 and energized at the anode a of the light emitting component L (for example, OLED), and prevent the next image frame from being affected. Therefore, the first phase can be called the reset phase. From the above description, it can be seen that the reset phase is the phase in which the first reset transistor M1 conducts.

Second phase (data voltage recording phase):

As shown in FIG. 2c, when the gate signal N is at a low voltage level, the data recording transistor M2 and the compensation transistor M3 are in a conductive state.

When the data recording transistor M2 is in the on state, the first electrode (eg, source s) of the driving transistor M4 is connected to the data voltage output port VO of the display driving circuit 40 . Thus, the data voltage Vdata output from the data voltage output port VO can be received in the write phase of the data voltage. In other words, the source voltage of the drive transistor M4 is Vs4=Vdata. Thus, the data voltage writing phase is a phase in which the data voltage Vdata is applied to the first electrode (for example, the source s) of the drive transistor M4.

When the compensation transistor M3 is turned on, the gate g of the drive transistor M4 is connected to the drain d of the drive transistor M4. In other words, the gate voltage Vg4 of the drive transistor M4 is the same as the drain voltage Vd4 of the drive transistor M4, and the drive transistor M4 is in the on state.

Based on the conductance characteristic of the transistor, it can be known that the drain voltage of the drive transistor M4 is Vd4=Vs4–|Vth_M4|=Vdata–|Vth_M4|, where Vth_M4 is the threshold voltage of the drive transistor M4. Since the compensation transistor M3 is in the on state, the gate voltage Vg4 of the drive transistor M4 is the same as the drain voltage Vd4 of the drive transistor M4. Thus, the voltage at the terminal of the first capacitor Cst is equal to the voltage Vg4 at the gate of the drive transistor M4, where Vg4=Vdata -|Vth_M4|. In other words, the gate voltage Vg4 of the drive transistor M4 is related to the threshold voltage Vth_M4 of the drive transistor M4.

As shown in Table 1, since the first reset transistor M1 is turned off, the drain voltage of the first reset transistor M1 is Vd1=Vinit=-4V, and the source voltage Vs1 of the first reset transistor M1 is the same as the gate voltage Vg4 of the transistor M4 excitation, where Vs1=Vdata–|Vth_M4|, the drain-to-source voltage of the first reset transistor M1 is Vsd1=Vs1–Vd1=Vdata–|Vth_M4|–Vinit=Vdata–|Vth_M4 |–(–4). The drain-source voltage Vsd3 of the compensation transistor M3 is equal to the voltage drop across the transistor in the on state, which is about 0.1 V.

Third phase (light emission phase):

As shown in FIG. 2d, when the light emission control signal EM is at a low voltage level, the first light emission control transistor M5 and the second light emission control transistor M6 are turned on.

The first electrode (eg, source s) of the driving transistor M4 is connected to the first supply voltage input, so that the first supply voltage ELVDD output from the first supply voltage input terminal can be received in the light emission phase. The first electrode (e.g., source s) of the compensation transistor M3 and the second electrode (e.g., drain d) of the drive transistor M4 may be connected to the anode a of the light emitting component L. Thus, the current path between the first supply voltage ELVDD and the second supply voltage ELVSS is open. .

The first capacitor Cst generates a drive current Isd through the drive transistor M4 and transmits the drive current Isd to the light emitting component L (for example, OLED) through the current path to drive the light emitting component L (for example, OLED) to emit light. From the above description, it can be understood that the light emission phase is the phase in which the light emitting component L (for example, OLED) is driven to emit light.

In this case, as shown in Table 1, the source voltage Vs1 of the first reset transistor M1, the drain voltage Vd3 of the compensation transistor M3, and the gate voltage Vg4 of the drive transistor M4 are the same and are all equal to Vdata–|Vth_M4|, that is, Vs1=Vd3= Vg4=Vdata–|Vth_M4|. The drain voltage Vd1 of the first reset transistor M1 is equal to the initial voltage Vinit, and therefore the drain-source voltage of the first reset transistor M1 is Vsd1=Vs1–Vd1=Vdata–|Vth_M4|–Vinit=Vdata–| Vth_M4|–(–4).

The drain voltage of the compensation transistor M3 is Vd3=ELVSS+Voled, and therefore the drain-source voltage of the compensation transistor M3 is Vsd3=Vs3–Vd3=Vdata–|Vth_M4|–(ELVSS+Voled).

[0083] The source-gate voltage of the drive transistor M4 is Vsg4=Vs4-Vg4=ELVDD-(Vdata-|Vth_M4|).

In addition to this, the drive current Isd, which drives the light emitting component L (for example, OLED) to emit light, satisfies the following formula:

Isd=1/2×μ×Cgi×W/L×(Vsg4–|Vth_M4|) ² , … (1)

μ is the carrier mobility rate of the drive transistor M4, Cgi is the capacitance between the gate g of the drive transistor M4 and the channel, W/L is the width to length ratio of the drive transistor M4, and Vth_M4 is the threshold voltage of the drive transistor M4.

It can be seen from formula (1) that the drive current that drives the light emitting component L (for example, OLED) to emit light is Isd=1/2×μ×Cgi×W/L×(ELVDD–Vdata+|Vth_M4|–|Vth_M4 |) ² =1/2×μ×Cgi×W/L×(ELVDD–Vdata) ² .

Since the drive current Isd has nothing to do with the threshold voltage Vth_M4 of the drive transistor M4, the uneven brightness phenomenon caused by the difference between the threshold voltages of the drive transistors can be avoided. Thus, after the threshold voltage compensation in the write phase of the data voltage (second phase in fig. 3) uniform brightness of the display 10 can be realized in the light emission phase (third phase in fig. 3). Since the light emitting component L (such as OLED) emits light in the third phase , third phase may be referred to as the light emission phase.

Based on the structure of the pixel circuit, the sub-pixels 20 in the display 10 are scanned line by line and emit light. Thus, when an image frame is displayed, after the subpixels 20 in the first row emit light, the light emitting state must be maintained until the subpixels 20 in the last row emit light so that the image frame can be displayed.

When the display 10 displays a dynamic image, a refresh rate of 60 Hz may be used. As shown in FIG. 4, the image frame period T2 is 1/60 sec. When the display 10 of the electronic device 01 displays a static image (eg, an idle image), a refresh rate of less than 60 Hz (eg, 30 Hz) may be used to reduce the power consumption of the electronic device 01. In this case, as shown in FIG. 4, the image frame period T1 is 1/30 sec. T1 is greater than T2.

In other words, when the display 10 uses a relatively low refresh rate, the image frame time increases. Thus, for sub-pixels 20 in the same row, when a refresh rate of 30 Hz is used, the period Δt1 during which the row of sub-pixels 20 continues to emit light, namely the duration of the light emission phase (third phase in fig. 3) is about 1/30 s. When the refresh rate is 60Hz, the period Δt2 during which the row of subpixels 20 continues to emit light is about 1/60s. That is, Δt1 is greater than Δt2.

On this basis, when the sub-pixel 20 emits light, the electric value Q of the first capacitor Cst in the pixel circuit 201 of the sub-pixel 20 satisfies the following formula:

Q=C×ΔV=I _{off_M1} ×Δt , … (2)

where C is the capacitance value of the first capacitor Cst, I _{off_M1} is the leakage current of the first reset transistor M1 in the light emission phase (third phase in fig. 3), ΔV is the voltage drop voltage Vg4 at the gate of the excitation transistor M4 in the light emission phase (third phase in fig. 3), and Δt is the period during which the subpixel 20 continues to emit light.

It can be seen from formula (2) that when the capacitance value C of the first capacitor Cst and the leakage current I _{off_M1} of the first reset transistor M1 are fixed, since Δt1 is larger than Δt2, the voltage drop ΔV1 of the gate voltage Vg4 of the drive transistor M4 when the display is 10 performs display at a frequency of 30 Hz, larger than the voltage drop ΔV2 of the gate voltage Vg4 of the drive transistor M4 when the display 10 performs display at a frequency of 60 Hz.

The gate-source voltage Vsg4 of the drive transistor M4 is the difference between the source voltage Vs4 and the gate voltage Vg4, that is, Vsg4=Vs4-Vg4, where from FIG. 2a shows that Vs4=ELVDD, i.e. the gate-source voltage Vs4 is constant. Since ΔV1>ΔV2, as shown in FIG. 5, the gate-source voltage Vsg4_1 of the drive transistor M4 when the display 10 is displaying at 30Hz is larger than the gate-source voltage Vsg4_2 of the drive transistor M4 when the display 10 is performing display at 60Hz, that is, Vsg4_1>VSg4_2.

It can be seen from formula (1) that the drive current Isd, which drives the light emitting component L (for example, OLED) to emit light, is proportional to the square of the gate-source voltage Vsg4 of the drive transistor M4. Since Vsg4_1>Vsg4_2, the drive current Isd1 that drives the light emitting component L (for example, OLED) to emit light when the display 10 performs display at a frequency of 30 Hz is larger than the drive current Isd2 that drives the light emitting component L (for example, OLED ) to emit light when the display 10 performs display at a frequency of 60 Hz, that is, Isd1>Isd2. In other words, when the refresh rate of the display 10 is changed from a relatively high refresh rate of 60 Hz to a relatively low refresh rate of 30 Hz for display, the drive current flowing through the light emitting component L (for example, OLED) in the sub-pixel 20 increases. In this case, when the frequency is changed update, the brightness of the light emitting component L (such as OLED) changes abruptly, and the human eye sharply picks up the sudden change in brightness. Accordingly, the display flickers.

Based on the above reason why the display 10 flickers when the display 10 is displaying at a low refresh rate of 30 Hz, in a possible implementation, the flickering of the low refresh rate display can be reduced by reducing the leakage current I _{off_M1} of the first reset transistor M1.

Specifically, when the display 10 performs display at a low refresh rate of 30 Hz, the voltage drop ΔV1 of the gate voltage Vg4 of the drive transistor M4 in the light emission phase (third phase shown in FIG. 3) can be reduced so that the voltage drop ΔV1 is approximately equal to the value of the voltage drop ΔV2 of the gate voltage Vg4 of the drive transistor M4 when the display 10 is displaying at 60 Hz. As shown in FIG. 5, when the display 10 performs display at a frequency of 30 Hz, the gate-source voltage Vsg4_1 of the drive transistor M4 decreases, so that the gate-source voltage Vsg4_1 is approximately equal to the gate-source voltage Vsg4_2 of the drive transistor M4 when the display 10 performs display at a frequency of 60 Hz. Thus, it can be seen from formula (1) that the drive current Isd1 that drives the light emitting component L (for example, OLED) to emit light when the display 10 performs display at a frequency of 30 Hz is approximately equal to the drive current Isd2 that drives the light emitting component L (eg OLED) to emit light when the display 10 is displaying at 60 Hz.

In FIG. 6 shows the current-voltage characteristic of the transistor. Each curve represents the case where the leakage current I _off of the transistor depends on the gate-source voltage Vsg when the source-drain voltage Vsd of the transistor has a certain value. For example, in FIG. 6, the Vsd_1 curve is above the Vsd_2 curve. Thus, Vsd_1>Vsd_2. When the gate-source voltages Vsg are the same, the leakage current I _off1 corresponding to the Vsd_1 curve is larger than the leakage current I _off2 corresponding to the Vsd_2 curve. In other words, a larger transistor source-drain voltage Vsd indicates a larger leakage current I _off , and a smaller transistor source-drain voltage Vsd indicates a smaller leakage current I _off .

Thus, in order to reduce the leakage current I _{off_M1} of the first reset transistor M1 in the light emitting phase, it is necessary to decrease the source-drain voltage Vsd1 of the first reset transistor M1.

In addition to this, as shown in FIG. 2d, the transistors which are connected to the drive transistor M4 and which are in the off state in the third phase 3 include the first reset transistor M1, the compensation transistor M3, and the data write transistor M2. Thus, the leakage current of the first reset transistor M1, the leakage current of the compensation transistor M3, and the leakage current of the data writing transistor M2 all together cause the gate voltage Vg4 of the drive transistor M4 to generate a voltage drop ΔV in the time period during which the subpixels 20 continue emit light. However, when the sub-pixels 20 display images with different gray scales, the degree of display flicker caused by the leakage current of the first reset transistor M1 is different from the degree of display flicker caused by the leakage current of the compensation transistor M3 or the leakage current of the data recording transistor M2.

As shown by A in FIG. 7a, when the sub-pixels 20 display a low gray scale image, the flickering of the display is mainly caused by the leakage current of the first reset transistor M1. As shown by B in FIG. 7a, in the case where the first supply voltage ELVDD is constant, the source-drain voltage Vsd of the first reset transistor M1 is reduced by increasing the initial voltage Vinit to reduce the leakage current of the first reset transistor M1. Thus, display flicker can be reduced when an image with a low gray scale is displayed.

As shown by A in FIG. 7b, when the sub-pixels 20 display an image with a medium or high gray level, the flickering of the display is mainly caused by the leakage current of the compensation transistor M3 and the leakage current of the data recording transistor M2. As shown by B in FIG. 7b, the high voltage level Vg_h, which corresponds to the gate signal N and which is received by the gate g of the compensation transistor M3, decreases (see FIG. 3), and the gate-source voltage Vsg shown in FIG. 6 increases (because Vsg=Vs-Vg, Vsg increases as Vg decreases), which is equivalent to increasing the source-drain voltage Vsd of the compensation transistor M3, thereby reducing the leakage current of the compensation transistor M3. Therefore, display flicker can be reduced when an image with a medium or high gray level is displayed.

Finally, the leakage current of the first reset transistor M1, the leakage current of the compensation transistor M3, and the leakage current of the data recording transistor M2 are reduced, so that when using a low refresh rate, the possibility of display flickering caused by the relatively large voltage drop Vg4 across the drive gate transistor M4 in the emission phase is reduced. light due to leakage current. For the first reset transistor M1 and the compensation transistor M3, the leakage current of the first reset transistor M1 and the leakage current of the compensation transistor M3 can be reduced by reducing the source-drain voltage and/or channel width of the first reset transistor M1 and the source-drain voltage and/or channel width compensation transistor M3. For the data recording transistor M2, the leakage current of the data recording transistor M2 can be reduced by reducing the channel width.

As shown in FIG. 8a, an embodiment of the present application provides for another display module. Compared to the display module shown in FIG. 1b, the display module shown in FIG. 8a further includes M first initial voltage lines S1, M second initial voltage lines S2, and at least one driver group 30 disposed in the non-display area 101. It should be noted that the display module may also have the MUX and display shown in FIG. 1c or fig. 1d, and details are not described here again.

The pixel circuit 201, the display drive circuit 40, and the driver group 30 may be disposed on the substrate described above.

Each driver group 30 includes M gate circuits 301. The display drive circuit 40 includes at least one data voltage output port VO, at least one first signal output O1, and at least one second signal output O2.

The data voltage output port VO of the display driving circuit 40 is connected to the pixel circuit 201 of at least one column of subpixels 20 via a data line (data line, DL), and the data voltage output port VO is configured to output the data voltage Vdata. The first signal output O1 and the second signal output O2 of the display driving circuit 40 are individually connected to the gate circuits 301 in each driver group 30 . The second signal terminal O2 of the display drive circuit 40 is further connected to the pixel circuit 201 of each subpixel 20 via the second start voltage line S2. The gate circuit 301 in each driver group 30 is connected to the pixel circuit 201 of the row of subpixels 20 via the first start voltage line S1.

The first signal terminal O1 may output the first initial voltage Vinit1, and the second signal terminal O2 may output the second initial voltage Vinit2. In the phase of light emission (third phase shown in FIG. 3) the absolute value of the second initial stress is greater than the absolute value of the first initial stress, i.e. |Vinit2|>|Vinit1|. The values of the first initial voltage Vinit1 can be in the range Vinit1>0V. For example, the first initial voltage of Vinit1 may be 0V, 1V, or 2V. The second initial voltage of Vinit2 may be -4V.

N^{-and I}the gate circuit 301 is connected to the second electrode (eg drain) of the first reset transistor M1 in the pixel circuit 201 in N^-Ouchrow of subpixels 20 and to the first electrode (eg, source) of the voltage modulation transistor Mc in the pixel circuit 201 in N^-Ouchrow of subpixels 20. N^{-and I}the gate circuit 301 is further connected to the first signal terminal O1 and the second signal terminal O2 of the display driving circuit 40, and is configured to select one of the first initial voltage Vinit1 and the second initial voltage Vinit2, which are output by the display driving circuit 40 as the third initial voltage Vinit3, and outputting the third initial voltage Vinit3 to the second electrode (eg drain) of the first reset transistor M1 in the pixel circuit 201 N^-Ouchrows of subpixels 20 and the first electrode (eg source) of the voltage modulation transistor Mc in the pixel circuit 201 N^-Ouch lines subpixels 20 through the first initial voltage line S1.

The display drive circuit 40 may be connected to the AP using the FPC shown in FIG. 1a, so that the display drive circuit 40 can receive the display data output by the AP, and the data voltage output port VO supplies the data voltage Vdata to the pixel circuit 201 of each subpixel 20 via the DL.

The following is a detailed description of the structure and function of the pixel circuit 201 and the gating circuit 301 using one pixel circuit 201 and one gating circuit 301 in the N ^th row as an example.

In particular, compared with the pixel circuit 201 shown in FIG. 2a, the pixel circuit shown in FIG. 8b further includes a first compensation transistor Ma, a second compensation transistor Mb, and a voltage modulation transistor Mc.

The difference between the pixel circuit 201 shown in FIG. 8b and the pixel circuit 201 shown in FIG. 2a looks like this: in the light emission phase (third phase in fig. 3) the second reset transistor M7 separately receives the second initial voltage Vinit2, the first compensation transistor Ma and the second compensation transistor Mb are combined to replace the compensation transistor M3, and the connection point between the first compensation transistor Ma and the second compensation transistor Mb receives the first initial voltage Vinit1 through the transistor Mc voltage modulation and the second electrode (eg drain) of the first reset transistor M1. Since the source-drain of the first compensation transistor Ma and the source-drain of the second compensation transistor Mb are connected in series, the leakage current of the first compensation transistor Ma directly affects the leakage current obtained after the combination of the first compensation transistor Ma and the second compensation transistor Mb. A relatively high first initial voltage Vinit1 (e.g. 1 V) is connected in the light emission phase (third phase in fig. 3) to reduce the source-drain voltage Vsd of the first reset transistor M1 and the source-drain voltage Vsd of the first compensation transistor Ma. Thus, the leakage current of the first reset transistor M1 and the leakage current of the first compensation transistor Ma (equivalent to the reduction of the compensation transistor M3 described above) are reduced separately to reduce the display flickering problem in the light emission phase.

Specifically, the first electrode (eg, source s) of the first compensation transistor Ma is connected to the second electrode (eg, drain d) of the second compensation transistor Mb and the second electrode (eg, drain d) of the voltage modulation transistor Mc. The second electrode (e.g., drain d) of the first compensation transistor Ma is connected to the gate g of the drive transistor M4, the first terminal of the first capacitor Cst (e.g., the bottom plate of the first capacitor Cst in Fig. 2a), and the first electrode (e.g., the source s) of the first transistor M1 reset.

The first electrode (for example, the source s) of the second compensation transistor Mb is connected to the second electrode (for example, the drain d) of the drive transistor M4 and the anode of the light emitting component L. The gate g of the first compensation transistor Ma and the gate s of the second compensation transistor Mb are configured to receive a strobe signal N.

The first electrode (e.g., source s) of the voltage modulation transistor Mc is connected to the second electrode (e.g., drain d) of the first reset transistor M1 and to the gating circuit 301 via the first start voltage line S1, and is configured to receive the first start voltage Vinit1 or the second start voltage Vinit2, which is selected and output by the gate circuit 301 . The gate g of the voltage modulation transistor Mc is configured to receive the light emission control signal EM.

The second electrode (for example, drain d) of the second reset transistor M7 is connected to the second signal terminal O2 of the display driving circuit 40 via the N ^th second initial voltage line S2, and is configured to receive the second initial voltage Vinit2.

Note that the function of combining the first compensation transistor Ma and the second compensation transistor Mb is the same as that of the compensation transistor M3 in FIG. 2a. For connection relationships between components that are not described in the pixel circuit 201, refer to the respective descriptions in FIG. 2b. The details are not re-described here.

Each gate circuit 301 includes a first gate transistor Ms1 and a second gate transistor Ms2.

The first electrode (for example, the source s) of the first gating transistor Ms1 is connected to the first signal terminal O1 of the display driving circuit 40 and is configured to receive the first initial voltage Vinit1 outputted by the first signal terminal O1 of the display driving circuit 40. The gate g of the first gate transistor Ms1 is configured to receive the light emission control signal EM. The light emission control signal becomes active in the light emission phase and ceases to operate in the non-light emission phase.

The first electrode (eg, source s) of the second gate transistor Ms2 is connected to the display driving circuit 40 . Specifically, the first electrode (e.g., source s) of the second gating transistor Ms2 is connected to the second signal terminal O2 of the display drive circuit 40, and is configured to receive the second initial voltage Vinit2 outputted by the second signal terminal O2 of the display drive circuit 40. The gate g of the second gating transistor Ms2 is configured to receive a phase inverted signal XEM of the light emission control signal EM. The phase inverted signal XEM of the light emission control signal EM can be obtained by inverting the phase of the light emission control signal EM using a phase inverter (not shown in the figure).

The second electrode (for example, drain d) of the first gate transistor Ms1 and the second electrode (for example, drain d) of the second gate transistor Ms2 in the N ^th gate circuit 301 are connected to the first electrode (for example, source s) of the voltage modulation transistor Ms in the pixel circuit 201 The N ^th row of sub pixels 20 and the second electrode (eg drain d) of the first reset transistor M1 in the pixel circuit 201 of the N ^th row of sub pixels 20 via the N ^th first start voltage line S1.

The gate circuit 301 is configured to: in the reset phase (first phase in fig. 3) and data voltage recording phase (second phase in fig. 3) outputting the second initial voltage Vinit2 to the second electrode (for example, drain) of the first reset transistor M1 and the first electrode (for example, source) of the voltage modulation transistor Mc through the first initial voltage line S1, and is further configured to: in the light-emitting phase (third phase in fig. 3), outputting the first initial voltage Vinit1 to the second electrode (eg drain) of the first reset transistor M1 and the first electrode (eg source) of the voltage modulation transistor Mc through the first initial voltage line S1.

Based on this, at least one driver group includes the first driver group 30A and the second driver group 30B shown in FIG. 9a. The first driver group 30A and the second driver group 30B are respectively located to the left and right of the display display area 100 .

Based on this, as shown in Fig. 9b, the N ^th gate circuit in the first driver group 30A and the N ^th gate circuit in the second driver group 30B are connected to the second electrode (for example, drain d) of the first reset transistor M1 in the pixel circuit 201 of the N ^th row of subpixels 20 and the first electrode. (for example, the source) of the voltage modulation transistor Mc in the pixel circuit 201 of the N ^th row of subpixels 20.

When the resolution of the display 10 is relatively high, there are a relatively large number of subpixels 20 in one row. output pin of the gate circuit in the exciter group. Thus, the accuracy of the signal is reduced.

Thus, the first driver group 30A and the second driver group 30B are respectively located on the left side and right side of the display area 100, so that one gating circuit in the first driver group 30A and one gating circuit in the second driver group 30V output the first initial voltage. Vinit1 or the second initial voltage Vinit2 from the left side and the right side to the second electrode (for example, drain d) of the first reset transistor M1 in the same row of subpixels 20. Thus, signal attenuation problem can be effectively reduced.

Various examples are given below to describe the structures of the gating circuit in the driver group 30 and the display 10 having the gating circuit.

In the following, as an example, Fig. 9b to describe the mode of operation of the above circuit.

Regardless of the reset phase (first phase in fig. 3), data voltage recording phase (second phase in fig. 3) and light emission phase (third phase in fig. 3), the second initial voltage of Vinit2 is always at a low voltage level (for example, -4V). That is, the voltage of the second electrode (eg, drain d) of the second reset transistor M7 is Vd7=Vinit2.

Reset phase (first phase in fig. 3):

As shown in FIG. 10, the gate circuit 301 selects the second initial voltage Vinit2 to output, that is, the third initial voltage Vinit3 is equal to the second initial voltage Vinit2, the gate signal N-1 switches from a high voltage level to a low voltage level, the gate signal N remains at a high voltage level, the signal The light emission control EM is at a high voltage level, and the phase-inverted signal XEM of the light emission control signal EM is at a low voltage level.

As shown in FIG. 11a, since the gate signal N-1 switches from a high voltage level to a low voltage level, the first reset transistor M1 and the second reset transistor M7 are turned on. The strobe signal N remains at a high voltage level, so that the first compensation transistor Ma, the second compensation transistor Mb, and the data recording transistor M2 are turned off. The light emission control signal EM is at a high voltage level, and the phase-inverted signal XEM of the light emission control signal EM is at a low voltage level, so that the second light emission control transistor M6, the voltage modulation transistor Mc, and the first gate transistor Ms1 in the gate circuit 301 turn off, and the second gate transistor Ms2 remains open. Thus, the gate circuit 301 transmits, via the first start voltage line S1, the second start voltage Vinit2 outputted from the second signal terminal O2 of the display driving circuit 40 to the second electrode (for example, drain d) of the first reset transistor M1 and the first electrode (for example, source) transistor MS voltage modulation.

Similar to the description shown in FIG. 2b, the third initial voltage Vinit3 (which at this time is equal to the second initial voltage Vinit2) is supplied to the gate g of the drive transistor M4 through the first reset transistor M1 to reset the gate g of the drive transistor M4. The second initial voltage Vinit2 is transmitted to the anode a of the light emitting component L (for example, OLED) through the second reset transistor M7 to reset the anode a of the light emitting component L (for example, OLED). In the reset phase (first phase in fig. 3) The gate voltage g of the drive transistor M4 and the voltage at the anode a of the light emitting component L (for example, OLED) can be reset to the initial voltage Vinit1 so that the previous image frame does not remain energized at the gate g of the drive transistor M4 and energized at the anode a at light emitting component L (such as OLED) and prevent the image from affecting the next frame.

As shown in Table 1, the drain-to-source voltage Vsd1 of the first reset transistor M1 is equal to the on-state voltage drop of the transistor, which is about 0.1V. the source of the compensation transistor M3 shown in FIG. 2b, except that Vinit in FIG. 2b changes to Vinit3 in FIG. 8b. That is, Vsd_a=Vinit3–(ELVSS+Voled).

Table 1

Block V The pixel circuit shown in FIG. 2a The pixel circuit shown in FIG. 8b Vinit Vsd1 Vsd3 Vinit3 Vsd1 Vsd_a First phase -4 About 0.1 Vinit-(ELVSS+Voled) –4(Vinit2) 0.1 Vinit3|–(ELVSS+Voled) Second phase -4 Vdata–|Vth_M4|–Vinit About 0.1 –4(Vinit2) Vdata–|Vth_M4|–Vinit3 About 0.1 Third phase -4 Vdata–|Vth_M4|–(ELVSS+Voled) 1(Vinit1) Vdata–|Vth_M4|–Vinit3 Vdata–|Vth_M4|–Vinit3

Data voltage recording phase (second phase in fig. 3):

As shown in FIG. 10, the gate circuit 301 selects the second initial voltage Vinit2 to output, that is, the third initial voltage Vinit3 is equal to the second initial voltage Vinit2, the gate signal N-1 switches from a low voltage level to a high voltage level, the gate signal N switches from a high voltage level to a low voltage level. voltage level, and the light emission control signal EM is at a high voltage level, the phase-inverted signal XEM of the light emission control signal EM is at a low voltage level.

As shown in FIG. 11b, since the gate signal N-1 switches from a low voltage level to a high voltage level, the first reset transistor M1 and the second reset transistor M7 are turned off. The strobe signal N is switched from a high voltage level to a low voltage level, so that the first compensation transistor Ma, the second compensation transistor Mb, and the data recording transistor M2 are turned on. The light emission control signal EM is at a high voltage level, and the phase-inverted signal XEM of the light emission control signal EM is at a low voltage level, so that the second light emission control transistor M6, the voltage modulation transistor Mc, and the first gate transistor Ms1 in the gate circuit 201 turn off, and the second gate transistor MS2 opens. Thus, the gate circuit 201 transmits, through the first start voltage line S1, the second start voltage Vinit2 outputted from the second signal terminal O2 of the display driving circuit 40 to the second electrode (for example, drain d) of the first reset transistor M1 and the first electrode (for example, source) transistor MS voltage modulation.

In this case, when the first compensation transistor Ma and the second compensation transistor Mb are turned on, the gate g of the drive transistor M4 is connected to the drain d of the drive transistor M4. In other words, the gate voltage Vg4 of the drive transistor M4 is the same as the drain voltage Vd4, and the drive transistor M4 is in the on state. In this case, the data voltage Vdata is written to the source s of the drive transistor M4 via the open data writing transistor M2.

As shown in the respective descriptions with reference to FIG. 2c, the gate voltage of the drive transistor M4 is Vg4=Vdata–|Vth_M4|. As shown in Table 1, the first reset transistor M1 is closed, and the drain voltage of the first reset transistor M1 is Vd1=Vinit1=-4V. The source voltage Vs1 of the first reset transistor M1 is the same as the gate voltage Vg4 of the drive transistor M4, that is, Vs1=Vdata–|Vth_M4|. Thus, the drain-source voltage of the first reset transistor M1 is Vsd1=Vs1-Vd1=Vdata-|Vth_M4|-Vinit3=Vdata-|Vth_M4|-(-4). The drain-source voltage Vsd_a of the first compensation transistor Ma is equal to the voltage drop across the transistor in the on state, which is about 0.1 V.

Light emission phase (third phase in fig. 3):

As shown in FIG. 10, the gate circuit 301 selects the output of the first start voltage Vinit1, that is, the third start voltage Vinit3 is equal to the first start voltage Vinit1, the gate signal N-1 and the gate signal N remain at a high voltage level, the light emission control signal EM is at a low voltage level, and the phase inverted signal XEM of the light emission control signal EM is at a high voltage level.

As shown in FIG. 11c, since the gate signal N is at a high voltage level, the first reset transistor M1 and the second reset transistor M7 are turned off. The gate signal N is at a high voltage level, so that the first compensation transistor Ma, the second compensation transistor Mb, and the data recording transistor M2 are turned off. The light emission control signal EM is at a low voltage level, and the phase-inverted signal XEM of the light emission control signal EM is at a high voltage level, so that the second light emission control transistor M6, the voltage modulation transistor Mc, and the first gate transistor Ms1 in the gate circuit 201 are turned on, and the second gate transistor Ms2 is closed. The gate circuit 201 transmits, through the first start voltage line S1, the first start voltage Vinit1 outputted from the first signal terminal O1 of the display driving circuit 40 to the second electrode (for example, drain d) of the first reset transistor M1 and the first electrode (for example, source) of the transistor Mc voltage modulation.

As shown in the respective descriptions with reference to FIG. 2d, since the first light emission control transistor M5 and the second light emission control transistor M6 are turned on, a current path between the first supply voltage ELVDD and the second supply voltage ELVSS is opened. The first capacitor Cst generates a drive current Isd through the drive transistor M4 and supplies the drive current Isd to the light emitting component L (for example, OLED) along the current flow path so as to drive the light emitting component L (for example, OLED) to emit light.

In this case, since the voltage modulation transistor Mc is open, it is equivalent that the first electrode (eg, source) of the first compensation transistor Ma is connected to the second electrode (eg, drain) of the first reset transistor. Thus, both the source voltage Vs_a of the first compensation transistor Ma and the drain voltage Vd1 of the first reset transistor are equal to the first initial voltage Vinit1. The second electrode (eg, drain d) of the first compensation transistor Ma is connected to the first electrode (eg, source) of the first reset transistor. Thus, the drain voltage Vd_a of the first compensation transistor Ma is equal to the source voltage Vs1 of the first reset transistor. Thus, the source-drain voltage Vsd_a of the first compensation transistor Ma is equal to the source-drain voltage Vsd1 of the first reset transistor M1, that is, Vsd_a=Vsd1.

As shown in the respective descriptions of FIG. 2d, the gate voltage of the drive transistor M4 is Vg4=Vdata–|Vth_M4|. Thus, as shown in Table 1, the source-drain voltage of the first compensation transistor Ma is Vsd_a=Vsd1=Vs1-Vd1=Vdata-|Vth_M4|-Vinit3.

In the phase of light emission (third phase in fig. 3) The source-drain voltage Vsd1 of the first reset transistor M1 changes from Vdata-|Vth_M4|-Vinit (the pixel circuit shown in Fig. 2a) to Vdata-|Vth_M4|-Vinit3 (the pixel circuit shown in Fig. 8b). The value of Vinit3 (which is currently equal to Vinit1) can be adjusted so that Vinit3 (which is currently equal to Vinit1) is greater than Vinit (which is currently equal to Vinit2). Thus, the source-drain voltage Vsd1 of the first reset transistor M1 is reduced, and the leakage current of the first reset transistor M1 is further reduced. Thus, when a low refresh rate is used, the possibility of display flickering caused by a relatively large drop in the gate voltage Vg4 of the drive transistor M4 in the light emission phase due to the leakage current is reduced.

In the phase of light emission (third phase in fig. 3) The source-drain voltage Vsd_a of the first compensation transistor Ma changes from Vdata–|Vth_M4|–(ELVSS+Voled) (the pixel circuit shown in Fig. 2a) to Vdata–|Vth_M4|–Vinit3 (the pixel circuit shown in Fig. 8b). The value of Vinit1 (Vinit3) can be adjusted so that Vinit1>(ELVSS+Voled). Thus, the source-drain voltage Vsd_a of the first compensation transistor Ma is reduced, and the leakage current obtained after combining the first compensation transistor Ma and the second compensation transistor Mb is further reduced (which is equivalent to the original compensation transistor M3). Thus, when a low refresh rate is used, the possibility of display flickering caused by a relatively large drop in the gate voltage Vg4 of the drive transistor M4 in the light emission phase due to the leakage current is reduced.

Finally, when the first start voltage Vinit1 is greater than the second start voltage Vinit2, it is possible to reduce the leakage current of the first reset transistor M1. When the first initial voltage Vinit1 is greater than the sum of the second supply voltage ELVSS and the voltage drop Voled of the light emitting component L (for example, OLED), the compensation transistor leakage current can be reduced. That is, the first initial voltage Vinit1 satisfies at least one of the following conditions: Vinit1>Vinit2 and Vinit1>(ELVSS+Voled).

For example, when Vth_M4=-1.5V, Vdata=2-6V, ELVSS=-3V, and Voled=2-4.5V, the specific values from Table 1 are shown in Table 2.

Table 2 shows that in the phase of light emission (the third phase in fig. 3) compared to the pixel circuit shown in FIG. 2a in the pixel circuit shown in FIG. 8b, when an image with a low gray scale (for example, gray scale 0) is displayed, the source-drain voltage Vsd1 of the first reset transistor M1 can be reduced by 8.5 to 3.5=4 V. When an image with a medium gray scale is displayed (for example, , grayscale 127), the source-drain voltage Vsd_a of the first compensation transistor Ma can be reduced by 3.5-2.5=1V. of the first compensation transistor Ma can be reduced by |–1|–|–0.5|=0.5 V.

table 2

Block V The pixel circuit shown in FIG. 2a The pixel circuit shown in FIG. 8b Vinit Vsd1 Vsd3 Vinit3 Vsd1 Vsd_a First phase -4 About 0.1 -5.5 (greyscale 255)
-3 (greyscale 0) -4 0.1 -5.5 (greyscale 255)
-3 (greyscale 0) Second phase -4 4.5 (greyscale 255)
8.5 (greyscale 0) About 0.1 -4 4.5 (greyscale 255)
8.5 (greyscale 0) About 0.1 Third phase -4 -1 (greyscale 255)
3.5 (greyscale 127) 1 0.5 (greyscale 255)
3.5 (greyscale 0) -0.5 (greyscale 255)
2.5 (greyscale 127)

As described above, the values of the first initial voltage Vinit1 may be in the range Vinit1>0V. When the first initial voltage Vinit1 is less than 0 V, in the light emission phase (third phasein fig. 3) the change difference between the source-drain voltage Vsd1 of the first reset transistor M1 is relatively small. Thus, in the light emission phase, the current I_{off_M1}leaks the first reset transistor M1 cannot be effectively reduced, and it is impossible to eliminate the flickering of the display. In addition, when the first initial voltage Vinit1 is greater than 2V, the leakage current of the second reset transistor M7 flows into the light emitting component L (for example, OLED), so that the light emitting component L (for example, OLED) emits light when the subpixels 20 display a black image. . In other words, the phenomenon of light leakage occurs.

In the method described above, the reason for reducing the leakage current of the transistor by reducing the width of the transistor channel is as follows:

As shown in FIG. 12, the leakage current of a thin film transistor (TFT) increases with increasing channel width and decreases with decreasing channel width. Thus, the leakage currents of the first reset transistor M1, the first compensation transistor Ma, and the second compensation transistor Mb can be reduced by reducing the channel width of the first reset transistor M1, the first compensation transistor Ma, and the second compensation transistor Mb, so that when a low refresh rate is used , the possibility of display flickering caused by a relatively large drop in the gate voltage Vg4 of the drive transistor M4 in the light emission phase due to the leakage current is reduced.

For example, a transistor channel width at a refresh rate of 60 Hz is typically 2 µm, and a transistor channel length is 2.5 µm. In a scenario in which a low refresh rate is used, for the pixel circuit shown in FIG. 2a, the channel width of at least one of the first reset transistor M1, the compensation transistor M3, and the data write transistor M2 is less than 2 µm. For the pixel circuit shown in FIG. 8b, the channel width of at least one of the first reset transistor M1, the first compensation transistor Ma, the second compensation transistor Mb, the voltage modulation transistor Mc, and the data recording transistor M2 is less than or equal to 2 µm.

The above descriptions are merely specific implementations of the present application, but are not intended to limit the scope of protection of the present application. Any change or substitution within the technical scope disclosed in this application must be within the protection scope of this application. Thus, the scope of protection of the present application should be consistent with the scope of protection of the claims.

Claims (24)

1. A display module comprising a display, a display drive circuit, and at least one group of drivers, where the display contains M rows of subpixels arranged in a matrix, and the pixel circuit of each subpixel contains a first compensation transistor, a second compensation transistor, a voltage modulation transistor, a drive transistor, a first reset transistor, a first capacitor, and a light emitting component, where M≥2 and M is positive integer; the first electrode of the first compensation transistor is connected to the second electrode of the second compensation transistor and the second electrode of the voltage modulation transistor, the second electrode of the first compensation transistor is connected to the gate of the drive transistor, and the first terminal of the first capacitor is connected to the first electrode of the first reset transistor; the first electrode of the second compensation transistor is connected to the second electrode of the drive transistor and the anode of the light emitting component, and the gate of the first compensation transistor and the gate of the second compensation transistor are configured to receive the gate signal N; the first electrode of the voltage modulation transistor is connected to the second electrode of the first reset transistor, and the gate of the voltage modulation transistor is configured to receive a light emission control signal; the second output of the first capacitor is connected to the first input of the supply voltage; the first electrode of the drive transistor is connected to the first supply voltage input or data voltage output port of the display drive circuit; the gate of the first reset transistor is configured to receive the gate signal N-1; and the cathode of the light emitting component is connected to the second supply voltage input terminal, where 1≤N≤M and N is a positive integer; the first electrode is a source and the second electrode is a drain, or the first electrode is a drain and the second electrode is a source, the first supply voltage input terminal is configured to input the first supply voltage, and the data voltage output port is configured to output the data voltage; each group of exciters contains M gating circuits; The Nth gate circuit is connected to the second electrode of the first reset transistor in the Nth subpixel row pixel circuit and to the first electrode of the voltage modulation transistor in the Nth subpixel row pixel circuit; The Nth gating circuit is additionally connected to the display drive circuit and configured to: receive the first initial voltage Vinit1 and the second initial voltage Vinit2 from the display drive circuit, output the second initial voltage Vinit2 to the second electrode of the first reset transistor and the first electrode of the voltage modulation transistor, when the pixel circuit is in a reset phase and a data voltage write phase, and outputting the first initial voltage Vinit1 to the second electrode of the first reset transistor and the first voltage electrode of the modulation transistor when the pixel circuit is in the light emitting phase; and the first initial voltage Vinit1 satisfies at least one of the following conditions: Vinit1>Vinit2 and Vinit1>(ELVSS+Voled), where ELVSS is the voltage output to the second supply voltage input pin and Voled is the voltage drop across the light emitting component; And the reset phase is the phase in which the first reset transistor is turned on, the data voltage write phase is the phase in which the data voltage is applied to the first electrode of the drive transistor, and the light emission phase is the phase in which the light emitting component emits light. 2. The display module of claim 1, wherein the display further comprises M first initial voltage lines, each gate circuit comprises a first gate transistor and a second gate transistor, the display drive circuit comprises at least one first signal output and at least one second signal output. output, the first signal terminal outputs the first initial voltage Vinit1, and the second signal terminal outputs the second initial voltage Vinit2; the second electrode of the first gating transistor in the Nth gating circuit and the second electrode of the second gating transistor in the Nth gating circuit are connected to the first electrode of the voltage modulation transistor in the Nth subpixel row pixel circuit and the second electrode of the first reset transistor M1 in the N-pixel circuit. th row of subpixels through the N-th first line of the initial voltage; the first electrode of the first gate transistor is connected to the first signal terminal, and the first electrode of the second gate transistor is connected to the second signal terminal; And the gate of the first gating transistor is configured to receive a light emission control signal, and the gate of the second gating transistor is configured to receive a phase-inverted light emission control signal, wherein the light emission control signal starts to operate in the light emission phase and ceases to operate out of the light emission phase. 3. The display module of claim 2, wherein the display further comprises M second initial voltage lines, and the pixel circuit further comprises a second reset transistor; And the first electrode of the second reset transistor is connected to the light emitting component, the second electrode of the second reset transistor in the Nth subpixel row pixel circuit is connected to the second signal terminal of the display drive circuit through the Nth second initial voltage line, and the gate of the second reset transistor is connected to the gate of the first transistor reset. 4. The display module according to any one of paragraphs. 1-3, wherein at least one driver group comprises a first driver group and a second driver group, and the first driver group and the second driver group, respectively, are located to the left and right of the display area of the display; And both the Nth gate circuit in the first driver group and the Nth gate circuit in the second driver group are connected to the second electrode of the first reset transistor in the Nth subpixel row pixel circuit and the first electrode of the voltage modulation transistor in the Nth row pixel circuit subpixels. 5. The display module according to any one of paragraphs. 1-4, wherein the display module comprises a substrate, a pixel circuit, a display drive circuit, and a driver group are disposed on the substrate, and the substrate material comprises a glass substrate, a flexible material, or an elastic material. 6. The display module according to any one of paragraphs. 1-5, in which the values of the first initial voltage Vinit1 can be in the range Vinit1>0 V. 7. The display module according to any one of paragraphs. 1-6, in which the pixel circuit further comprises a data recording transistor, the first electrode of the data recording transistor is configured to receive the data voltage outputted by the data voltage output port of the display drive circuit, the second electrode of the data recording transistor is connected to the first electrode of the drive transistor, the gate of the recording transistor The data recording transistor is configured to receive the gate signal N, and the channel width of the data recording transistor is less than or equal to 2 µm. 8. Display module according to any one of paragraphs. 1-7, wherein the channel width of at least one of the first reset transistor, the first compensation transistor, the second compensation transistor, and the voltage modulation transistor is less than or equal to 2 mm. 9. A display module comprising a display and a display drive circuit in which the display contains M rows of subpixels arranged in a matrix, the pixel circuit of each subpixel contains a data recording transistor, a compensation transistor, a drive transistor, a first reset transistor, a first capacitor, and a light emitting component, where M≥2 and M is a positive integer; the first electrode of the data recording transistor is configured to receive a data voltage outputted by the data voltage output port of the display drive circuit, the second electrode of the data recording transistor is connected to the first electrode of the drive transistor, and the gate of the data recording transistor is configured to receive the gate signal N; the first electrode of the compensation transistor is connected to the second electrode of the drive transistor and the light emitting component, the second electrode of the compensation transistor is connected to the gate of the drive transistor, the first terminal of the first capacitor, and the first electrode of the first reset transistor, and the gate of the compensation transistor is configured to receive the gate signal N; the second output of the first capacitor is connected to the first input of the supply voltage; the gate of the first reset transistor is configured to receive the gate signal N-1; and the second electrode of the first reset transistor is configured to receive the initial voltage Vinit, where 1≤N≤M and N is a positive integer; the first electrode is a source and the second electrode is a drain, or the first electrode is a drain and the second electrode is a source, the first supply voltage input terminal is configured to input the first supply voltage, and the data voltage output port is configured to output the data voltage; And the channel width of at least one of the first reset transistor, the compensation transistor, and the data write transistor is less than 2 µm. 10. Electronic display device containing the display module according to any one of paragraphs. 1-9.

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