RU2792841C1 - Method for comparative evaluation of the resistance of batches of integrated circuits to electrostatic discharge - Google Patents

Abstract

FIELD: microelectronics.

SUBSTANCE: invention relates to the control of semiconductor integrated circuits (IC). Each IC from representative samples from each batch being compared is exposed to electrostatic discharges (ESD) of different polarity with a voltage equal to twice the value allowed by specifications for a given type of IC until the IC fails. The ICs of subsequent samples from the compared batches are exposed to the ESD potential increased by a certain amount, for example, 250 V, until the IC fails. The procedure with increasing ESR potential is repeated at least two times. Then dependencies are plotted for the sample-averaged values of the number of ESD pulses before until the IC fails exposed to the ESD voltage. The IC batch with the lower dependence obtained is assumed to be more resistant to ESD than the other batch.

EFFECT: increased reliability of resistance assessment of IC batches to ESD.

1 cl, 1 dwg, 1 tbl

Description

The invention relates to microelectronics, and in particular to methods for determining the resistance of integrated circuits (IC) to electrostatic discharge (ESD) in the manufacture of electronic equipment.

Known methods for sorting semiconductor products for resistance to ESD and reliability in general involve exposure to a product of the ESD series until a parametric or catastrophic failure occurs [see, for example, Patent 2226698 of the Russian Federation, Publ. 04/10/2004.], often introducing irreversible changes into the structure of products. It is known [cf. Gorlov M.I. Emelyanov AV, Plebanovich VI Electrostatic charges in electronics. - Minsk: Bel. The science. - 2006. - 295 p.], that semiconductor products, including ICs, even of the same production batch, have a spread in the number of ESD pulses leading to product failures, depending both on the ESD voltage and its sign.

The closest in technical essence to the proposed invention is a method for rejecting ICs according to patent 2146827 of the Russian Federation, taken as a prototype, according to which an informative parameter is measured, a single ESD pulse with a voltage equal to half of the allowable voltage according to specifications is applied to the IC, and then thermal annealing is carried out at the maximum allowable p-n-junction temperature for 24-48 hours, and ICs with informative parameters that go beyond the tolerance field after annealing are rejected.

The disadvantages of this method include the need for subsequent rather long temperature annealing, which does not completely restore the structure of the semiconductor product.

The invention is aimed at simplifying the procedure and increasing the reliability of the comparative assessment of the resistance of IC batches to electrostatic discharge. This is achieved by constructing dependences of the number of ESD pulses leading to IC failures on the ESD voltage for pulses of different polarity for the compared batches of ICs (an example of such dependences is shown in Fig. 1). It turned out that the most dangerous for IS, for example, type K561LN2, is the alternation of the polarity of the acting ESD pulses (in Fig. 1, this option is indicated as "+/-").

The technical result is achieved in the proposed method, which is carried out as follows. From the compared batches of the same type of IC, a sample of 10-20 pieces is randomly taken. The input-output terminals of the IC are supplied with an ESD voltage 2 times higher than the allowable according to the specifications according to the model of the human body, alternately positive and negative polarity until the IC fails. Then, 250 V more ESD pulses are applied to the ICs of the next sample from the batch, and then the procedure is repeated. The dependence of the number of ESD pulses, averaged over each sample, leading to failures, on the ESD voltage is plotted, and the IC batch, for which the resulting dependence will lie higher, is assumed to be more resistant to ESD compared to another batch, the dependence of which will lie lower.

The proposed method for comparative evaluation of IC batches in terms of ESD resistance was tested on two batches of ICs of the K561LN2 type. 15 schemes were selected from each batch by random selection. The first 5 ICs are supplied with ESD discharges of both positive and negative polarity of 500 V (allowable ESD voltage is 200 V) until the ICs fail. Then, the other 5 ICs are supplied with +-750V ESD, and then the next 5 ICs are supplied with +/-1000V ESD. The measurement results for two batches are shown in Table 1.

Table 1 Number of ESD pulses leading to IC failure batch number U _ESD = +-500 V
Number of pulses (N) ESD for IC U _ESD = +-750 V
Number of pulses (N) ESD for IC U _ESD = +-1000 V
Number of pulses (N) ESD for IC Average value of N at U _ESD 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 +-500 +-750 +-
1000 1 153 159 147 152 149 132 135 129 131 137 115 118 109 116 111 152 133 114 2 160 148 149 155 153 135 136 134 131 132 117 114 115 117 118 153 134 116

If we compare batches in terms of ESD resistance, then batch No. 2 will be more resistant, because the average value of the number of ESD exposures before failure is greater than that of batch No. 1.

Simplification of the evaluation procedure in comparison with the prototype is achieved by eliminating long-term thermal annealing.

Claims (1)

A method for comparative evaluation of the resistance of integrated circuits to electrostatic discharge, according to which the integrated circuits of representative samples from the compared batches are affected until the failure of each integrated circuit by electrostatic discharges of different polarity with a voltage of twice the value allowed by the technical specifications for integrated circuits, characterized in that integrated circuits of subsequent samples are exposed to electrostatic discharges of different polarity with a potential increased by a certain amount, for example, by 250 V, until the failure of each integrated circuit from the sample, the procedure with an increase in the voltage of the electrostatic discharge is repeated at least two times, then dependencies are plotted for the values of the number averaged over the samples electrostatic discharges before the failure of the integrated circuits from the voltage of the electrostatic discharge, the batch of integrated circuits, in which the obtained dependence will lie below, is taken b More ESD resistant than the other batch.

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