RU2790861C1 - Capacitor insulation device - Google Patents

Abstract

FIELD: semiconductor industry.

SUBSTANCE: invention relates to integrated circuits and can be used in systems for receiving, processing and transmitting digital and analog data, which require galvanic isolation of the data receiver and transmitter. The capacitor isolation device comprises first and second areas of integrated circuits 12 and 21, including functional circuits 122, 212, capacitor insulation control circuits 121, 211 located in the substrates of integrated circuits, insulating capacitors 1a, 1b, 2a, 2b made using conductive layers of these microcircuits. The insulating capacitors comprise the first plate located on the first conductive layer connected to the capacitor insulation control circuits, as well as the second plate located on the second conductive layer and connected to outputs 1, 2, 3, 4. By means of the switching device 5, the first output is electrically connected to the third output, the second output is connected to the fourth output, and each insulating capacitor comprises an area 301 located in the microcircuit substrates, under the lower plates of the capacitors.

EFFECT: reducing the capacitance of the lower plate of the insulating capacitor by using an insulating region in the substrate of the microcircuit located under the lower plate of the insulating capacitor, which allows using the first wiring level as the lower plate of the insulating capacitor without a significant decrease in the amplitude of the differential signal at the input of the receiver.

2 cl, 12 dwg

Description

The invention relates to the semiconductor industry, in particular to integrated circuits, and can be used in systems for receiving, processing and transmitting digital and analog data, which require galvanic isolation of the data receiver and transmitter.

In systems with galvanic isolation, important parameters are: isolation voltage, level of resistance to rapidly changing magnetic and electric fields of the environment. Several types of galvanic isolation are known, which are used in integrated circuits, among them:

- transformer,

- condenser,

- optoelectronic,

- magnetoresistive.

It should be noted that transformer and capacitor decoupling is the most widely used, due to their manufacturability when integrated into standard manufacturing processes for integrated circuits. Transformer-decoupled integrated circuits achieve a high level of resistance to magnetic fields, but they are always inferior to capacitor-decoupled microcircuits, which is due to the design of capacitors, in which there are no elements sensitive to magnetic fields. The level of resistance to rapidly changing electric fields depends on the design features of the entire priming path and the transmission of a galvanically isolated signal. In particular, in systems with capacitor isolation, a differential system for receiving and transmitting a signal is used, for which pairs of isolating capacitors are used in the receiver and transmitter. With a rapid change in the voltage difference on the isolated parts of the integrated circuit, the capacitances of the insulating capacitors are recharged, which causes the appearance of currents in the receiver and transmitter circuits, which can cause a violation of their operating mode and, as a result, a malfunction of the device. The positive effect of using pairs of capacitors is that the signal between the isolated parts of the receiver and transmitter is transmitted in the form of a voltage difference across the paired capacitors, which the currents that occur when the voltage difference across the isolated parts of the integrated circuit changes rapidly does not have such a significant effect in comparison with single isolating capacitors. Each insulating capacitor is made using metal layers of an integrated circuit, the number of which affects parameters such as insulation voltage, through capacitance and capacitance of the capacitor plates relative to the common substrate. The insulation voltage increases with an increase in the number of metal layers, and the capacitance decreases. In this case, the higher the level of the metal layer used as the lower lining of the insulating capacitor, the lower the insulation voltage. The capacitance of the bottom plate relative to the common substrate also depends on what level of the metal layer is used in it. The higher this level, the lower the capacitance, which is determined by the number and thickness of the underlying dielectric layers. The capacitance of the top lining, usually performed at the highest level of metal, also depends on the number of metal layers used and decreases with increasing number of them.

(Capacitive Isolation: A Fundamental Building Block in Future AC/DC Power Conversion, by Zhihong Yu, AC/DC & Lighting Product Marketing Manager, Monolithic Power Systems) [2] describes a voltage-isolated integrated circuit that contains two galvanically isolated crystals containing functional circuits located in the substrates of said crystals, as well as integrated capacitive decoupling circuits of functional circuits, wherein the capacitive decoupling circuit is made in the conductive layers of the crystals. Capacitive decoupling circuits contain at least two capacitors on each crystal and have top and bottom plates made in the conductive layers of the respective crystals. The functional circuits are electrically connected to the bottom plates of the capacitors, and the top plates are used to connect isolated crystals to each other, creating a capacitive coupling between the crystals. The signals between the functional circuits are transmitted through isolating capacitors, which are connected in series, resulting in an isolation voltage equal to the sum of the two isolation voltages. On one of the crystals, called the transmitter, there is a circuit for generating a transmitted differential signal, and on the second crystal, called a receiver, there is a circuit for receiving and amplifying the differential signal. The shape and frequency of the transmitted signal is determined by the value of the capacitance of the insulating capacitors and can be close to sinusoidal, with a frequency of hundreds of megahertz. In this case, the amplitude of the received signal is significantly affected not only by the capacitances of the insulating capacitors, but also by the parasitic capacitances of the capacitor plates. The parasitic capacitance of the lower plate has a significant effect, reducing which allows you to increase the signal at the receiver input, thereby increasing the reception reliability, as well as increasing the level of resistance to the common mode signal.

Closest to the claimed invention is known from the prior art capacitor insulation device presented in the patent [1]. This device is chosen as a prototype of the proposed device.

The disadvantages of this invention include the design of insulating capacitors, in which the through capacitance is less than the parasitic capacitance of the lower plate relative to the substrate. In the prototype, in Fig. 12, their values are given as 88fF and 165fF, respectively. This leads to a decrease in the amplitude of the useful signal at the receiver input and to a decrease in the level of resistance to common mode noise.

The object of the present invention is to provide a capacitor insulator device with a higher insulation voltage and a lower capacitance value of the bottom plate of the insulating capacitors.

The technical result consists in reducing the capacitance of the lower plate of the insulating capacitor due to the use of an insulating region in the substrate of the microcircuit located under the lower plate of the insulating capacitor, which allows the first conductive layer to be used as the lower plate of the insulating capacitor without a significant decrease in the amplitude of the differential signal at the input of the receiver.

To achieve the above technical result, a capacitor isolation device containing the first area of the integrated circuit, including functional circuits, capacitor insulation control circuits located in the substrate of the integrated circuit, containing insulating capacitors made using conductive layers of this integrated circuit, as well as the second area of the integrated circuit, including functional circuits, capacitor isolation control circuits containing insulating capacitors made using conductive layers of this integrated circuit, while the capacitive isolation circuit of the first region of the integrated circuit includes a first insulating capacitor containing a first lining located on the first conductive layer connected to the functional circuits , as well as the second plate located on the second conductive layer and connected to the first output, as well as the second insulating capacitor containing the first plate, located laid on the first conductive layer connected to the functional circuits, as well as the second plate located on the second conductive layer and connected to the second output; the capacitive isolation circuit of the second area of the integrated circuit includes a third insulating capacitor containing a first plate located on the first conductive layer connected to the functional circuits, as well as a second plate located on the second conductive layer and connected to the third output, as well as a fourth insulating capacitor containing the first plate located on the first conductive layer connected to the functional circuits, as well as the second plate located on the second conductive layer and connected to the fourth output, while, using a switching device, the first output is electrically connected to the third output, and the second output is connected with the fourth exit.

There is a variant in which the isolated areas of integrated circuits contain six conductive layers, while the lower plate of the insulating capacitors is made in the first conductive layer, the upper plate is made in the sixth conductive layer, and each insulating capacitor contains an insulation area of the lower plate of the capacitor located in the chip substrate.

The specified technical result is achieved by the fact that in the device of the capacitor insulator, insulating areas are additionally used, located in the substrates of integrated circuits, directly under the lower plates of the insulating capacitors, and the insulation area of the lower plate of the capacitor is made in the form of a grid of vertical dielectric layers.

The essence of the invention is illustrated by drawings, where:

- in Fig. 1 shows the device of the capacitor insulator according to the patent (1), where

1602 - the first and second areas of integrated circuits,

1603 - data inputs and outputs of the receiver and transmitter,

1604 - the first isolating capacitors,

1605 - second isolating capacitors,

1606 - functional diagrams of receivers and transmitters,

1607 - a device for connecting capacitors of isolated microcircuits.

- in Fig. 2 shows a section of the structure of an insulating capacitor according to (1), where

300 - crystal substrate,

101 - conductive area of the lower plate of the capacitor,

102 - conductive area of the upper plate of the capacitor,

201-206 - insulating areas of the conductive layers of the microcircuit.

- in Fig. 3 shows a sectional view of the structure of an insulating capacitor according to this invention, where

300 - crystal substrate,

301 - isolating area,

101 - conductive area of the lower plate of the capacitor,

102 - conductive area of the upper plate of the capacitor,

201-206 - insulating areas of the conductive layers of the microcircuit.

- in Fig. 4 shows the equivalent circuit of two isolating capacitors according to the patent (1) where

601 - passing capacitance of the insulating capacitor of the first microcircuit,

601a - capacitance of the lower lining on the chip substrate,

601b - capacitance of the upper plate on the microcircuit substrate,

602 - passing capacitance of the insulating capacitor of the second microcircuit,

602a - capacitance of the lower lining on the chip substrate,

602b - capacitance of the upper plate on the chip substrate,

5 - connection of the upper plates of insulating capacitors.

- in Fig. 5 shows the equivalent circuit of two isolating capacitors according to this invention, where

601 - passing capacitance of the insulating capacitor of the first microcircuit,

601a - capacitance of the lower lining on the insulating area of the microcircuit,

601b - capacitance of the upper plate on the plates on the insulating area of the microcircuit,

601c - capacitance of the insulating area of the microcircuit on the substrate,

602 - passing capacitance of the insulating capacitor of the first microcircuit,

602a - capacitance of the lower lining on the insulating area of the microcircuit,

602b - capacitance of the upper plate on the plates on the insulating area of the microcircuit,

602s - capacitance of the insulating area of the microcircuit on the substrate,

5 - connection of the upper plates of insulating capacitors.

- in Fig. 6 shows an equivalent circuit of the transceiver path according to this invention, where

600a,b - transmitter drivers of the first chip,

1-4 - insulating capacitors of the transmitter and receiver microcircuits,

605a,b - equivalent input impedances of the receiver,

606a - capacitance of the insulating region of the microcircuit on the substrate,

5a,b - connection of the upper plates of insulating capacitors.

- in Fig. 7 shows a section of the structure of an insulating capacitor according to this invention using dielectric insulation elements, where

300 - crystal substrate,

400 - horizontal insulating area,

500 - vertical isolating areas,

101 - conductive area of the lower plate of the capacitor,

102 - conductive area of the upper plate of the capacitor,

201-206 - insulating areas of the conductive layers of the microcircuit.

- in Fig. 8 shows the topology of the dielectric insulation layer in an insulating capacitor according to this invention, where

the vertical isolating regions 500 are in the form of a grid.

- in Fig. 9 shows the results of modeling the receiving-transmitting path, where

WF_1 - differential signal at the input of the receiver in the presence of an insulating area under the lower plate of the capacitor,

WF_2 - differential signal at the input of the receiver in the absence of an insulating area under the lower plate of the capacitor,

WF_3 - differential common mode signal,

WF_4 - differential signal at the output of the transmitter in the presence of an isolating area,

WF_5 - differential signal at the output of the transmitter in the absence of an isolating region.

- in Fig. 10 shows a block diagram of a transceiver channel with isolating capacitors according to this invention, where

12 and 21 - isolated chips of microcircuits,

122 and 212 - functional diagrams,

121 and 211 - receivers and transmitters,

1a,b - isolating capacitors of the first crystal,

2a,b - insulating capacitors of the second crystal,

5 - switching device,

5a,b - connection of the upper plates of insulating capacitors.

- in Fig. 11 shows a timing diagram of the operation of a transceiver channel with isolating capacitors according to this invention, where

700a,b - signals at the outputs of the transmitter drivers,

701 - signal restored at the output of the receiver.

- in Fig. 12 shows the equivalent circuit of one isolation capacitor according to US 8169108, where

1110 - isolating capacitor,

1102 - parasitic capacitor of the lower plate,

1104 - bottom lining,

1106 - parasitic capacitor of the upper plate,

1108 - top lining.

The invention is carried out as follows.

The capacitor isolation device comprises (FIG. 10) the first area of the integrated circuit 12, including functional circuits 122, capacitor insulation control circuits 121 located in the integrated circuit substrate, as well as insulating capacitors 1a, 1b, made using the conductive layers of this integrated circuit, and also the second area of the integrated circuit 21, including functional circuits 212, capacitor insulation control circuits 211, as well as insulating capacitors 2a, 2b, made using conductive layers of this integrated circuit, while the capacitive isolation circuit of the first area of the integrated circuit includes the first insulating capacitor 1a, containing the first plate located on the first conductive layer connected to the capacitor insulation control circuits 121, as well as the second plate located on the second conductive layer and connected to the first output 1, as well as the second insulating capacitor containing the first the second plate located on the first conductive layer connected to the capacitor insulation driving circuits 121, as well as the second plate located on the second conductive layer and connected to the second output 2, the capacitive isolation circuit of the second area of the integrated circuit includes a third insulating capacitor 2a containing the first plate located on the first conductive layer connected to the capacitor insulation control circuits 211, as well as the second plate located on the second conductive layer and connected to the third output 3, as well as the fourth insulating capacitor containing the first plate located on the first conductive layer connected to capacitor insulation control circuits 211, as well as the second plate located on the second conductive layer and connected to the fourth output 4, while using the switching device 5, the first output is electrically connected to the third output, the second output is connected to the fourth output, and each isolating The second capacitor contains an area 301, which is located in the substrate of the microcircuit, under the lower plate of the capacitor.

In a particular case of the invention, the isolated areas of integrated circuits contain six conductive layers, while the lower lining of the insulating capacitors is made in the first conductive layer, and the upper lining is made in the sixth conductive layer, and the area 301 (Fig. 3) is made in the form of a grid of vertical dielectric layers (Fig. 8).

Conditional sections of insulating capacitors are shown in Fig. 2 and 3, on which 101 and 102 are the lower and upper plates of insulating capacitors, 201-205 are insulating dielectric layers, 300 is a microcircuit substrate, 301 is an isolated area. The use of isolated regions 301 located in the substrates of integrated circuits directly below the bottom plates of the insulating capacitors makes it possible to reduce the capacitance of the bottom plates of the insulating capacitors relative to the chip substrate. In this case, two positive effects are achieved: firstly, the amplitude of the differential signal entering the receiver inputs increases and, secondly, the effect of common-mode noise is reduced. In FIG. 4 and 5 are equivalent circuits of two electrically coupled insulating capacitors, explaining the effect of the additional insulating region. The reduction in the capacitances of the lower plates of the insulating capacitors occurs due to the capacitances of the additional insulating regions 601c, 602c connected in series with the capacitances of the lower plates 601a, 602a. In FIG. 6 shows the equivalent circuit of one channel of the transceiver path, which includes drivers 600a, 600b, isolation capacitors 1-4, equivalent receiver input impedances 605a, 605b, and a differential receiver 606a. In FIG. 9 shows the simulation results of the process of transmitting the differential output signal WF_4 through isolating capacitors to the input of the receiver: WF_2 in the absence of an isolating region and WF_1 in its presence. In the time interval 5.08 µs - 5.1 µs, the signal amplitudes differ by more than 2 times. In the time interval 5.1 µs - 5.15 µs, the common mode signal WF_3 changes from 0 V to 3 kV, which corresponds to a rate of change of 60 kV/µs. In this case, the WF_2 signal significantly decreases in amplitude and changes its shape, while the WF_1 signal only slightly decreases in amplitude while maintaining the shape. This behavior of the signals at the input of the receiver is due to the fact that recharging the capacitance of the lower lining of the insulating capacitors leads to an increase in the output current of the drivers and, as a result, to an increase in the voltage drop across its output transistors, which contributes both to a decrease in the output voltage and to a change in the shape of the output signal WF_4, WF_5.

An integrated circuit of a digital transceiver containing four digital reverse channels based on CMOS technology with a design standard of 0.18 microns and full dielectric insulation was developed, manufactured and researched.

The design of the insulating capacitor included the first and sixth levels of metals as insulating capacitor plates and a grid of vertical dielectric layers as an insulating layer located under the lower capacitor plate. The dimensions of the capacitors were 103 µm x 103 µm. The transmitter drivers are made on the basis of CMOS transistors with an operating voltage of 5 V and sizes W=72 µm, L=0.5 µm and W=32 µm, L=0.5 µm, p- and p-channel transistors, respectively. The receivers are made on the basis of 3 stages of differential amplifiers with capacitive decoupling, as well as detector circuits and a comparator of levels of amplified signals. The forms of transmitted and received signals are shown in Fig. 11, where 600a, 600b are driver outputs and 606a is the level comparator output. The logic zero level corresponds to time intervals where there are no pulses, and the logic one level corresponds to time intervals filled with pulses. Measurements have shown that the insulation voltage exceeds 5 kV, and the level of resistance to the effects of rapidly changing electric fields exceeds the rate of change of 20 kV/µs.

Literature

1. US Patent 8,169,108.

2. Capacitive Isolation: A Fundamental Building Block in Future AC/DC Power Conversion, by Zhihong Yu, AC/DC & Lighting Product Marketing Manager, Monolithic Power Systems.

Claims (2)

1. A capacitor isolation device containing the first area of the integrated circuit, including functional circuits, capacitor insulation control circuits, as well as insulating capacitors located in the substrate of the integrated circuit, made using conductive layers of this integrated circuit, as well as the second area of the integrated circuit, including functional circuits, capacitor isolation control circuits, as well as insulating capacitors, made in the substrate of the integrated circuit, using the conductive layers of this integrated circuit, while the insulating capacitors of the first region of the integrated circuit include the first insulating capacitor, containing the first plate located on the first conductive layer connected with capacitor insulation control circuits, as well as a second plate located on the second conductive layer and connected to the first output, as well as a second insulating capacitor containing the first plate, located laid on the first conductive layer connected to the capacitor insulation control circuits, as well as the second plate located on the second conductive layer and connected to the second output, the insulating capacitors of the second area of the integrated circuit include a third insulating capacitor containing the first plate located on the first conductive layer, connected to the capacitor insulation control circuits, as well as the second plate located on the second conductive layer and connected to the third output, as well as the fourth insulating capacitor containing the first plate located on the first conductive layer connected to the capacitor insulation control circuits, as well as the second plate located on the second conductive layer and connected to the fourth output, while using the switching device, the first output is electrically connected to the third output, and the second output is connected to the fourth output, and each insulating capacitor contains an isolation area the bottom plate of the capacitor, located in the substrate of the microcircuit. 2. The device according to claim. 1, characterized in that the isolated areas of integrated circuits contain six conductive layers, while the lower plate of the insulating capacitors is made in the first conductive layer, the upper plate is made in the sixth conductive layer, and the insulation area of the lower plate of the capacitor is made in the form grids of vertical dielectric layers.

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