CN111326496B - Isolation capacitor and isolation circuit - Google Patents
Isolation capacitor and isolation circuit Download PDFInfo
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- CN111326496B CN111326496B CN202010149101.0A CN202010149101A CN111326496B CN 111326496 B CN111326496 B CN 111326496B CN 202010149101 A CN202010149101 A CN 202010149101A CN 111326496 B CN111326496 B CN 111326496B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
Abstract
The invention discloses an isolation capacitor and an isolation circuit, wherein the isolation capacitor comprises a substrate, a dielectric layer positioned on the substrate and electrode wires positioned on the dielectric layer, the electrode wires comprise first electrode wires and second electrode wires which are arranged at intervals, and the isolation capacitor is electrically connected with an external chip or system through the first electrode wires and/or the second electrode wires so as to realize electrical isolation. The medium layer is arranged on the substrate in the isolation capacitor, and the two stages are arranged on the surface of the medium layer, so that parasitic capacitance between polar plates is reduced, attenuation in the AC signal transmission process is reduced, and back-to-back enhancement type isolation can be realized; the size of the isolation voltage can be realized by changing the interval between two electrode wires, the preparation process is not required to be changed, and the process cost is greatly reduced.
Description
Technical Field
The invention belongs to the technical field of isolation circuits, and particularly relates to an isolation capacitor and an isolation circuit.
Background
Isolation capacitors, particularly high voltage capacitor isolation circuits, are increasingly being used for signal transmission between chips or systems in different voltage domains, which can provide electrical isolation of up to several kilovolts between two or more chips or systems, achieve "ground" isolation between different voltage domains, and improve the reliability of the chips or systems.
The high voltage capacitive isolation circuit is typically composed of a Transmitter (TX), a Receiver (RX), and a high voltage isolation capacitor for completing transmission of an ac signal while blocking passage of a dc signal, thereby achieving high voltage isolation.
The high-voltage isolation capacitor is usually realized by improving the thickness of the medium between different metal layers on the basis of the existing mature CMOS process, so that the difficulty in process realization is greatly improved, the thickness of a chip is increased, and the process cost is increased; meanwhile, the increase of the thickness of the dielectric layer also obviously reduces the capacitance of a unit area, so that the area of the capacitor needs to be increased when a certain capacitance value is needed to be realized, and the cost of the chip is increased.
Referring to fig. 1, a schematic diagram of an isolation circuit in the prior art is shown, which includes a first chip 10 'and a second chip 20', wherein a plurality of signal transmitting units 11 '(or signal receiving units) and a first isolation capacitor 31' are integrated on the first chip 10', a plurality of signal receiving units 21' (or signal transmitting units) and a second isolation capacitor 32 'are integrated on the second chip 20', and two isolation capacitors (the first isolation capacitor 31 'and the second isolation capacitor 32') in different voltage domains are electrically connected through Bonding wires, so as to realize back-to-back capacitor serial connection enhanced isolation.
Referring to fig. 2, a schematic structure of an isolation capacitor (a first isolation capacitor 31' or a second isolation capacitor 32 ') is shown, which includes a substrate 301', a lower electrode plate 302', a dielectric layer 303' and an upper electrode plate 304' from bottom to top, and the high-voltage isolation capacitor can be realized by increasing the thickness of the dielectric layer 303' between the lower electrode plate and the upper electrode plate.
The preparation method of the high-voltage isolation capacitor in the prior art is generally based on a standard CMOS process, an upper polar plate and a lower polar plate of the high-voltage isolation capacitor are formed by upper and lower layers of metal, and the thickness of a dielectric layer between the upper polar plate and the lower polar plate is increased to realize high isolation voltage level. This approach suffers from two drawbacks:
1. larger parasitic capacitance exists between the upper polar plate, the lower polar plate and the substrate of the capacitor, so that the transmitted AC signal is attenuated greatly;
2. to achieve a higher isolation voltage level, the thickness of the dielectric layer must be further increased, which requires adjustment of the manufacturing process, and has the disadvantages of high implementation difficulty, long period, and high cost.
Therefore, in order to solve the above-mentioned problems, it is necessary to provide an isolation capacitor and an isolation circuit.
Disclosure of Invention
The invention aims to provide an isolation capacitor and an isolation circuit, which are used for reducing parasitic capacitance between polar plates and reducing signal transmission attenuation.
In order to achieve the above object, an embodiment of the present invention provides the following technical solution:
the isolation capacitor comprises a substrate, a dielectric layer positioned on the substrate and electrode wires positioned on the dielectric layer, wherein the electrode wires comprise first electrode wires and second electrode wires which are arranged at intervals, and the isolation capacitor is electrically connected with an external chip or a system through the first electrode wires and/or the second electrode wires so as to realize electrical isolation.
In an embodiment, the first electrode lines and the second electrode lines are distributed in a comb-like and crossed manner.
In an embodiment, the first electrode wire includes a first main electrode wire and a plurality of first sub electrode wires electrically connected to the first main electrode wire, and the second electrode wire includes a second main electrode wire and a plurality of second sub electrode wires electrically connected to the second main electrode wire.
In one embodiment, the first main electrode line and the first sub electrode line are vertically distributed, and the second main electrode line and the second sub electrode line are vertically distributed.
In an embodiment, the first electrode lines and the second electrode lines are distributed at equal intervals or non-equal intervals.
In an embodiment, the isolation capacitor includes a plurality of first electrode lines and a plurality of second electrode lines that are distributed in cascade.
The technical scheme provided by the other embodiment of the invention is as follows:
an isolation circuit, the isolation circuit comprising:
the first chip comprises a first substrate and a plurality of signal sending units and/or signal receiving units integrated on the first substrate;
the second chip comprises a second substrate and a plurality of signal receiving units and/or signal transmitting units integrated on the second substrate;
the isolation capacitor is the isolation capacitor and is positioned between the signal sending unit and the signal receiving unit of the first chip and the second chip and used for realizing electric isolation between the first chip and the second chip.
In an embodiment, the first substrate is provided with a first bonding area electrically connected with the signal transmitting unit and/or the signal receiving unit, the second substrate is provided with a second bonding area electrically connected with the signal receiving unit and/or the signal transmitting unit, the substrate of the isolation capacitor is provided with a third bonding area and a fourth bonding area electrically connected with the upper polar plate and/or the lower polar plate, and the first bonding area is electrically connected with the third bonding area, and the second bonding area is electrically connected with the fourth bonding area.
A further embodiment of the present invention provides the following technical solution:
an isolation circuit, the isolation circuit comprising:
the first chip comprises a first substrate and a plurality of signal sending units and/or signal receiving units integrated on the first substrate;
the second chip comprises a second substrate and a plurality of signal receiving units and/or signal transmitting units integrated on the second substrate;
the first chip and the second chip further comprise a dielectric layer and electrode wires positioned on the dielectric layer, the electrode wires comprise first electrode wires and second electrode wires which are arranged at intervals, and the isolation capacitor is electrically connected with an external chip or a system through the first electrode wires and/or the second electrode wires so as to realize electrical isolation.
In an embodiment, a fifth bonding area electrically connected with the signal transmitting unit and/or the signal receiving unit is arranged on the first substrate, a sixth bonding area electrically connected with the signal receiving unit and/or the signal transmitting unit is arranged on the second substrate, the signal transmitting unit and/or the signal receiving unit on the first substrate are electrically connected with the fifth bonding area through a first electrode wire and/or a second electrode wire on the first substrate, the signal receiving unit and/or the signal transmitting unit on the second substrate are electrically connected with the sixth bonding area through a first electrode wire and/or a second electrode wire on the second substrate, and the fifth bonding area and the sixth bonding area are electrically connected.
Compared with the prior art, the invention has the following advantages:
the medium layer is arranged on the substrate in the isolation capacitor, and the two stages are arranged on the surface of the medium layer, so that parasitic capacitance between polar plates is reduced, attenuation in the AC signal transmission process is reduced, and back-to-back enhancement type isolation can be realized;
the size of the isolation voltage can be realized by changing the interval between two electrode wires, the preparation process is not required to be changed, and the process cost is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of an isolation circuit of the prior art;
FIG. 2 is a schematic diagram of an isolation capacitor in the prior art;
FIG. 3 is a schematic cross-sectional view of a isolation capacitor according to a first embodiment of the present invention;
fig. 4 is a schematic plan view of an electrode wire according to a first embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a isolation capacitor according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a isolation circuit according to a third embodiment of the present invention;
fig. 7 is a schematic diagram of a isolation circuit according to a fourth embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the embodiments shown in the drawings. The embodiments are not intended to limit the invention, but structural, methodological, or functional modifications of the invention from those skilled in the art are included within the scope of the invention.
The invention discloses an isolation capacitor, which comprises a substrate, a dielectric layer positioned on the substrate and electrode wires positioned on the dielectric layer, wherein the electrode wires comprise first electrode wires and second electrode wires which are arranged at intervals, and the isolation capacitor is electrically connected with an external chip or system through the first electrode wires and/or the second electrode wires so as to realize electrical isolation.
The invention also discloses an isolation circuit, which comprises:
the first chip comprises a first substrate and a plurality of signal sending units and/or signal receiving units integrated on the first substrate;
the second chip comprises a second substrate and a plurality of signal receiving units and/or signal transmitting units integrated on the second substrate;
and the isolation capacitor is positioned between the signal transmitting unit and the signal receiving unit of the first chip and the second chip and is used for realizing electric isolation between the first chip and the second chip.
The invention also discloses an isolation circuit, which comprises:
the first chip comprises a first substrate and a plurality of signal sending units and/or signal receiving units integrated on the first substrate;
the second chip comprises a second substrate and a plurality of signal receiving units and/or signal transmitting units integrated on the second substrate;
the first chip and the second chip further comprise a dielectric layer and electrode wires positioned on the dielectric layer, the electrode wires comprise first electrode wires and second electrode wires which are arranged at intervals, and the isolation capacitor is electrically connected with an external chip or a system through the first electrode wires and/or the second electrode wires so as to realize electrical isolation.
The isolation capacitor and isolation circuit of the present invention are further described below in connection with specific embodiments.
Referring to fig. 3, a schematic structural diagram of an isolation capacitor according to a first embodiment of the present invention is shown, where the isolation capacitor 30 in this embodiment includes a substrate 31, a dielectric layer 32 on the substrate, and an electrode line 33 on the first dielectric layer from bottom to top.
Referring to fig. 4, the electrode wires in the present embodiment include a first electrode wire 331 and a second electrode wire 332 that are disposed at intervals, and the isolation capacitor is electrically connected to an external chip or system through the first electrode wire 331 and the second electrode wire 332 to realize electrical isolation.
The dielectric layer 32 in this embodiment is SiO 2 The material and thickness of dielectric layer 32 may be designed as desired.
Specifically, the first electrode line 331 and the second electrode line 332 in the embodiment are distributed in a comb-like manner, wherein the first electrode line 331 includes a first main electrode line 3311 and a plurality of first sub-electrode lines 3312 electrically connected to the first main electrode line, the second electrode line 332 includes a second main electrode line 3321 and a plurality of second sub-electrode lines 3322 electrically connected to the second main electrode line, the first main electrode line 3311 and the first sub-electrode lines 3312 are vertically distributed, and the second main electrode line 3321 and the second sub-electrode lines 3322 are vertically distributed.
Further, the first electrode line 331 and the second electrode line 332 are equally spaced, that is, the first sub-electrode line 3312 and the second sub-electrode line 3322 are equally spaced, and the specific spacing may be designed according to the required isolation voltage.
In the prior art, the size of the capacitor is realized by controlling the thickness of a dielectric layer between the upper polar plate and the lower polar plate, but the size of the capacitor can be realized by changing the distance between two electrode wires without changing the preparation process, thereby greatly reducing the process cost.
The first electrode line 331 and the second electrode line 332 in this embodiment may form a capacitor for electrical isolation therebetween as two plates of the capacitor.
In addition, the isolation capacitor 30 is electrically connected (e.g. by Bonding wire) to an external chip or system through the first electrode wire 331 and the second electrode wire 332 to achieve electrical isolation, for example, the first electrode wire 331 in the present embodiment further includes a first connection wire 334, the second electrode wire further includes a second connection wire 335, and the first connection wire 334 and the second connection wire 335 are electrically connected to the external chip or system respectively.
In the isolation capacitor of the embodiment, the capacitor is manufactured on a separate substrate, and the electrode wire is spaced from the chip substrate by a relatively thick SiO 2 The parasitic capacitance of the dielectric layer and the two poles of the capacitor is obviously reduced, and the transmission attenuation of the AC signal is also obviously reduced.
Referring to fig. 5, a schematic diagram of a structure of an electrode line on an isolation capacitor in a first embodiment of the present invention is shown, and referring to fig. 3, an isolation capacitor 30 in this embodiment includes a substrate 31, a dielectric layer 32 on the substrate, and an electrode line 33 on the first dielectric layer from bottom to top.
Referring to fig. 5, the electrode wires in the present embodiment include a first electrode wire 331, a second electrode wire 332 and a third electrode wire 333 that are disposed at intervals, and the isolation capacitor is electrically connected to an external chip or system through the first electrode wire 331 and the third electrode wire 333 to realize electrical isolation.
The first electrode line 331 and the second electrode line 332, and the second electrode line 332 and the third electrode line 333 in the present embodiment are distributed in a comb-like manner, and the specific distribution manner is similar to that of the first embodiment, and the detailed description is omitted here.
Similarly, the first electrode line 331 and the second electrode line 332, and the second electrode line 332 and the third electrode line 333 are equally spaced, and the specific spacing may be designed according to the required isolation voltage.
In this embodiment, the left half part of the first electrode line 331 and the second electrode line 332 are used as two plates of a capacitor, the right half part of the second electrode line 332 and the third electrode line 333 are used as two plates of another capacitor, and the two capacitors are connected in series in two stages to form a capacitor for electrical isolation.
It should be understood that, in this embodiment, two capacitors are illustrated in series, and in other embodiments, the number of series capacitors may be increased by increasing the number of electrode lines, so as to achieve different isolation voltage levels.
Referring to fig. 6, a schematic diagram of an isolation circuit according to a third embodiment of the present invention is shown, where the isolation circuit includes:
a first chip 10 including a first substrate 101 and a plurality of signal transmitting units 11 (or signal receiving units) integrated on the first substrate 101;
a second chip 20 including a second substrate 201 and a plurality of signal receiving units 21 (or signal transmitting units) integrated on the second substrate 201;
the isolation capacitor 30, the isolation capacitor 30 is an isolation capacitor in the first embodiment, and is located between the signal transmitting unit 11 and the signal receiving unit 21 of the first chip 10 and the second chip 20, for achieving electrical isolation between the first chip 10 and the second chip 20.
Further, in the present embodiment, the first substrate 101 is provided with a first bonding region 12 electrically connected to the signal transmitting unit 11, the second substrate 201 is provided with a second bonding region 22 electrically connected to the signal receiving unit 21, the substrate of the isolation capacitor 30 is provided with a third bonding region 301 and a fourth bonding region 302 electrically connected to the first electrode line and the second electrode line, and the first bonding region 12 and the third bonding region 301, and the second bonding region 22 and the fourth bonding region 302 are electrically connected.
In this embodiment, all electrode lines in the isolation capacitor are formed on the same substrate, each group of electrode lines forms a capacitor, and electrical isolation is performed for signal paths (channels) between each group of signal receiving units and the signal transmitting units, where the number of signal paths is n, n signal transmitting units and/or signal receiving units are disposed on the first chip, n signal receiving units and/or signal transmitting units are disposed on the second chip, and n groups of electrode lines described in the first embodiment are disposed on the isolation capacitor.
Referring to fig. 7, a schematic diagram of an isolation circuit according to a fourth embodiment of the present invention is shown, the isolation circuit includes:
a first chip 10 including a first substrate 101 and a plurality of signal transmitting units 11 (or signal receiving units) integrated on the first substrate 101;
a second chip 20 including a second substrate 201 and a plurality of signal receiving units 21 (or signal transmitting units) integrated on the second substrate 201;
the first chip 10 and the second chip 20 in this embodiment and the isolation capacitor 30 share the first substrate 101 and the second substrate 201, and the first substrate 101 and the second substrate 201 further include a dielectric layer and an electrode wire on the dielectric layer, where the arrangement of the dielectric layer and the electrode wire is the same as the first embodiment, and no description is repeated here.
Further, the first substrate 101 is provided with a fifth bonding area 13 electrically connected to the signal transmitting unit 11, the second substrate 201 is provided with a sixth bonding area 23 electrically connected to the signal receiving unit 21, the signal transmitting unit 11 on the first substrate 101 is electrically connected to the fifth bonding area 13 through a first electrode wire on the first substrate, the signal receiving unit 21 on the second substrate 201 is electrically connected to the sixth bonding area 23 through a second electrode wire on the second substrate, and the fifth bonding area 13 and the sixth bonding area 23 are electrically connected.
The technical scheme shows that the invention has the following beneficial effects:
the medium layer is arranged on the substrate in the isolation capacitor, and the two stages are arranged on the surface of the medium layer, so that parasitic capacitance between polar plates is reduced, attenuation in the AC signal transmission process is reduced, and back-to-back enhancement type isolation can be realized;
the size of the isolation voltage can be realized by changing the interval between two electrode wires, the preparation process is not required to be changed, and the process cost is greatly reduced.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment contains only one independent technical solution, and that such description is provided for clarity only, and that the technical solutions of the embodiments may be appropriately combined to form other embodiments that will be understood by those skilled in the art.
Claims (7)
1. The isolation capacitor is characterized by comprising a substrate, a dielectric layer positioned on the substrate and an electrode wire positioned on the dielectric layer, wherein the electrode wire comprises a first electrode wire, a second electrode wire and a third electrode wire which are arranged at intervals, the second electrode wire comprises a first part, a second part and a ridged electrode wire, the first part and the second part share the ridged electrode wire, the ridged electrode wire and the first part and the second part of the second electrode wire are vertically arranged, and the isolation capacitor is electrically connected with an external chip or system through the first electrode wire and the third electrode wire so as to realize electrical isolation.
2. The isolation capacitor of claim 1, wherein first portions of the first and second electrode lines are arranged in a comb-like interleaved arrangement, and second portions of the second and third electrode lines are arranged in a comb-like interleaved arrangement.
3. The isolation capacitor of claim 2, wherein the first electrode line and the second electrode line comb-shaped intersections are equally spaced or non-equally spaced, and the second electrode line and the third electrode line comb-shaped intersections are equally spaced or non-equally spaced.
4. An isolation circuit, the isolation circuit comprising:
the first chip comprises a first substrate and a plurality of signal sending units and/or signal receiving units integrated on the first substrate;
the second chip comprises a second substrate and a plurality of signal receiving units and/or signal transmitting units integrated on the second substrate;
the isolation capacitor is an isolation capacitor according to any one of claims 1 to 3, and is located between the signal sending unit and the signal receiving unit of the first chip and the second chip, and is used for realizing electrical isolation between the first chip and the second chip.
5. The isolation circuit of claim 4, wherein a first bonding region electrically connected to the signal transmitting unit and/or the signal receiving unit is provided on the first substrate, a second bonding region electrically connected to the signal receiving unit and/or the signal transmitting unit is provided on the second substrate, a third bonding region and a fourth bonding region electrically connected to the upper plate and/or the lower plate are provided on the substrate of the isolation capacitor, and the first bonding region and the third bonding region, and the second bonding region and the fourth bonding region are electrically connected.
6. An isolation circuit, the isolation circuit comprising:
the first chip comprises a first substrate and a plurality of signal sending units and/or signal receiving units integrated on the first substrate;
the second chip comprises a second substrate and a plurality of signal receiving units and/or signal transmitting units integrated on the second substrate;
the first chip and the second chip are further provided with a dielectric layer and electrode wires positioned on the dielectric layer, the electrode wires comprise a first electrode wire, a second electrode wire and a third electrode wire which are arranged at intervals, the second electrode wire comprises a first part, a second part and a ridged electrode wire, the first part and the second part share the ridged electrode wire, the ridged electrode wire is perpendicular to the first part and the second part of the second electrode wire, and the isolation capacitor is electrically connected with an external chip or a system through the first electrode wire and the third electrode wire to realize electrical isolation.
7. The isolation circuit of claim 6, wherein a fifth bonding region electrically connected to the signal transmitting unit and/or the signal receiving unit is provided on the first substrate, a sixth bonding region electrically connected to the signal receiving unit and/or the signal transmitting unit is provided on the second substrate, the signal transmitting unit and/or the signal receiving unit on the first substrate is electrically connected to the fifth bonding region through a first electrode wire and/or a second electrode wire on the first substrate, the signal receiving unit and/or the signal transmitting unit on the second substrate is electrically connected to the sixth bonding region through a first electrode wire and/or a second electrode wire on the second substrate, and the fifth bonding region and the sixth bonding region are electrically connected.
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| CN202010149101.0A CN111326496B (en) | 2020-03-05 | 2020-03-05 | Isolation capacitor and isolation circuit |
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| CN202010149101.0A CN111326496B (en) | 2020-03-05 | 2020-03-05 | Isolation capacitor and isolation circuit |
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| US6539253B2 (en) * | 2000-08-26 | 2003-03-25 | Medtronic, Inc. | Implantable medical device incorporating integrated circuit notch filters |
| CN103247592B (en) * | 2012-02-14 | 2015-11-25 | 无锡华润上华半导体有限公司 | MOM capacitor and preparation method thereof |
| ITTO20120179A1 (en) * | 2012-02-28 | 2013-08-29 | St Microelectronics Srl | MICROELETTROMECHANICAL SENSOR WITH OUT OF PLAN DETECTION AND PROCEDURE FOR THE MANUFACTURE OF A MICROELETTROMECANICAL SENSOR |
| JP6115408B2 (en) * | 2013-08-29 | 2017-04-19 | 三菱電機株式会社 | Semiconductor device |
| CN106411136A (en) * | 2016-08-25 | 2017-02-15 | 浙江大学 | High-voltage capacitance coupling based control chip of isolated type power converter |
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