RU2790616C1 - Fast buffer ab class amplifier - Google Patents

Abstract

FIELD: analog microelectronics.

SUBSTANCE: invention relates to the field of analog microelectronics and can be used as push-pull buffer amplifiers. The result is achieved by the fact that in the buffer amplifier the combined emitters of the first (3) and second (4) input transistors are connected to the combined emitters of the third (10) and fourth (11) input transistors through an additional correction capacitor (15), the emitter of the first (9) output transistor is connected to the output of the device (2) through the first (16) additional resistor, and the emitter of the second (14) output transistor is connected to the output of the device (2) through the second (17) additional resistor.

EFFECT: creation of a buffer amplifier with increased (by 1-2 orders of magnitude) values of the maximum increment rate of the output voltage at a low static current consumption not exceeding the static current consumption of the prototype buffer amplifier.

1 cl, 13 dwg

Description

The invention relates to the field of analog microelectronics and can be used as push-pull buffer amplifiers and output stages in various analog devices (operational amplifiers, communication line drivers, etc.).

In modern analog microcircuitry, class AB buffer amplifiers based on complementary n-p-n and p-n-p output transistors are widely used, in which a general negative feedback (OOS) is introduced to improve the linearity of the amplitude characteristic [1-10]. In practical circuits, the FOS is implemented on two input complementary differential stages of the dual-input-stage class [1-10].

The closest prototype of the proposed device is a buffer amplifier (Fig. 1), presented in US patent 6724260, fig. 12, 2004. Scheme of the CU prototype of Fig. 1 contains input 1 and output 2 of the device, the first 3 and second 4 input transistors, the common emitter circuit of which is connected through the first 5 reference current source with the first 6 power supply bus, the first 7 current mirror, matched with the second 8 power supply bus, the input of which connected to the collector of the first 3 input transistor, and the output is connected to the collector of the second 4 input transistor and the base of the first 9 output transistor, the base of the first 3 input transistor is connected to the input 1 of the device, and the base of the second 4 input transistor is connected to the emitter of the first 9 output transistor and connected with the output of device 2, the third 10 and fourth 11 input transistors, the common emitter circuit of which is connected through the second 12 reference current source with the second 8 power supply bus, the second 13 current mirror, matched with the first 6 power supply bus, the input of which is connected to the collector of the third 10 input transistor, and the output is connected to the collector of the fourth 11 input the base of the second 14 output transistor, the base of the third 10 input transistor is connected to input 1 of the device, and the base of the fourth 11 input transistor is connected to the emitter of the second 14 output transistor and is connected to the output of device 2, and the collector of the first 9 output transistor is connected to the second 8 power supply bus, and the collector of the second 14 output transistor is connected to the first 6 power supply bus.

A significant drawback of the CU prototype is that it has a relatively small value of the maximum slew rate of the output voltage for large pulse changes in the input signal. This limits the scope of its application, does not allow the use of this circuit solution as output stages of high-speed op amps, communication line drivers, etc.

The main objective of the proposed invention is to create a buffer amplifier with increased (by 1-2 orders of magnitude) values of the maximum slew rate of the output voltage at low static current consumption, not exceeding the static current consumption of the CU prototype.

The problem is solved by the fact that in the buffer amplifier of Fig. 1, containing input 1 and output 2 of the device, the first 3 and second 4 input transistors, the common emitter circuit of which is connected through the first 5 reference current source with the first 6 power supply bus, the first 7 current mirror, matched with the second 8 power supply bus, input which is connected to the collector of the first 3 input transistor, and the output is connected to the collector of the second 4 input transistor and the base of the first 9 output transistor, the base of the first 3 input transistor is connected to the input 1 of the device, and the base of the second 4 input transistor is connected to the emitter of the first 9 output transistor and connected to the output of the device 2, the third 10 and fourth 11 input transistors, the common emitter circuit of which is connected through the second 12 reference current source with the second 8 power supply bus, the second 13 current mirror, matched with the first 6 power supply bus, the input of which is connected to the collector third 10 input transistor, and the output is connected to the collector of the fourth 11 input transistor and the base of the second 14 output transistor, the base of the third 10 input transistor is connected to the input 1 of the device, and the base of the fourth 11 input transistor is connected to the emitter of the second 14 output transistor and is connected to the output of the device 2, and the collector of the first 9 output transistor is connected to the second 8 bus power source, and the collector of the second 14 output transistor is connected to the first 6 power supply bus, new elements and connections are provided - the combined emitters of the first 3 and second 4 input transistors are connected to the combined emitters of the third 10 and fourth 11 input transistors through an additional corrective capacitor 15, the emitter the first 9 output transistor is connected to the output of the device 2 through the first 16 additional resistor, and the emitter of the second 14 output transistor is connected to the output of the device 2 through the second 17 additional resistor.

In the drawing of FIG. 1 shows a prototype buffer amplifier circuit according to US 6724260, fig. 12, 2004

In the drawing of FIG. 2 shows a diagram of the proposed buffer amplifier in accordance with the claims.

In the drawing of FIG. 3 shows a diagram for modeling the prototype CU of FIG. 1 in LTspice environment at t=27°C, +Vcc=-Vee=10 V, R _load =1 MΩ, I ₁ =I ₂ =200 μA. In this case, hereinafter, computer models of bipolar transistors of basic matrix crystals of Integral JSC (Minsk) were used.

In the drawing of FIG. 4 shows the transient response of the leading edge of the prototype CU of FIG. 3 in the LTspice environment.

In the drawing of FIG. 5 shows the transient response of the trailing edge of the prototype CU of FIG. 3 in the LTspice environment.

In the drawing of FIG. 6 in Table 1 shows the slew rates of the output voltage of the prototype VCU of FIG. 3 for leading and trailing edges.

In the drawing of FIG. 7 shows the amplitude response of the prototype CU of FIG. 3 in the LTspice environment.

In the drawing of FIG. 8 shows a diagram for modeling the proposed CU of FIG. 2 in LTspice environment at t=27°C, +Vcc=-Vee=10 V, R _load =1 MΩ, I ₁ =I ₂ =200 μA, R1=R2=88 Ω, C _k1 =0.

In the drawing of FIG. 9 shows the logarithmic frequency response (LAFC) of the voltage gain of the proposed fast VU of FIG. 8 in the LTspice environment.

In the drawing of FIG. 10 shows the amplitude characteristic of the proposed high-speed control unit of FIG. 8 in LTspice environment at Rload=1 kΩ/ 2 kΩ/ 10 kΩ/1 MΩ.

In the drawing of FIG. 11 shows the transient response of the leading edge of the proposed high-speed control unit of FIG. 8 in the LTspice environment at С _k1 =0÷5 pF.

In the drawing of FIG. 12 shows the transient response of the trailing edge of the proposed high-speed BU of Fig.8 in the LTspice environment at C _k1 =0÷5 pF.

In the drawing of FIG. 13 in table 2 shows the slew rates of the output voltage of the proposed control unit of FIG. 8 for leading and trailing edges.

The class AB fast buffer amplifier of FIG. 2 contains input 1 and output 2 of the device, the first 3 and second 4 input transistors, the common emitter circuit of which is connected through the first 5 reference current source with the first 6 power supply bus, the first 7 current mirror, matched with the second 8 power supply bus, the input of which connected to the collector of the first 3 input transistor, and the output is connected to the collector of the second 4 input transistor and the base of the first 9 output transistor, the base of the first 3 input transistor is connected to the input 1 of the device, and the base of the second 4 input transistor is connected to the emitter of the first 9 output transistor and connected with the output of the device 2, the third 10 and fourth 11 input transistors, the common emitter circuit of which is connected through the second 12 reference current source with the second 8 power supply bus, the second 13 current mirror, matched with the first 6 power supply bus, the input of which is connected to the collector of the third 10 input transistor, and the output is connected to the collector of the fourth 11 input the base of the second 14 output transistor, the base of the third 10 input transistor is connected to input 1 of the device, and the base of the fourth 11 input transistor is connected to the emitter of the second 14 output transistor and is connected to the output of device 2, and the collector of the first 9 output transistor is connected to the second 8 power supply bus, and the collector of the second 14 output transistor is connected to the first 6 power supply bus. The combined emitters of the first 3 and second 4 input transistors are connected to the combined emitters of the third 10 and fourth 11 input transistors through an additional correction capacitor 15, the emitter of the first 9 output transistor is connected to the output of the device 2 through the first 16 additional resistor, and the emitter of the second 14 output transistor is connected to output device 2 through the second 17 additional resistor. In the diagram of Fig. 2 resistor 18 models the properties of the load.

Consider first the operation of the CU prototype of FIG. 1.

имеет «пилообразную» форму с крутизнойWith a pulsed change in the input voltage of positive polarity, the first 3 input op-amp transistor in a circuit with 100% negative feedback (NFB) switches almost instantly and its emitter and collector currents become equal to the current of the first 5 reference current source I ₅ \u003d 2I ₀ , and the second 4 input the transistor is locked in the emitter circuit. As a consequence, the total capacitance C _Σ1 in the high-impedance node Σ ₁ is recharged by a relatively small current I ₅ =2I ₀ , and the voltage

has a "sawtooth" shape with a steepness

(1)

(1)

) передается (практически с единичным коэффициентом) через эмиттерный повторитель на первом 9 выходном транзисторе на выход 2 устройства. Поэтому максимальная скорость нарастания выходного напряжения БУ-прототипа также определяется формулой (1), из которой следует, что при фиксированных значениях

, которое определяется емкостью база-коллектор первого 9 выходного и первого 4 входного транзисторов, в схеме известного БУ для увеличения SR приходится существенно увеличивать ток I₅=2I₀. Это отрицательно сказывается на энергопотреблении БУ в статическом режиме. Об этом свидетельствуют графики переходных характеристик на чертежах фиг. 4 и фиг. 5, а также данные таблицы фиг. 6.As a consequence, the voltage in the high-impedance node Σ ₁ (

) is transmitted (almost with a unity coefficient) through the emitter follower on the first 9 output transistor to output 2 of the device. Therefore, the maximum slew rate of the output voltage of the CU prototype is also determined by formula (1), from which it follows that for fixed values

, which is determined by the capacitance of the base-collector of the first 9 output and first 4 input transistors, in the well-known BU circuit, to increase SR, it is necessary to significantly increase the current I ₅ =2I ₀ . This negatively affects the power consumption of the CU in static mode. This is evidenced by the graphs of transient responses in the drawings of FIG. 4 and FIG. 5 as well as the data in the table of FIG. 6.

The introduction of the first 16 and second 17 additional resistors allows, if necessary, to stabilize the static collector currents of the first 9 and second 14 output transistors and reduce their values from 2.9 mA to less than 100 μA. This is evidenced by a comparison of the static modes of the schemes BU in the drawings of Fig.3 and Fig.8.

The introduction of new elements and connections between them in accordance with the claims of the invention allows you to increase the maximum rate of increase in the output voltage of the control unit by 1-2 orders of magnitude without increasing its static current consumption.

Indeed, with a pulsed change in the input voltage of positive polarity u _in ^(+), the pulsed collector current of the first 3 input transistor is not limited to the level I ₅ \u003d 2I ₀ and is determined by the current i _c15 ⁽⁺⁾ through an additional corrective capacitor 15:

– производная напряжения на дополнительном корректирующем конденсаторе 15 на начальном этапе переходного процесса,Where

- the derivative of the voltage on the additional corrective capacitor 15 at the initial stage of the transient,

C ₁₅ - the capacity of the additional corrective capacitor 15.

As a result, the parasitic capacitance C _Σ1 in the high-impedance node Σ ₁ is recharged by a relatively large current i _c15 ⁽⁺⁾ , which significantly increases the maximum rate of voltage rise at the output 2 of the device. This is evidenced by the graphs of the transient process in the drawings of Fig. 11, as well as the data of table 2 in the drawing of FIG. 13, from which it follows that SR increases by 69 times.

With large negative pulse signals at input 1, similar results are obtained, which is reflected in the graphs of Fig. 12 and in table 2 in FIG. 13 - The maximum slew rate is improved by more than 65 times.

The amplitude characteristic of Fig. 10 of the proposed CU of FIG. 8 shows that the considered circuit provides satisfactory operation at relatively low-resistance load resistances (R _load = 1 kOhm).

Thus, the proposed buffer amplifier has significant advantages over the CU prototype in terms of speed.

REFERENCES

1. Patent US 6.724.260, fig. 12, 2004

2. Patent US 6.724.260 B2, fig. 12, 2004

3. Patent US 5.291.149, fig. 3, 1994

4. Patent US 6.268.769, fig. 3, 2001

5. Patent US 4.636.743, fig. 1, 1987

6. Patent US 4.783.637, fig. 1, 1988

7. Patent US 5.225.791, fig. 2, 1993

8. Patent US 5.512.859, fig. 1, 1996

9. Patent US 3.968.451, fig. 7, 1976

10. Patent SU 1220105, fig. 1, 1982

Claims (1)

Class AB high-speed buffer amplifier containing the input (1) and output (2) of the device, the first (3) and second (4) input transistors, the common emitter circuit of which is connected through the first (5) reference current source to the first (6) source bus power supply, the first (7) current mirror matched with the second (8) power supply bus, the input of which is connected to the collector of the first (3) input transistor, and the output is connected to the collector of the second (4) input transistor and the base of the first (9) output transistor , the base of the first (3) input transistor is connected to the input (1) of the device, and the base of the second (4) input transistor is connected to the emitter of the first (9) output transistor and is connected to the output of the device (2), the third (10) and fourth (11 ) input transistors, the common emitter circuit of which is connected through the second (12) reference current source with the second (8) power supply bus, the second (13) current mirror, matched with the first (6) power supply bus, the input of which is connected to the collector of the third (10) input transistor, and the output is connected to the collector of the fourth (11) input transistor and the base of the second (14) output transistor, the base of the third (10) input transistor is connected to the input (1) of the device, and the base of the fourth (11) input transistor is connected to the emitter of the second (14) output transistor and is connected to the output of the device (2), wherein the collector of the first (9) output transistor is connected to the second (8) power supply bus, and the collector of the second (14) output transistor is connected to the first (6 ) power supply bus, characterized in that the combined emitters of the first (3) and second (4) input transistors are connected to the combined emitters of the third (10) and fourth (11) input transistors through an additional correction capacitor (15), the emitter of the first (9) of the output transistor is connected to the output of the device (2) through the first (16) additional resistor, and the emitter of the second (14) output transistor is connected to the output of the device (2) through the second oh (17) additional resistor.

Images