RU2775857C1 - Apparatus and method for accurate measurement of the phase difference between signals using quadrature components (variants) - Google Patents

Abstract

FIELD: measuring.

SUBSTANCE: invention relates to systems for accurate measurement of the phase shift between signals, namely, to allocation of quadrature components for one of the compared signals, and can be used for highly accurate phase detection, including that in analogue systems, using a comparator to additionally convert analogue signal into digital signal. Claimed group of inventions comprises two variants of the apparatus, wherein each variant includes sampling apparatus, phase detectors, accumulators, a state counter, and a frequency phase locking system. Claimed methods involve measuring the phase difference between the second signal and the in-phase and quadrature components of the first signal in phase detectors on the exclusive-OR elements. The averaged signals at the outputs of phase detectors are subjected to mathematical processing in order to compensate for the imperfection of propagation of signals in the meter.

EFFECT: increase in the accuracy of measuring the phase difference between two signals while the complexity of the measuring apparatus is low.

12 cl, 6 dwg

Description

FIELD OF TECHNOLOGY

[0001] This technical solution relates to systems for accurately measuring the phase shift between signals, using the selection of quadrature components for one of the compared signals and can be used for high-precision phase detection, including in analog systems when using a comparator for additional conversion of an analog signal into a digital signal .

BACKGROUND OF THE INVENTION

[0002] A known device and method (US 2018/0224524, A1, G01S 7/02 (2006.01), G01S 7/28 (2006.01), Aug. 09, 2018) for estimating the phase difference between signals, which contains a controlled delay line, the device sampling, noise suppression block, correlation block, control and computing controller. The principle of operation of the device is based on the restructuring of the controlled delay line, the input of which is a reference frequency signal, and the output controls the device for sampling the measured signal. In the measurement process, only digital signals are used; if it is necessary to measure the phase difference of analog signals, they must be converted to digital form. To reduce the impact of noise and interference on the device for measuring the phase difference, a noise suppression block is used, which uses signal samples at several clock intervals.

[0003] The disadvantage of the method is the limitation of the accuracy of measuring the phase difference, which is determined by the minimum tuning step of the controlled delay line, as well as the sensitivity of the characteristics of the delay line to the effects of external excitation factors (temperature, supply voltage, etc.).

[0004] There is a method (RU 2645440, C1, G01R/00 (2006.01), 21.02.2018) for measuring the phase difference of two quasi-harmonic signals by measuring the amplitudes of three signals: two original signals, the phase shift of which is measured, and the third signal, generated as a sum two original signals. The calculation of the amplitude values of the three analyzed signals not distorted by noise is carried out by the analysis of rice data. The amplitudes of the three analyzed signals, "cleared" from the inevitable influence of Gaussian noise, form a triangle, which makes it possible to calculate the desired phase difference based on simple geometric considerations.

The phase difference is determined by the following relationship:

where: A ₁ , A ₂ - the amplitude of the original signals, and A ₃ - the amplitude of the total signal.

[0005] The disadvantage of the proposed method is the need to use analog signals to estimate the amplitudes, the complexity of the procedure for statistical estimation of signal amplitudes, the impossibility of using the method to estimate the phase difference of digital signals.

[0006] The closest in technical essence to the proposed one is a phase measurement system based on a synchronization device, a digital phase detector, a correlator, a polarity determination device, a computing module (J. Mitra, T. Nayak. An FPGA-Based Phase Measurement System // IEEE Transactions on Very Large Scale Integration (VLSI) Systems, October, 2017, PP.1-10.10.1109/TVLSI.2017.2758807). The determination of the phase difference of two digital signals with the same frequencies is based on their sampling using a reference digital signal with a frequency that is a multiple of the frequency of the signals, followed by digital phase detection on the XOR element and accumulation of the detection result in the correlator over the measurement time. Considering that the detector characteristic of the phase detector on the XOR element has a linear form, the phase difference of two digital signals with the same frequencies is determined by a linear dependence on the measurement result in accordance with the following formulas:

y[t]=x[t] ⊗ x[t+ΔϕT/360°],

Δϕ=90° × R,

where: x[t] is the original first digital signal, x[t+ΔϕT/360°] is the original second digital signal, phase-shifted by the measured value relative to the first digital signal, T is the period of the measured digital signals, y[t] is the signal at the output of the phase detector on the XOR element, Ts=T/D is the period of the reference digital signal used for digitization, the frequency of which has a multiplicity of D to the frequencies of the original signals, R is the ratio of the signals at the output of the correlators.

[0007] The disadvantage of the closest technical solution is the static error in measuring the phase difference, caused by the finite multiplicity of the sampling frequency of the reference signal and the frequency of the measured signals, the need to accurately measure the polarity of one of the measured signals to eliminate the uncertainty in measuring the phase difference in the entire range of possible values (0.360] degrees. The presence of even a small error in determining the polarity signal leads to significant phase measurement errors.

SUMMARY OF THE INVENTION

[0008] The claimed invention solves the existing technical problem, characterized by the shortcomings of the prior art solutions, by implementing a new method for measuring the phase difference between two digital signals.

[0009] The technical result consists in increasing the accuracy of measuring the phase difference between two signals, with a low complexity of the measuring device.

[0010] The claimed technical result is achieved using a device for measuring the phase difference between the input signals, which contains

a first sampling device configured to obtain from the first input signal x ₁ (t) a digital signal x ₁ [t] and transmit it to a digital phase-locked loop (DPLL);

a second sampling device configured to receive from the second input signal x ₂ (t) a digital signal x ₂ [k] and transmit it to the phase detectors;

и

разность фаз между которыми равна 90°, и передачи квадратурных сигналов в фазовые детекторы;DPLFC configured to generate a reference signal based on the first digital signal x ₁ [k], wherein the reference signal consists of two quadrature digital signals

and

the phase difference between which is equal to 90°, and the transmission of quadrature signals to the phase detectors;

и

и вторым цифровым сигналом х₂[k], получаемых на входы фазовых детекторов;phase detectors capable of generating I and Q signals proportional to the phase difference between quadrature digital signals

and

and the second digital signal x ₂ [k] received at the inputs of the phase detectors;

adders-accumulators Σ, configured to extract the constant component of the signals I and Q at the outputs of the phase detectors;

a counter of N states, configured to count the clock pulses for measuring the phases of the signals and reset after N clock cycles from its state to zero and issue a pulse to end the measurement;

a computing device configured to estimate the phase difference from the received values of the I and Q signals processed by the phase detectors.

[0011] In one of the particular examples of the implementation of the sampling device built on a chain of D-flip-flops.

[0012] In another particular implementation example, the computing device determines an estimate of the phase difference based on the results of the preliminary calibration of the device, compensation for the error in the formation of signal quadratures, and compensation for the influence of the duty cycle of the signal pulses x ₁ (t) and x ₂ (t) on the measurement result.

[0013] In another particular implementation example, the calculation of the phase difference of the signals is carried out taking into account the deviation of the detector characteristics of the phase detectors from the linear form in the areas of phase difference 0°, 90°, 180°, 270°.

[0014] In another particular implementation, the phase detectors are XOR elements.

[0015] The claimed technical result is also achieved using a device for measuring the phase difference between the input signals, which contains

и

разность фаз между которыми равна 90°, передаваемых на вход первому и второму устройству дискретизации;an analog phase-locked loop (ASPLL) configured to supply the first input signal x ₁ (t) to the input and form in-phase and quadrature signals based on it

and

the phase difference between which is equal to 90°, transmitted to the input of the first and second sampling device;

цифрового сигнала

и его передачи в фазовый детектор;first sampler capable of deriving from an in-phase signal

digital signal

and its transfer to the phase detector;

цифрового сигнала

и его передачи в фазовый детектор;a second sampler configured to derive from the quadrature signal

digital signal

and its transfer to the phase detector;

a third sampling device configured to receive from the second input signal x ₂ (t) a digital signal x ₂ [k] and transmit it to the phase detectors;

и

и вторым цифровым сигналом х₂[k], получаемых на входы фазовых детекторов;phase detectors capable of generating I and Q signals proportional to the phase difference between quadrature digital signals

and

and the second digital signal x ₂ [k] received at the inputs of the phase detectors;

adders-accumulators Σ, configured to extract the constant component of the signals I and Q at the outputs of the phase detectors;

a counter of N states, configured to count the clock pulses for measuring the phases of the signals and reset after N clock cycles from its state to zero and issue a pulse to end the measurement;

a computing device configured to estimate the phase difference from the received values of the I and Q signals processed by the phase detectors.

[0016] In one of the particular examples of the implementation of the sampling devices are built on a chain of D-flip-flops.

[0017] In another particular implementation example, the computing device determines the phase difference estimate based on the results of device pre-calibration, signal quadrature generation error compensation, and compensation for the influence of the duty cycle of the x ₁ (t) and x ₂ (t) signal pulses on the measurement result.

[0018] In another particular implementation example, the calculation of the phase difference of the signals is carried out taking into account the deviation of the detector characteristics of the phase detectors from the linear form in the phase difference regions of 0°, 90°, 180°, 270°.

[0019] In another particular implementation, the phase detectors are XOR elements.

[0020] The claimed technical result is also achieved by performing a method for measuring the phase difference between input signals using the device according to the first embodiment, and contains the steps at which:

receive from the first input signal x ₁ (t) the first digital signal x ₁ [t];

receive from the second input signal x ₂ (t) the second digital signal x ₂ [k];

и

разность фаз между которыми близка к 90°;form a reference signal based on the first digital signal x ₁ [k], and the reference signal consists of two quadrature digital signals

and

the phase difference between which is close to 90°;

и

и вторым цифровым сигналом x₂[k];generate I and Q signals proportional to the phase difference between quadrature digital signals

and

and the second digital signal x ₂ [k];

allocate the constant component of the signals I and Q;

the phase difference is estimated from the obtained values of the I and Q signals.

[0021] The claimed technical result is also achieved by performing a method for measuring the phase difference between input signals using a device according to the second embodiment, and contains the steps at which:

и

разность фаз между которыми близка к 90°;receive the first input signal x ₁ (t) and form on its basis in-phase and quadrature signals

and

the phase difference between which is close to 90°;

цифровой сигнал

obtained from common mode signal

digital signal

цифровой сигнал

obtained from quadrature signal

digital signal

receive the second input signal x ₂ (t) and form on its basis a digital signal x ₂ [k];

и

и цифровым сигналом х₂[k];generate I and Q signals proportional to the phase difference between quadrature digital signals

and

and digital signal x ₂ [k];

allocate the constant component of the signals I and Q;

the phase difference is estimated from the obtained values of the I and Q signals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1. Structural diagram of a device for accurate measurement of the phase difference using a digital phase-locked loop system.

[0023] FIG. 2. Diagram of signals at the inputs and outputs of the sampling system.

[0024] FIG. 3. Diagram of quadrature signals at the output of a digital phase locked loop system.

[0025] FIG. Fig. 4. Structural diagram of the device for accurate measurement of the phase difference using an analog phase-locked loop system.

[0026] FIG. 5. Results of preliminary calibration of the phase difference meter.

[0027] FIG. 6. Zoning of the detector characteristic of the phase difference meter in the calculation algorithm.

IMPLEMENTATION OF THE INVENTION

[0028] The present technical solution proposes a method, implemented using appropriate circuits and devices, to find the value of the phase difference between the input signals x ₁ (t) and x ₂ (t). The necessary conditions are the periodicity of signals with the same period, the presence of only one rising and falling edge of the signal within one period of the signals: transition non-negative signal - negative signal, negative signal - non-negative signal. The duty cycle of the signals x ₁ (t) and x ₂ (t) can be any and not necessarily the same. Implementation of the present solution involves two ways of implementation. In both implementations, an auxiliary periodic clock signal is used with a frequency ƒ _S , a multiple of the frequency of the measured signals ƒ:

m<n,

m<n,

where m and n are coprime numbers, with clock rates with the smallest n being most preferred.

[0029] In FIG. 1 shows a diagram of the first version of the device (10) for measuring the phase difference between the input signals and the method implemented using it. When performing the method using the device (10), it uses a digital phase-locked loop (DPLL).

[0030] The input signals x ₁ (t) and x ₂ (t), representing a periodic train of pulses, have the same frequency, but an unknown constant phase shift that you want to determine. No rigid restrictions are imposed on the duty cycle of the pulse train. The measured signals are sampled at a frequency ƒ _S that is a multiple of the repetition rates of the measured signals.

[0031] The signals x ₁ (t) and x ₂ (t) are applied to the first and second sampling devices (101, 102) built on the basis of a chain of D-flip-flops. The frequency sampling signal ƒ _S can be obtained, for example, by multiplying the frequency of one of the measured signals in an external analog phase-locked loop system or from the signal conditioning system x ₁ (t) and x ₂ (t), if it is located in close proximity to the meter. DPLL (103) can be implemented using various schemes, such as those given in [1]. The exact orthogonality condition is not imposed on the output signals of the DPLL (103). The non-orthogonality of the output signals leads to the introduction of a correction factor into the calibration procedure in the computer program (109).

[0032] A serial chain of D-flip-flops can reduce the influence of the metastability phenomenon on the measurement result. All subsequent signal processing is done digitally.

и

на выходе ЦСФАПЧ (103) используется сигнал x₁[k]. Тильда над обозначением сигналов означает оценку фазы исходного сигнала x₁[k], которая отличается от истинного значения на величину ошибки работы ЦСФАПЧ (103). ЦСФАПЧ (103) формирует на своем выходе два меандра со скважностью 2, фаза первого из которых повторяет фазу входного сигнала, а фаза второго сдвинута на 90° относительно фазы первого. Таким образом, в случае нулевой ошибки подстройки ЦСФАПЧ (103) квадратурные сигналы могут быть определены следующим образом:[0033] To measure the phase difference of two digital signals x ₁ [k], x ₂ [k], generated by sampling devices (102, 103), one of them is selected as a reference. In circuit (10) as a reference signal for the formation of quadrature signals

and

at the output of the DSPFL (103) the signal x ₁ [k] is used. The tilde above the signal designation means the estimate of the phase of the original signal x ₁ [k], which differs from the true value by the amount of the DPLL error (103). The DSLFC (103) generates at its output two meanders with a duty cycle of 2, the phase of the first of which repeats the phase of the input signal, and the phase of the second is shifted by 90° relative to the phase of the first. Thus, in the case of zero adjustment error of the DPLL (103), the quadrature signals can be defined as follows:

On FIG. 2 shows a diagram of the input and digitized signals.

[0034] To obtain a correct result of measuring the phase difference in the proposed device (10), it is necessary that the D-flip-flops have long setup and hold times.

представленные на Фиг. 3, далее подаются параллельно с сигналом x₂[k] на вход фазовых детекторов (104, 105), которые выполняются как элементы исключающее ИЛИ (XOR). На выходе фазовых детекторов (104, 105) формируется постоянная составляющая, пропорциональная разности фаз сигналов на входе. Для выделения постоянной составляющей сигналов I и Q на выходах фазовых детекторов (104, 105) используются сумматоры-накопители Σ (106, 107).[0035] Quadrature signals

shown in FIG. 3 are then fed in parallel with the signal x ₂ [k] to the input of the phase detectors (104, 105), which are performed as XOR elements. At the output of the phase detectors (104, 105), a constant component is formed, which is proportional to the phase difference of the signals at the input. To isolate the constant component of the I and Q signals at the outputs of the phase detectors (104, 105), adders-accumulators Σ (106, 107) are used.

[0036] The measurement cycle is N cycles of frequency ƒ _S . The start and end of the measurement cycle is determined by the N-state counter (108), which generates a reset signal when the maximum count is reached. The counter (108) provides for counting the clock pulses for measuring the phases of the signals and resetting after N clock cycles from its state to zero and issuing a pulse for the end of the measurement. The duration of the measurement cycle is N frequency periods ƒ _S . At the end of the measurement cycle, the outputs of the accumulator adders (106, 107) generate I and Q signals, the values of which are proportional to the correlation between the signal ^and the in-phase and quadrature components of the signal x ₁ [t].

[0037] The computing device (109) (microcontroller or microprocessor) receives the results of I and Q averaging of the signals x ₁ [k], x ₂ [k] at the outputs of the phase detectors (104, 105). The computing device (109) determines the estimate of the phase difference, taking into account the preliminary calibration of the device, compensation for the error in the formation of quadratures (inaccurate phase shift 90°), compensation for the influence of the duty cycle of the signal pulses x ₁ (t) and x ₁ (t) on the measurement result, calculation of the phase difference signals taking into account the deviation of the detector characteristics of the phase detectors (104, 105) from the linear form in the regions of phase difference (0° 90°, 180°, 270°) due to the phenomenon of the metastable state.

[0038] In FIG. 4 shows the second implementation of the device circuit (20) involves the use of an analog PLL (ASPLL) (201) for the formation of quadrature signals. At the output of the APLFC (201), the in-phase and quadrature components of the selected reference signal are formed (in this case, x ₁ [t]):

[0039] In this case, it is required to sample three signals: the in-phase and quadrature components of the first signal and the second signal. The need to sample an additional signal leads to the appearance of additional errors associated with different propagation paths of the in-phase and quadrature components. The advantage of this implementation is the ability to reduce the effect of noise on the measurement result, since in APLL (201) there are additional measures to increase the signal-to-noise ratio. The algorithm of operation of the digital part of this method of implementation is similar to how it is described for the previous method.

и

разность фаз между которыми равна 90°, которые передаются на вход первому и второму устройству дискретизации (202, 203).[0040] The APLFC (201) provides the ability to supply the first input signal x ₁ (t) to the input and form in-phase and quadrature signals based on it

and

the phase difference between which is equal to 90°, which are transmitted to the input of the first and second sampling devices (202, 203).

цифровой сигнал

для его последующей передачи в фазовый детектор (205). Второе устройство дискретизации (203) обеспечивает получение из квадратурного сигнала

цифровой сигнал

и его последующую передачу в фазовый детектор (206). Третье устройство (204) дискретизации обеспечивает получение из второго входного сигнала x₂(t) цифрового сигнала х₂[k] и его передачу в фазовые детекторы (205, 206).[0041] The first sampler (202) obtains from the in-phase signal

digital signal

for its subsequent transfer to the phase detector (205). The second sampler (203) obtains from the quadrature signal

digital signal

and its subsequent transfer to the phase detector (206). The third sampling device (204) provides a digital signal x ₂ [k] from the second input signal x ₂ (t) and its transmission to the phase detectors (205, 206).

и

и вторым цифровым сигналом х₂[k], получаемых на их входах.[0042] The phase detectors (205, 206) output I and Q signals proportional to the phase difference between quadrature digital signals

and

and the second digital signal x ₂ [k] received at their inputs.

[0043] Adders-accumulators Σ (207, 208) operate in the same way as in circuit (10), and provide the ability to extract the DC component of the I and Q signals at the outputs of the phase detectors (205, 206).

[0044] The counter of N states (209) counts the clock pulses for measuring the phases of the signals and resets after N clock cycles from its state to zero and outputs a measurement termination pulse.

[0045] The computing device (210) implements a computing algorithm for estimating the phase difference from the received values of the I and Q signals processed by the phase detectors (205, 206).

[0046] The computing device (109, 210) in each of the presented device diagrams (10, 20) implements the procedure for the final calculation of the measured phase difference. The determination of the phase difference is carried out according to a previously obtained calibration curve, which takes into account the non-ideality of obtaining the in-phase and quadrature components, signal delays in the measurement circuit, and transient characteristics of D-flip-flops. An example of a calibration curve is shown in Fig. 5.

[0047] As shown in FIG. 6, the computing device (109, 210) evaluates the phase difference from the received I and Q signals in accordance with a predetermined algorithm. On FIG. 6 thick lines correspond to the I and Q values for an ideal phase difference meter, thin lines correspond to the I and Q values of a real phase difference meter, dash-dotted lines indicate the boundaries of regions I, II, III, IV and V, in accordance with which the computing device calculates the phase difference .

[0048] When the values of I and Q fall into region I, the computing device (109, 210) makes an estimate of the phase difference as the arithmetic average of the phase difference estimates for the values of I and Q. When the values of I and Q fall into region II, III, IV or V the computing device (109, 210) determines the estimate of the phase difference through the approximation of the non-linear part of the pre-calibrated values.

[0049] The value of the phase difference (angle) is the value of the point on the calibration curve (I _cal , Q _cal ), at which the distance between the points (I, Q) and (I _cal , Q _cal ) will be minimal. The operation of calculating the phase difference from the obtained values of I and Q is performed in the device (109, 210).

[0050] The implementation of the model leads to an increase in the accuracy of measuring the phase difference of two signals, including analog harmonic signals when using comparators for their digitization, with the simplicity of digital implementation.

[0051] The proposed method, due to the use of two phase detectors in the circuits of devices (10, 20), eliminates the need to determine the polarity signal, and also improves the algorithm for calculating the phase difference, taking into account compensation. The implementation of the model leads to an increase in the accuracy of measuring the phase difference of two signals, including analog harmonic signals when using comparators for their digitization, with the simplicity of digital implementation.

[0052] In order to verify the proposed method for high-precision measurement of the phase difference, tests were carried out, the results of which are presented in FIG. 5. As an example, the test device was implemented according to the block diagram shown in FIG. 4. For a set of phase differences consisting of 280 different values, I and Q values were measured. and quadrature components, which is expressed in the transformation of a rectangle into a parallelogram.Tests have shown the efficiency of the proposed method for determining the phase difference.

[0053] The use of the results given in the present description will improve the accuracy of measuring the phase difference in synchronization systems, positioning, precise timing systems, high-precision measurement of the delay between signals.

Sources of information:

1. Roland E. Best. Phase-Locked Loops: Design, Simulation and Applications. - 6th. - McGraw-Hill Education, 2007.

Claims (40)

1. A device for measuring the phase difference between input signals, containing a first sampling device configured to obtain from the first input signal x ₁ (t) a digital signal x ₁ [t] and transmit it to a digital phase-locked loop (DPLL); a second sampling device configured to receive from the second input signal x ₂ (t) a digital signal x ₂ [k] and transmit it to the phase detectors; DPLFC configured to generate a reference signal based on the first digital signal x ₁ [k], wherein the reference signal consists of two quadrature digital signals

and

, the phase difference between which is equal to 90º, and the transmission of quadrature signals to phase detectors; phase detectors capable of generating I and Q signals proportional to the phase difference between quadrature digital signals

and

and the second digital signal x ₂ [k] received at the inputs of the phase detectors; adders-accumulators Σ, configured to extract the constant component of the signals I and Q at the outputs of the phase detectors; a counter of N states, configured to count the clock pulses for measuring the phases of the signals and reset after N clock cycles from its state to zero and issue a pulse to end the measurement; a computing device configured to estimate the phase difference from the received values of the I and Q signals processed by the phase detectors. 2. The device according to claim 1, in which the sampling devices are built on a chain of D-flip-flops. 3. The device according to claim 1, in which the computing device determines the estimate of the phase difference based on the preliminary calibration of the device, compensation for the error in the formation of signal quadratures, and compensation for the influence of the duty cycle of the signal pulses x ₁ ( t ) and x ₂ ( t ) on the measurement result. 4. The device according to claim 3, in which additionally the calculation of the phase difference of the signals is carried out taking into account the deviation of the detector characteristics of the phase detectors from the linear form in the areas of phase difference 0º, 90º, 180º, 270º. 5. The apparatus of claim 1, wherein the phase detectors are XOR elements. 6. A device for measuring the phase difference between input signals, containing an analog phase-locked loop (ASPLL) configured to supply the first input signal x ₁ (t) to the input and form in-phase and quadrature signals based on it

and

, the phase difference between which is equal to 90°, transmitted to the input of the first and second sampling devices; first sampler capable of deriving from an in-phase signal

digital signal

and its transfer to the phase detector; a second sampler configured to derive from the quadrature signal

digital signal

and its transfer to the phase detector; a third sampling device configured to receive from the second input signal x ₂ (t) a digital signal x ₂ [k] and transmit it to the phase detectors; phase detectors capable of generating I and Q signals proportional to the phase difference between quadrature digital signals

and

and the second digital signal x ₂ [k] received at the inputs of the phase detectors; adders-accumulators Σ, configured to extract the constant component of the signals I and Q at the outputs of the phase detectors; a counter of N states, configured to count the clock pulses for measuring the phases of the signals and reset after N clock cycles from its state to zero and issue a pulse to end the measurement; a computing device configured to estimate the phase difference from the received values of the I and Q signals processed by the phase detectors. 7. The device according to claim 6, in which the sampling devices are built on a chain of D-flip-flops. 8. The device according to claim 6, in which the computing device determines the estimate of the phase difference based on the preliminary calibration of the device, compensation for the error in the formation of signal quadratures, and compensation for the effect of the duty cycle of the signal pulses x ₁ ( t ) and x ₂ ( t ) on the measurement result. 9. The device according to claim 8, in which additionally the calculation of the phase difference of the signals is carried out taking into account the deviation of the detector characteristics of the phase detectors from the linear form in the areas of phase difference 0 º, 90 º, 180 º, 270 º. 10. The apparatus of claim 6 wherein the phase detectors are XOR elements. 11. Method for measuring the phase difference between the input signals using the device according to any one of paragraphs. 1-5, containing the steps in which: receive from the first input signal x ₁ (t) the first digital signal x ₁ [t]; receive from the second input signal x ₂ (t) the second digital signal x ₂ [k]; form a reference signal based on the first digital signal x ₁ [k], and the reference signal consists of two quadrature digital signals

and

, the phase difference between which is close to 90º; generate I and Q signals proportional to the phase difference between quadrature digital signals

and

and the second digital signal x ₂ [k]; allocate the constant component of the signals I and Q; the phase difference is estimated from the obtained values of the I and Q signals. 12. Method for measuring the phase difference between the input signals using the device according to any one of paragraphs. 6-10, containing the steps in which: receive the first input signal x ₁ (t) and form on its basis in-phase and quadrature signals

and

, the phase difference between which is close to 90°; obtained from common mode signal

digital signal

; obtained from quadrature signal

digital signal

; receive the second input signal x ₂ (t) and form on its basis a digital signal x ₂ [k]; generate I and Q signals proportional to the phase difference between quadrature digital signals

and

and digital signal x ₂ [k]; allocate the constant component of the signals I and Q; the phase difference is estimated from the obtained values of the I and Q signals.

Images