RU2775489C1 - Access blocks separator signaling method - Google Patents

Abstract

FIELD: data processing.

SUBSTANCE: invention relates to the field of data processing. Proposed method and apparatus includes computer program code configured to ensure that the processor or processors perform the following: receiving video data; defining an access block delimiter syntax in at least one network abstraction layer (NAL) block in said video data; determining whether the access unit separator syntax indicates a slice type value for said NAL unit; determining whether the access unit delimiter syntax in said NAL unit indicates a video coding level (VCL) value and/or an access unit sequence number value for the NAL unit; and signaling access unit boundary values ​​for the NAL unit according to whether the access unit delimiter syntax indicates at least one of a slice type value, a VCL value, and an access unit sequence number value.

EFFECT: improving the display of random access block information and improving the reliability of access block boundary detection.

20 cl, 15 dwg

Description

Cross-references to related applications

[1] This application cites the priority of U.S. Provisional Application No. 62/904361, filed September 23, 2019, and U.S. Patent Application No. 17/023711, filed September 17, 2020, both of which are incorporated herein in their entirety. by reference.

Prerequisites for the creation of the invention

1. Technical field

[2] The present invention aims to improve the indication of random access unit (AU) information and improve the reliability of access unit boundary detection.

2. Description of the prior art

[3] VCEG (Q6/16) and ISO/IEC MPEG (JTC 1/SC 29/WG 11) ITU-T published the H.265/HEVC (High Efficiency Video Coding) standard in 2013 (Version No. 1), in 2014 (Version #2), in 2015 (Version #3 and in 2016 (Version #4). In 2015, these two standardizing organizations formed a Joint Video Exploration Team (JVET) , whose mission was to explore the potential for developing new video coding standards beyond HEVC.In October 2017, they published a joint call for proposals (Call for Proposals, Cfp) with proposals for video compression that would surpass the capabilities of HEVC.By February 15, 2018, applications were submitted a total of 22 standard dynamic range (SDR) entries, 12 standard dynamic range (SDR) entries, and 12 360-degree video entries. 2018 all taken in response to CfP applications were evaluated during the 10th JVET / MPEG meeting. As a result of this meeting, JVET officially launched the next-generation video coding standardization process. The new standard was named Versatile Video Coding (VVC), and the JVET group was renamed the Joint Video Experts Group. The current version of the VTM standard (VVC Test Model, VVC Test Model) is VTM 6.

[4] It is still undetermined in the art whether access unit delimiters (AUD) need to be signaled to point to an access unit boundary, and therefore a solution is desirable that can address this lack of reliability in signaling, and consequently improve its reliability and efficiency.

The essence of the invention

[5] A method and apparatus is provided, including a memory configured to store computer program code and a processor or processors configured to access the computer program code and perform operations in accordance with instructions from the computer program code. The computer program code includes an acquisition code configured to cause said at least one processor to receive video data, a first determination code configured to cause said at least one processor to determine an access block delimiter syntax in at least one network abstraction layer block (network abstraction layer, NAL) in said video data, a second determination code configured to allow said at least one processor to determine whether said access block delimiter syntax indicates a slice type value for said NAL unit, a third determination code configured to provide determining by said at least one processor whether the access block separator syntax in said NAL unit indicates a video coding layer (VCL) value and/or an access unit sequence number assignment for said NAL unit, and a signal code lization, configured to signal, by said at least one processor, access unit boundary values for said NAL unit, according to whether the access unit delimiter syntax indicates at least one of the following: slice type value, VCL layer value or the value of the serial number of the access block.

[6] In accordance with embodiments of the present invention, the third determination code is further configured to allow said at least one processor to determine whether the access unit delimiter syntax in the NAL unit indicates a VCL value and/or an access unit sequence number value for said the NAL unit by determining if at least one of the VCL values is set to any of the following values: 0, 1, or 2.

[7] In accordance with exemplary embodiments of the present invention, the signaling code is further configured to cause said at least one processor to signal the access block boundary values for said NAL unit by signaling if it has been determined that the access block delimiter indicates that said at least one VCL is set to 0, at least one of the following: a coded slice of a retarded picture value, a coded slice of a step-wise temporal sub-layer access (STSA) picture value, a coded slice of a forward skipped value image with random access (Random Access Skipped Leading, RASL) and the encoded slice of the value of the advanced decoded image with random access (Random Access Decodable Leading, RADL).

[8] In accordance with exemplary embodiments of the present invention, the signaling code is further configured to cause said at least one processor to signal access boundary values for said NAL unit by signaling if it has been determined that the access unit separator indicates that said at least one VCL is set to 1, at least one of the following: an instantaneous decoder reference (IDR) image value encoded slice, a Clean Random Access (CRA) encoded image slice value, and an encoded slice image value gradual decoder update (gradual decoding reference, GDR).

[9] In accordance with exemplary embodiments of the present invention, the signaling code is further configured to cause said at least one processor to signal access boundary values for said NAL unit by signaling if it has been determined that the access unit separator indicates that said at least one VCL is set to 2, the plurality of VCL values for the plurality of coded picture slices in the access block.

[10] In accordance with embodiments of the present invention, the third determination code is further configured to allow said at least one processor to determine whether the access unit delimiter syntax in the NAL unit indicates a VCL value and/or an access unit sequence number value for said of the NAL unit by determining whether the access unit sequence number value for said NAL unit identifies an access unit.

[11] In accordance with embodiments of the present invention, the third determination code is further configured to allow said at least one processor to determine whether the access unit delimiter syntax in the NAL unit indicates a VCL value and/or an access unit sequence number value for said NAL unit by determining whether the value of the access unit sequence number lies in the range from 0 to 255.

[12] In accordance with embodiments of the present invention, the third determination code is further configured to allow said at least one processor to determine whether the syntax of the access unit delimiter in the NAL unit indicates a VCL value and/or an access unit sequence number value for said of the NAL unit by determining whether the access unit sequence number value for said NAL unit identifies said access unit among adjacent access units.

[13] In accordance with embodiments of the present invention, the second determination code is further configured to allow said at least one processor to determine whether the syntax of the access unit separator in the NAL unit indicates a slice type value for said NAL unit by determining whether the type value is set slice to any of the following values: 0, 1, or 2.

[14] In accordance with embodiments of the present invention, the second determination code is further configured to allow said at least one processor to determine whether the access block separator syntax in the NAL unit indicates a slice type value by determining the presence of an intra prediction slice and/or slice with external prediction.

Brief description of the drawings

[15] Additional features, essence and various advantages of the proposed invention can be understood in more detail with the help of the following detailed description and the attached drawings, where:

[16] in FIG. 1 is a simplified schematic diagram in accordance with embodiments of the present invention;

[17] in Fig. 2 is a schematic block diagram in accordance with embodiments of the present invention;

[18] in FIG. 3 is a schematic block diagram in accordance with embodiments of the present invention;

[19] in FIG. 4 is a schematic block diagram in accordance with embodiments of the present invention;

[20] Fig. 5 is a sketch illustration in accordance with embodiments of the present invention;

[21] Fig. 6 is a sketch illustration in accordance with embodiments of the present invention;

[22] Fig. 7 is a sketch illustration in accordance with embodiments of the present invention;

[23] Fig. 8 is a sketch illustration in accordance with embodiments of the present invention;

[24] Fig. 9A is a sketch illustration in accordance with embodiments of the present invention;

[25] Fig. 9B is a sketch illustration in accordance with embodiments of the present invention;

[26] in FIG. 10 is a simplified flowchart in accordance with embodiments of the present invention;

[27] in FIG. 11 shows a data structure in accordance with embodiments of the present invention;

[28] in FIG. 12A shows a simplified table in accordance with embodiments of the present invention;

[29] in FIG. 12B shows a simplified table in accordance with embodiments of the present invention;

[30] in FIG. 13 is a simplified flowchart in accordance with embodiments of the present invention;

[31] in FIG. 14 is a simplified flowchart in accordance with embodiments of the present invention;

[32] in FIG. 15 is a schematic diagram in accordance with embodiments of the present invention.

Detailed description of the invention

[33] The features of the present invention described below may be used singly or in various combinations, in any order. However, embodiments of the present invention may be implemented using data processing circuits (eg, one or more processors or one or more integrated circuits). In one example, one or more processors may execute a program stored on a computer-readable medium.

[34] FIG. 1 illustrates a simplified block diagram of a communications system 100 in accordance with one embodiment of the present invention. The communication system 100 may include at least two terminals 102 and 103 connected to each other by a network 105. In a unidirectional data transmission, the first terminal 103 may encode video data locally for transmission to the second terminal 102 over the network 105. The second terminal 102 may receive encoded video data from the first terminal from the network 105, decode the encoded data, and display the reconstructed video data. Unidirectional data transmission is widely used in media service applications and similar applications.

[35] FIG. 1 illustrates a second pair of terminals 101 and 104 configured to support bidirectional encoded video transmission, which may be required in video conferencing, for example. In bidirectional communication, both terminals 101 and 104 may encode locally captured video data for transmission to another terminal over network 105. Both terminals 101 and 104 may also receive encoded video data transmitted by the other terminal, may decode the encoded data, and display the reconstructed video data on a local display device. .

[36] In the example of FIG. 1, terminals 101, 102, 103, and 104 may be servers, personal computers, or smartphones, but the present invention is not limited thereto. Embodiments of the present invention may be applied to laptop computers, tablet computers, media players and/or dedicated video conferencing equipment. Network 105 may be any number of networks that transmit encoded video data between terminals 101, 102, 103, and 104, including, for example, wired and/or wireless networks. Communication network 105 may provide communication over circuit-switched and/or packet-switched links. Examples of such networks may be telecommunications networks, local area networks, wide area networks and/or the Internet. In the present description, the architecture and topology of the network 105 do not play any role in the operation of the proposed invention, unless explicitly indicated.

[37] FIG. 2 illustrates, as an example of the application of the present invention, the placement of a video encoder and decoder in a streaming environment. The proposed invention can be applied with equal efficiency in other areas where video is used, including, for example, videoconferencing, digital television, storage of compressed video on digital media, including CDs, DVDs, memory cards, and the like.

[38] The streaming system may include a capture subsystem 203, which may include a video source 201, such as a video camera, that generates a stream 213 of uncompressed samples. The sample stream 213, shown in bold to emphasize the larger amount of data compared to the encoded video streams, may be processed by the encoder 202 associated with the camera 201. The encoder 202 may include hardware, software, or a combination of both that allow aspects of the proposed invention to be implemented, in according to the following more detailed description. The encoded video stream 204, shown as a thin line to emphasize the smaller amount of data compared to the uncompressed video sample stream 202, may be stored on the streaming server 205 for later use. One or more streaming clients 121 and 207 may access the streaming server 205 to obtain copies 208 and 206 of the encoded video bitstream 204 . The client device 212 may include a video decoder 211 that decodes the received copy of the encoded video bitstream 208 and generates a video sample output stream 210 that can be displayed on a display 209 or other display device (not shown). In some streaming systems, video bitstreams 204, 206, and 208 may be encoded according to predetermined video coding/video compression standards. Examples of such standards have been mentioned below and will be discussed in more detail in the following description.

[39] FIG. 3 is an example of a functional block diagram of a video decoder 300 in accordance with one embodiment of the present invention.

[40] Receiver 302 may receive one or more encoded video sequences for decoding by decoder 300. In the same or alternative embodiment of the present invention, video sequences may be received in turn, with the decoding of each of the encoded video sequences independent of the decoding of the remaining video sequences. The encoded video sequence may be received from channel 301, which may be a hardware and/or software link to a storage device where the encoded video data is stored. The receiver 302 may receive encoded video data along with other data, such as encoded audio data and/or auxiliary data streams, which may be redirected to the respective elements using them (not shown). The receiver 302 may separate the encoded video sequence from the rest of the data. A buffer memory 303 may be installed between the receiver 302 and the entropy decoder/analyzer 304 (hereinafter referred to as the “analyzer”) to combat network jitter. transmission, the buffer 303 may not be used or may be small. In the case of non-guaranteed packet networks, such as the Internet, the buffer 303 is necessary, can be relatively large, and preferably still have an adaptive size.

[41] Video decoder 300 may include a parser 304 for recovering symbols 313 from an entropy coded video sequence. The types of these symbols may include, for example, information used to control the operation of the decoder 300, and possibly also information to control a display device, such as display 312, which may be associated with, but not an integral part of, the decoder. The control information for display devices may, for example, be in the form of Supplementary Enhancement Information (SEI) messages or Video Usability Information (VUI) parameter set fragments (not shown). The parser 304 may perform analysis/entropy decoding of the received encoded video sequence. The encoded video sequence may be encoded in accordance with some video coding technology or standard, and may follow principles well known to those skilled in the art, including variable length coding, Huffman coding, context-dependent or context-independent arithmetic coding, etc. P. The analyzer 304 may extract from the encoded video sequence a set of subgroup parameters for at least one subgroup of pixels in the video decoder based on at least one parameter corresponding to the group. Subgroups can include groups of pictures (Groups of Pictures, GOP), images, tiles, slices, macroblocks, code blocks (Coding Units, CU), blocks (blocks), transformation units (Transform Units, TU), prediction units (Prediction Units, PU) etc. The analyzer may also extract information such as transform coefficients, quantizer parameter values, motion vectors, and the like from the encoded video sequence.

[42] Parser 304 may perform entropy decoding/analysis operations on the video sequence received from buffer 303 and generate symbols 313. Parser 304 may receive encoded data and selectively decode some of the symbols 313. Also, parser 304 may determine whether some of the symbols 313 be passed to a motion compensated prediction block 306, a scaler/inverse transform block 305, an intra prediction block 307, or a loop filter 311.

[43] Different device blocks may be involved in symbol recovery 313, depending on the type of encoded video images or portions thereof (e.g., internally and externally predicted images, internally and externally predicted sample blocks), as well as other factors. are involved, and how, may be determined by the subgroup control information extracted from the encoded video sequence by the analyzer 304. For simplicity, the flow of such subgroup control information between the analyzer 304 and the plurality of device blocks described below is not shown in the figure.

[44] In addition to the functional blocks already mentioned, decoder 300 can be conceptually subdivided into a set of functional blocks described below. In commercial implementations, many of these blocks interact closely with each other and can be at least partially mutually integrated. However, for purposes of describing the present invention, the division into functional blocks described below is suitable.

[45] The first of these blocks may be the block 305 scaling/inverse transformation. The scaling/inverse transform unit 305 receives the quantized transform coefficients as well as control information, including information about which transform to use, sample block size, quantization factor, quantization scaling matrices, and the like, as symbols 313 from parser 304. It produces blocks of samples including sample values that can be entered into the aggregator 310.

[46] In some cases, the samples output from the scaler/demapper 305 may be of the type of intra-coded sample blocks; that is, blocks of samples that do not use prediction information from previously reconstructed images, but may use information from previously reconstructed portions of the current image. Such prediction information may be provided by the intra picture prediction block 307 . In some cases, the intra image prediction block 307 may generate blocks of samples of the same size and shape as the restored block of samples, using already restored information about its environment obtained from the current (partially restored) image in the current image memory 309. The aggregator 310 may, in some cases, add the prediction information generated by the intra prediction block 307 to the sample output provided by the scaling/inverse transform block 305 individually for each sample.

[47] In other cases, the samples at the output of the scaler/demapper 305 may refer to externally encoded blocks of samples, and potentially, blocks of samples with motion compensation. In such cases, motion compensation predictor 306 may access reference picture memory 308 and obtain samples used for prediction. After motion compensation, the received samples, in accordance with the symbols 321 related to this block of samples, can be added by the aggregator 355 to the output data of the scaling / inverse transform block 351 (in this case they are called difference samples or a difference signal), resulting in an output counting information. Reference picture memory addresses from which the motion-compensated predictor obtains predicted samples may be determined by the motion vectors available to the motion-compensated predictor in the form of symbols 313, which may have, for example, an X-component, a Y-component, and a reference component. Images. Motion compensation may also include interpolation of sample values obtained from the reference picture memory when motion vectors, motion vector prediction mechanisms, and the like having sub-pixel accuracy are applied.

[48] The samples output from the aggregator 310 may be processed using various loop filtering techniques in the loop filter block 311 . The video compression technologies may include in-loop filtering technologies that are controlled by parameters contained in the encoded video bitstream and provided to the loop filtering block 311 as symbols 313 from parser 304. parts of the encoded image or encoded video sequence, as well as from previously restored and loop-filtered sample values.

[49] The output of the loop filter block 311 may be a sample stream that is fed to the display device 312 and also stored in the reference picture memory 557 for use in future inter-picture prediction.

[50] Individual encoded pictures, after they have been completely reconstructed, can be used as references for future prediction. Once the encoded picture has been completely reconstructed, and if it has been determined to be a reference (eg, by parser 304), the current reference picture 309 may be placed in the reference picture buffer 308, and a new current picture memory may be allocated before the next encoded picture is recovered.

[51] Video decoder 300 may perform decoding operations in accordance with a predetermined video compression technology that may be documented in a standard such as ITU-T H.265 recommendation. The encoded video sequence may conform to the syntax given by the applicable video compression technology or standard in the sense that it conforms to the syntax given in the document or standard of the video compression technology, and in particular to the syntax of the specified profiles of the standard. However, in order to comply with some of the video compression technologies or standards, the complexity of the encoded video sequence must be within the limits determined by the level of video compression technology or standard. In some cases, the levels of the standard limit the maximum image size, the maximum frame rate, the maximum sampling rate (measured in millions of samples per second, for example), the maximum reference image size, and the like. Layer restrictions can in some cases be further limited by Hypothetical Reference Decoder (HRD) specifications and HRD buffer management metadata signaled in the encoded video sequence.

[52] In one embodiment of the present invention, the receiver 302 may receive additional (redundant) data along with the encoded video. This additional data may be an integral part of the encoded video sequence (or video sequences). The additional data may be used by video decoder 300 to correctly decode the data and/or to more accurately reconstruct the original video data. The additional data may take the form of, for example, refinement temporal and spatial levels, signal-to-noise ratio (SNR) enhancement level, redundant slices, redundant images, forward error correction codes, and the like.

[53] FIG. 4 shows a functional block diagram of a video encoder 400 in accordance with one embodiment of the present invention.

[54] The encoder 400 may receive video samples from a video source 401 (which is not part of the encoder) of the capturing video image for encoding by the encoder 400.

[55] The video source 401 may supply the source video sequence for encoding by the video encoder (303) in the form of a digital stream of video samples having any suitable bit depth (e.g., 8 bits, 10 bits, 12 bits, ...), any color space (e.g., BT. 601 Y CrCB, RGB, ...) and any suitable reporting structure (eg Y CrCb 4:2:0, Y CrCb 4:4:4). In a media service system, video source 401 may be a storage device that stores pre-prepared video. In a videoconferencing system, video source 401 may be a video camera that captures image information locally in the form of a video sequence. The video data may be in the form of multiple individual images that convey a sense of movement when viewed sequentially. The images themselves may be organized as a spatial array of pixels, where each pixel may include one or more samples, depending on the sample structure used, color space, and the like. Those skilled in the art should recognize the relationship between pixels and samples. Further in the present description will be considered readings.

[56] In accordance with one embodiment of the present invention, encoder 400 may encode and compress images of the source video sequence into encoded video sequence 410 in real time, or in accordance with other time constraints imposed by practical application. One function of controller 402 may be to provide a suitable code rate. The controller controls the rest of the functional blocks described below and is functionally linked to these blocks. This relationship is not shown in the drawing for simplicity. Parameters set by the controller may include parameters related to speed control (skipping images, quantizer, λ value for rate-distortion optimization methods, ...), image size, GOP arrangement, maximum motion vector search range, etc. . Other functions of controller 402 should be apparent to those skilled in the art as they may correspond to video encoder 400 optimized for a particular system design.

[57] Some of the video encoders operate in a configuration that is familiar to those skilled in the art called "coding loop". Extremely simplified, the coding loop may consist of an encoding subsystem in the encoder 402 (hereinafter "source encoder") responsible for generating symbols based on the input encoded pictures as well as reference pictures, and a (local) decoder 406 built into the encoder 400 and recovering the symbols. , producing sample data that would be identically generated by a (remote) decoder (because the compression of symbols into an encoded video bitstream is lossless compression in the video compression technologies of the present invention). This reconstructed sample stream is entered into the reference picture memory 405 . Since the decoding of a symbol stream results in the same bit-accurate results regardless of the decoder (local or remote), the contents of the reference picture buffer are also the same bit-accurate at the local encoder and the remote encoder. In other words, the prediction subsystem in the encoder "sees" as reference picture samples exactly the same sample values that the decoder "sees" using prediction in decoding. This fundamental principle of reference picture synchronism (and the resulting drift if synchronism cannot be achieved due to, for example, channel errors) should be well known to those skilled in the art.

[58] The operation of the "local" decoder 406 is essentially identical to the "remote" decoder 300, which has already been described in detail above in connection with FIG. 3. However, since the symbols are available, and the entropy encoder 408 and parser 304 can be losslessly encoded/decoded into the encoded video sequence, the entropy decoding subsystems of the decoder 300, including channel 301, may not be fully implemented in the local decoder 406. receiver 302, buffer 303 and analyzer 304.

[59] It can be seen here that any decoding technology other than analysis/entropy decoding available in a decoder must be present in a substantially identical functional form in a corresponding encoder. A description of the encoding technologies may be omitted as they may be the reverse of the decoding technologies described in detail. Only in some places a more detailed description is needed, and it will be given below.

[60] Among its operations, the source encoder 403 may perform motion compensation-based predictive coding in which input frames are predictively encoded based on one or more previously encoded frames of a video sequence that have been labeled "keyframes". Thus, the coding subsystem 407 encodes the differences between the pixel blocks in the input frame and the pixel blocks in the reference frame (or frames) that can be chosen as reference for predicting the input frame.

[61] The local video decoder 406 may decode the encoded video data of the frames marked as reference, depending on the symbols generated by the source encoder 403. The operations of the encoding subsystem 407 are preferably lossy data processing. When the encoded video data is decoded in a video decoder (not shown in FIG. 4), the reconstructed video sequence is typically a replica of the original video sequence with some errors. The local video decoder 406 exactly reproduces the decoding process that could be performed by a remote video decoder on the reference frames and places the recovered reference frames in the reference picture cache 405 . Thus, the encoder 400 can locally store copies of the reconstructed key frames whose content matches the reconstructed key frames received by the remote video decoder (in the absence of transmission errors).

[62] Predictor 404 may search for predictions for coding subsystem 407 . That is, for a new frame to be encoded, predictor 404 may search reference picture memory 405 to find sample data (as candidate pixel reference blocks) or metadata, such as reference picture motion vectors, block shapes, etc., that can serve as reference for new images. Predictor 404 can find suitable reference data for each individual block of pixels. In some cases, depending on the search results obtained by the predictor 404, the reference data for predicting the input image may be extracted from multiple reference pictures stored in the reference picture memory 405 .

[63] The controller 402 may control the encoding operations in the video encoder 403, including, for example, setting parameters and subgroup parameters used to encode video data.

[64] The output of all the functional blocks described above may be entropy encoded in an entropy encoder 408. The entropy encoder converts the symbols generated by the various functional blocks into an encoded video sequence by compressing these symbols, losslessly, in accordance with techniques known to those skilled in the art. techniques such as Huffman coding, variable length coding, arithmetic coding, and the like.

[65] The transmitter 409 may buffer the encoded video sequence (or video sequences) generated by the entropy encoder 408 to prepare it for transmission over the communication channel 411, which may be a hardware and/or software link to a storage device where the encoded video data is stored. The transmitter 409 may combine the encoded video data from the video encoder 403 with other transmitted data, such as encoded audio and/or ancillary data streams (their sources are not shown).

[66] The controller 402 may control the operation of the encoder 400. When encoding, the controller 405 may assign to each encoded picture some type of encoded picture, which may affect the encoding methods applied to it. For example, images can be assigned one of the frame types described below.

[67] An intra predictive picture (I-picture) may be an image that is encoded and decoded without using any other frames of the video sequence as a source for prediction. Some video codecs support various types of intrinsically predictive pictures, such as independent decoding update (IDR) pictures. Those skilled in the art should be aware of such I-image variants, as well as their properties and applicability.

[68] A predictive picture (P-picture) is an picture that can be encoded and decoded using intra or inter prediction using a maximum of one motion vector and a reference picture pointer to predict the sample values of each block of samples.

[69] A bi-directionally predictive picture (B-picture) is a picture that can be encoded and decoded using intra or inter prediction using a maximum of two motion vectors and reference picture pointers to predict the sample values of each block of samples. Similarly, in the case of multi-predicted images, more than two reference images and associated metadata may be used to reconstruct one block of samples.

[70] Source images are usually spatially partitioned into a plurality of sample blocks (eg, blocks of 4x4, 8x8, 4x8, or 16x16 samples each) and encoded block by block. Blocks of samples may be predictively encoded based on other (already encoded) blocks, depending on the coding types assigned to the images corresponding to these blocks. For example, blocks of samples in I-pictures may be encoded without prediction or predicted based on already coded blocks of the same picture ("spatial prediction" or "intra prediction"). Blocks of pixels in P-pictures may be encoded without prediction, with spatial prediction, or with temporal prediction based on a single previously encoded reference picture. Sample blocks in B-pictures may be encoded without prediction, with spatial prediction, or with temporal prediction based on one or two previously encoded reference pictures.

[71] Video encoder 400 may perform encoding operations in accordance with a predetermined video coding technology or standard, which may be documented in a standard, such as ITU-T H.265 recommendation. In operation, video encoder 400 may perform various compression operations, including predictive coding operations that exploit temporal and spatial redundancy in the input video sequence. The encoded video data may suitably follow the syntax given by the applied video coding technology or standard.

[72] In one embodiment of the present invention, the transmitter 409 may, in conjunction with the encoded video, transmit additional data. Source encoder 403 may provide data such as a fragment of an encoded video sequence. The additional data may include temporal, spatial, or SNR refinement data, redundant images or slices, supplemental refinement information (SEI) messages, or video usage information (VUI) parameter set fragments, and the like.

[73] FIG. 5 illustrates the intra prediction modes used in the HEVC and JEM standards. The number of intra prediction modes used to capture contour directions, which in natural video can have arbitrary directions, has been increased from 33 used in HEVC to 65. The additional direction modes in JEM compared to HEVC are indicated by dotted arrows in FIG. 1(b), while flat mode and DC mode remain unchanged. Increased direction density for intra prediction modes is available for blocks of any size, both for luminance and chrominance predictions. In accordance with the illustration of FIG. 5, the directional intra prediction modes shown by dotted arrows are associated with odd intra prediction mode sequence numbers and are referred to as odd intra prediction modes. The directional intra prediction modes shown by solid arrows are associated with even intra prediction mode sequence numbers. They are called even intra prediction modes. Herein, the directional intra prediction modes shown in FIG. 5 with both solid and dotted arrows, also referred to as angular modes.

[74] In the JEM standard, a total of 67 intra prediction modes are used for intra luminance prediction. To encode the intra prediction mode, a list of 6 elements, called the most probable mode (MPM) list, is formed based on the intra prediction modes of neighboring report blocks. If the intra prediction mode is not selected from the MPM list, a special flag is signaled that indicates whether the intra prediction mode belongs to the selected modes. In the JEM-3.0 standard, there are 16 favorite modes, chosen evenly, like every fourth corner mode. In the JVET-D0114 and JVET-G0060 standards, 16 secondary MRMs are formed instead of uniformly selected modes.

[75] FIG. 6 shows N reference rows used for directional intra prediction modes. There is block 611, segment A 601, segment B 602, segment C 603, segment D 604, segment E 605, segment F 606, first support row 610, second support row 609, third support row 608, and fourth support row 607.

[76] In both HEVC and JEM, as well as some other standards such as H.264/AVC, the reference samples used to predict the current block of samples are limited to the nearest reference line (row or column). In the multiple reference line intra prediction method, the number of candidate reference lines (rows or columns) is increased from one (i.e., nearest line) to N for directional intra prediction modes, where N is an integer greater than or equal to one. In FIG. 2, a 4×4 prediction unit (PU) is considered as an example to illustrate the principle of the multi-line directional intra prediction method. The directional intra prediction mode may randomly select one of the N reference rows to generate predictions. In other words, the prediction p(x, y) is generated based on the reference samples S1, S2, ..., and SN. A flag indicating which of the reference rows is selected for the directional intra prediction mode is signaled. If N is set to 1, the directional intra prediction method is identical to the traditional method used in JEM 2.0. In FIG. 6, reference lines 610, 609, 608, and 607 are composed of six segments 601, 602, 603, 604, 605, and 606, along with an upper left reference. In this document, the reference row is also referred to as the reference line. The coordinates of the top left pixel in the current block are (0,0), while the top left pixel in the 1st reference line has coordinates (-1,-1).

[77] In the JEM standard, prior to the described procedure for generating a sample's intra-prediction value, for a luminance component, samples adjacent to it are filtered. Filtering is determined by the given intra prediction mode and transform block size. If the intra prediction mode is DC mode, or if the transform block size is 4×4, adjacent samples are not filtered. If the distance between the predetermined intra prediction mode and the vertical mode (or horizontal mode) is greater than a predetermined threshold, the filtering procedure is activated. The filter [1, 2, 1] and bilinear filters are used to filter neighboring samples.

[78] The position dependent intra prediction combination (PDPC) method is an intra prediction method that combines unfiltered boundary reference samples and HEVC type prediction with boundary reference filtering. For each sample located at coordinates (x, y), the prediction pred[x][y] is calculated as follows:

where R _x , _-1 ,R _-1 , _y are unfiltered reference samples located above and to the left of the current sample (x, y), respectively, and R _{-1, -1} is the unfiltered reference sample located in the upper left corner of the current block of samples . Weights are calculated as follows:

[79] FIG. 7 shows a block diagram 700 in which the DC mode PDPC method determines the weights (wL, wT, wTL) for positions (0, 0) and (1, 0) within a single 4x4 sample block. If PDPC is applied in DC mode, planar, horizontal and vertical intra prediction modes, additional edge filters such as HEVC DC mode edge filter or horizontal or vertical mode edge filters are not required. In FIG. 7 shows the definition of the reference samples Rx _,-1 , R- _1,y, and R- _1,-1 for the PDPC method applied to the right-up diagonal mode. The count prediction pred(x', y') is at position (x', y') within the prediction block. The x-coordinate of the reference sample R _x,-1 is obtained as x=x'+y'+1, and the y-coordinate of the reference sample R _-1,y is similarly as y=x'+y'+1.

[80] FIG. 8 shows a block diagram 800 of Local Illumination Compensation (LIC) that is based on a linear brightness model using a scaling factor a and an offset b. It is enabled or disabled adaptively for each individual CU encoded in the inter prediction mode.

[81] When the LIC procedure is applied to a coding block, the least squares method is used to calculate the parameters a and b, using adjacent samples in the current coding block and their corresponding reference samples. In particular, in accordance with the illustration of FIG. 8 use a subsample (with 2:1 scaling) of adjacent samples of a given coding block and corresponding samples (pointed to by motion information of the current coding block or sub-coding block) in a reference picture. Luminance compensation parameters are calculated and applied for each prediction direction independently.

[82] When a coding block is encoded in merge mode, the _LIC flag is copied from neighboring blocks, similar to copying motion information in merge mode. Otherwise, the LIC flag is signaled to the coding unit to indicate that the LIC procedure should be applied.

[83] FIG. 9A illustrates intra prediction modes 900 in the HEVC standard. There are a total of 35 intra prediction modes in the HEVC standard, with mode 10 being a horizontal mode, mode 26 being a vertical mode, and modes 2, 18, and 34 being diagonal. The intra prediction modes are signaled using the three most likely modes (MPMs) and 32 remaining modes.

[84] In embodiments of the VVC standard, as illustrated in FIG. 9, there are a total of 87 intra prediction modes, with mode 18 being the horizontal mode, mode 50 being the vertical mode, and modes 2, 34, and 66 being the diagonal modes. Modes -1 ~ -10 and modes 67 ~ 76 are called Wide-Angle Intra Prediction (WAIP) modes.

[85] The prediction pred(x, y) of the sample at position (x, y) is found using the intra prediction mode (DC, flat, angular) and a linear combination of reference samples according to the PDPC expression:

where R _{x, -1} ,R _{-1, y} - reference samples located above and to the left of the current sample (x, y), respectively, and R _{-1, -1} denotes the reference sample located in the upper left corner of the current block of samples.

[86] For DC mode, the weights for the width x height block are calculated as follows:

и где wT весовойwhere

and where wT is the weight

coefficient for the reference located at the top of the reference line with the same horizontal coordinate, wL weight for the reference located at the left of the reference line with the same vertical coordinate, wTL - weight for the top left reference for the current block, nScale defines, how fast the weights decrease along the axis (wL decreases from left to right, wT decreases from top to bottom), i.e., the rate of decrease in weights, which in this circuit is equal to the x-axis (left to right) and the y-axis (top to bottom). The number 32 denotes the original weights for neighboring samples, while the original weights are also the top (left or left-top) coefficients assigned to the top left sample in the current coding block, and the weights for neighboring samples in the procedure must be less than or equal to this original weighting factor.

[87] In flat mode wTL=0 while in horizontal mode wTL=wT and in vertical mode wTL=wL. The weighting coefficients for PDPC can be calculated using only addition and shift operations. The value of pred(x,y) can be computed in one step using eq. one.

[88] The methods proposed here can be used both individually and in various combinations, in any order. However, all methods (or embodiments of the invention), encoder and decoder proposed in the embodiments of the present invention can be implemented using data processing circuits (for example, one or more processors or one or more integrated circuits). In one example, one or more processors may execute a program stored on a non-volatile computer-readable medium. In the description below, the term "block" can be understood as a prediction block, coding block, or coding block, CU.

[89] FIG. 10 shows a simplified flowchart 1000 in accordance with exemplary embodiments of the present invention. In step S10, an encoder, such as that described with encoder 400 in FIG. 4 receives input images, and in step S11 encodes these images, for example, by encoding, including the formation of NAL (Network Abstraction Layer) units, each of which contains a header and payload data. Some of the NAL units contain parameter sets and others contain encoded picture samples, wherein in these pictures the various units may refer to one or more of a plurality of slices or slice segments, which may or may not be dependent on each other. In step S12, the NAL unit bitstream is transmitted, alone or together with other data, over the network, for example, to a decoder, such as decoder 300 shown in FIG. 3.

[90] FIG. 13 shows a flowchart 1300 where, in step S30, similar to step S11 in FIG. 10 form an access block separator syntax, for example, in accordance with the illustration of FIG. 11. In step S31, with respect to the syntax structure 1101 pic_type, a determination is made whether this syntax structure is to be specified by determining whether the corresponding data is generated as a result of encoding or not, and if so, what value can be signaled with this syntactic structure 1101 pic_type. For example, it can be determined whether the pic_type syntax structure 1101, if present, indicates a value of 0, 1, or 2, as illustrated in FIG. 12, i.e. this means that one or more slice_type values may be present in the slices of the encoded picture in the access block that contains the access block delimiter, and may be set and signaled appropriately in step S34.

[91] In step S32 of FIG. 13, with respect to the rap_type syntax structure 1102, it is determined whether this syntax structure is to be specified by determining whether the corresponding data is generated as a result of encoding or not, and if so, what value can be signaled with this rap_type syntax structure 1102. For example, it can be determined whether the rap_type syntax structure 1102, if present, indicates a value of 0, 1, or 2, as illustrated in FIG. 12V, thereby possibly indicating a nuh_unit_type VCL value for all encoded slices may be present in the encoded picture slices in the access unit that contains the access unit separator, and may be appropriately set and signaled in step S34.

[92] In step S43 of FIG. 14, with respect to the au_order_cnt syntax structure 1103, a determination is made whether this syntax structure is to be specified by determining whether the corresponding data is generated as a result of encoding or not, and if so, what value can be signaled with this au_order_cnt syntax structure 1103 . For example, it can be determined whether the au_order_cnt syntax structure 1103, if present, points to an access unit sequence number value that identifies the corresponding access unit(s) among neighboring access units, and whether it lies in the range 0 to 255 inclusive , and such information can be appropriately set and signaled in step S34.

[93] In accordance with the embodiments of the present invention, steps S31, S32, and S33 may be performed sequentially or in parallel, in accordance with the illustration of FIG. 13, and depending on the results of determination in one or more of these steps, S31, S32 and S33, the information described above may be specified in step S34 and specified as part of one or more NAL access units, in connection with possible syntax elements of the syntax structure. 1100 the access_unit_delimiter_rbsp shown in FIG. eleven.

[94] Also, in FIG. 10, one or more of the NAL units may be encoded and received in step S13 with the data described in the example of FIG. 11 and other related drawings, so that the access block delimiter can point to various information described herein, and in step S13, these data are parsed and decoded, resulting in step S14, one or more output images are obtained in accordance with the present description.

[95] FIG. 11 shows a payload source byte sequence (RBSP) parsing table 1100 for an access block delimiter that is used to signal video frame start information, in accordance with embodiments of the present invention, and FIG. 12 shows a table 1200 illustrating slice_type values.

Декодеры, отвечающие вариантам осуществления настоящего изобретения, должны игнорировать зарезервированные значения pic_type.[96] The pic_type syntax structure 1101 indicates that the slice_type values for all coded picture slices in an access block that contains the access block delimiter NAL unit are members of the set listed in table 1100 for a given pic_type value. In bitstreams conforming to this version, the value of pic_type must be 0, 1, or 2. Consider table 1200 in FIG. 12. In accordance with the embodiments of the present invention, a pic_type value of 0 may indicate the presence, in the encoded image, of an I slice_type value (a slice with exclusively intra prediction), a pic_type value of 0 may indicate the presence, in an encoded image, of an I slice_type value (of a slice exclusively intra-predictive), a pic_type value of 1 may indicate the presence, in the encoded picture, of a slice_type value of P (inter-predicted slice based on a single I- or P-slice) and I, and a pic_type value of 2 may indicate the presence, in the encoded image, slice_type values B (inter-prediction slice based on two I- or P-slices) P, and I. The remaining pic_type values are reserved for future use.

Decoders in accordance with embodiments of the present invention must ignore reserved pic_type values.

[97] FIG. 14 shows a flowchart 1400 where, in step S40, similar to step S13 in FIG. 10 receive and parse the syntax of the access block separator, for example, in accordance with the illustration of FIG. 11. In step S41, with respect to the pic_type syntax structure 1101, a determination is made whether this syntax structure 1101 is present, and if so, what value can be signaled with this pic-type syntax structure 1101. For example, it can be determined whether the pic_type syntax structure 1101, if present, indicates a value of 0, 1, or 2, as illustrated in FIG. 12, i.e. this means that one or more slice_type values may be present in the slices of the encoded image in an access block that contains the access block delimiter.

[98] It is to be understood that a NAL unit, in accordance with embodiments of the present invention, may include encoded video data that contains bytes indicating the type of data in that NAL unit, as well as payload data, which may be generated by an encoder, encoder 400 described above. The video coding layer (VCL) NAL unit or units may contain an identifier referring to a Picture Parameter Set (PPS), such as referring to a Sequence Parameter Set (SPS), and may be transmitted as Parameter Sets in baseband and/or out of it, in different delivery schemes depending on the carrier channel.

[99] It should also be understood that an access unit may contain multiple NAL units, and the decoding of each access unit may result in a decoded image. In accordance with the foregoing description, access block delimiter prefixing may be provided, and the plurality of VCL NAL units in each access block may contain a primary encoded picture including slices or slice data pieces representing video samples.

[100] The rap_type syntax 1102 specifies that the nuh_unit_type VCL ("nuh" - NAL unit header, NAL unit header) values for all coded picture slices in an access unit that contains an access block delimiter NAL unit are members of the set listed in table 1200V for the given value of rap_type. In bitstreams according to embodiments of the present invention, the value of rap type must be 0, 1, or 2. Consider the 1200V table in FIG. 12 B. In accordance with embodiments of the present invention, a value of 0 rap type may indicate the presence, in the encoded image, of a nuh_layer_id value equal to any of the following: TRAIL_NUT (trailing NAL unit header (NUT)), STSA_NUT (NUT incremental temporal sublayer access (STSA)), RASL_NUT (NUT of skip ahead random access picture(s) (RASL)), RADL_NUT (NUT of decodable random access picture (RADL)), and a rap_type value of 1 may indicate the presence, in the encoded image, a nuh_layer_id value equal to any of the following: IDR_W_RADL (instantaneous decoder update (IDR) with RADL (leading pictures may be present)), IDR_N_LP (no leading pictures), CRA_NUT (Cure Random Access Point (CRA) NUT), GDR_NUT (NUT Gradual Decoder Update (GDR), and a rap_type value of 2 may indicate the presence, in the encoded picture, of any nuh_unit_type_values VCL values. The rest of the rap type values are reserved for future use by ITU-T ISO/IEC. Decoders complying with embodiments of the present invention should ignore reserved rap_type values. The rap_type value may determine whether the encoded pictures in the access block contain only NAL units that are not IRAP (Intra Prediction Random Access Point), only NAL_IRAP units, or both IRAP and non-IRAP NAL units. The rap type value can be used to indicate whether a random access point is present in the access block. In accordance with embodiments of the present invention, the following classes of pictures may be present in HEVC: IRAP pictures (which may belong to temporal sublayer 0 and be encoded without using the contents of other pictures as reference data), leading pictures (following the IRAP picture in decoding order, however, preceding in output order) and retarded images (following an IRAP image in both decoding order and output order).

[101] In step S42 in FIG. 14, with respect to the rap_type syntax structure 1102, a determination is made whether that syntax structure is present, and if so, what value can be signaled with that rap_type syntax structure 1102. For example, it can be determined whether the rap_type syntax structure 1102, if present, indicates a value of 0, 1, or 2, as illustrated in FIG. 12 V, thereby possibly indicating a nuh_unit_type VCL value for all encoded slices may be present in the encoded picture slices in the access block that contains the access block delimiter.

[102] In accordance with embodiments of the present invention, AUD signaling may be required to indicate an access block boundary. In AUD, the pic_type syntax element may be signaled to indicate which slice_type values are present in the coded picture slices in an access unit that contains the access unit delimiter NAL unit, where pic_type may be used to determine whether the access unit is dependent or independent of other access units. .

[103] In this case, the syntax structure 1103 au_order_cnt defines the value of the sequence number of the access unit, which identifies the corresponding access unit among neighboring access units. In accordance with the embodiments of the present invention, the value of au_order_cnt must be in the range from 0 to 255 inclusive. The access block sequence number value may be used to define the access block boundary, in particular when one or more AUDs are lost.

[104] At step S43 in FIG. 14, with respect to the au_order_cnt syntax structure 1103, a determination is made whether this syntax structure is present, and if so, what value can be signaled with this au_order_cnt syntax structure 1103. For example, it may be determined whether the au_order_cnt syntax structure 1103, if present, indicates an access unit sequence number value that identifies the corresponding access unit(s) among adjacent access units, and may range from 0 to 255 inclusive.

[105] In accordance with the embodiments of the present invention, steps S41, S42, and S43 may be performed sequentially or in parallel, in accordance with the illustration of FIG. 14, and depending on the results of determination in one or more of these steps, S41, S42, and S43, the above-described information may be set and signaled in step S44, in connection with the possible syntax elements of the access_unit_delimiter_rbsp syntax structure 1100 shown in FIG. eleven.

[106] In accordance with embodiments of the present invention, as already noted, there may be one or more hardware processors and computer components, such as buffers, arithmetic logic units, instructions in memory, which are configured to determine or store predetermined delta values (differences) for the various values described in this document.

[107] Accordingly, using the embodiments of the present invention discussed in this document, the above technical problems can be effectively solved, at least in part, using one or more of the proposed technical solutions. That is, in accordance with embodiments of the present invention, in order to solve one or more various technical problems, new technical aspects are described herein, in which, preferably, an access block delimiter (AUD) can be signaled to indicate which slice_type values are present in slices of encoded pictures in an access unit containing a NAL unit with an access unit delimiter. The pic_type structure can be used to determine whether an access block is independent or dependent on other access blocks. Also, it is claimed that the signaling of the mentioned new syntax elements allows to effectively point to random access blocks, and accordingly, allows to increase the reliability of the definition of access block boundaries, in accordance with the exemplary embodiments of the present invention, and therefore, allows to increase the accuracy and efficiency.

[108] The methods described above may be implemented in computer software using computer-readable instructions and physically stored on one or more computer-readable media, or using specially configured one or more hardware processors. For example, in FIG. 12 shows a computer system 1200 suitable for implementing some of the embodiments of the present invention.

[109] Computer software may be encoded using any suitable machine code or programming language that can be processed by assembly, compilation, linking, or similar mechanisms, resulting in a code that includes instructions executed directly or by interpretation, execution microcode, etc., computer central processing units (CPUs), graphics processors (Graphics Processing Units, GPU), etc.

[110] The instructions may be executed on computers, or computer components, of various types, including, for example, personal computers, tablet computers, servers, smartphones, gaming devices, IoT devices, and the like.

[111] The components of the computer system 1500 shown in FIG. 15 are provided by way of example only and are not intended to suggest any limitation on the scope or functionality of the computer software implementing the embodiments of the present invention. Likewise, the component configuration shown is also not to be interpreted as having any dependency or requirement associated with any component illustrated in the exemplary computer system 1500, or combination of such components.

[112] Computer system 1500 may include input devices from the user interface. Input devices in a user interface may respond to input from one or more users using, for example, tactile input (eg, keystrokes, swipe gestures, cyber glove movements), audio input (eg, voice, handclaps), visual input (for example, gestures), olfactory input (not shown in the drawing). User interface devices may also be used to capture media of various types, not necessarily associated with conscious input from a human, such as audio (eg, voice, music, environmental sounds), images (eg, scanned images, still images taken from a camera), video (eg 2D video, 3D video including stereoscopic video).

[113] User interface devices may include one or more of the following (the drawing shows only one device of each type): keyboard 150), mouse 1502, trackpad 1503, touch screen 1510, joystick 1505, microphone 1506, scanner 1508, camera 1507 .

[114] Computer system 1500 may also include user interface output devices. User interface output devices may affect the senses of one or more users, such as through tactile output, sound, light, and/or smell/taste. User interface output devices may include tactile output devices (eg, tactile feedback from the touch screen 1510 or joystick 1505, but tactile output devices that are not input devices may also be present). For example, such devices can be audio output devices (for example, 1509 speakers, headphones (not shown)), visual output devices (for example, 1510 screens, including CRT screens, LCD screens, plasma screens, OLED screens, such as touch and non-touch, with or without haptic feedback, some of the screens may be capable of displaying 2D visual information or more than 3D visual information by means such as stereographic output ; virtual reality glasses (not shown in the drawing), holographic displays, smoke machines, and printers (not shown in the drawing).

[115] The computer system 1500 may also include user-accessible storage devices and associated storage media, such as optical media including CD/DVD ROM/RW 1520, with CD/DVD media 1511 or the like, a flash drive 1522, removable hard drive or 1523 solid state drive, legacy magnetic media such as tapes or floppy disks (not shown), dedicated ROM/ASIC/PLD based devices such as dongles (not shown), and etc.

[116] Persons skilled in the art should understand that the term "computer-readable storage medium" as used in connection with the present invention does not include transmission media, carrier waves, or other energy dependent signals.

[117] Computer system 1500 may also have an interface 1599 with one or more communication networks 1598. Networks 1598 may be wireless, wired, or optical, for example. Networks 1598 may also be local, wide area, metro, vehicle or industrial, real-time, delay tolerant, and the like. Examples of networks 1598 include local area networks such as Ethernet, wireless LANs, cellular networks including GSM, 3G, 4G, 5G, LTE, etc., wired or wireless digital broadcast wide area networks including cable television, satellite television, and terrestrial networks. broadcasting, vehicle and industrial networks, including CANBus, etc. Some 1598 networks require external network interface adapters connected to general purpose data ports or peripheral buses (1550 and 1551) (for example, the USB ports of the 1500 computer system. Other networks can be integrated into the internal structure of the 1500 computer system by connecting to the system bus, as described below (for example, an Ethernet interface on a personal computer system, or a cellular network interface on a smartphone-based computer system. The use of any of these networks 1598 allows computer system 1500 to communicate with other entities. Such communication may be unidirectional, receive only (for example, TV broadcast), unidirectional, transmit only (for example, a CANbus network to some CANbus devices) or bidirectional, for example, to other computer systems using local area networks or wide area networks On any of the networks and network interfaces described above can be applied relevant protocols and protocol stacks.

[118] The user interface devices, user-accessible storage devices, and network interfaces described above may be connected to the basic internal structure 1540 of the computer system 1500.

[119] The basic internal structure 1540 may include one or more central processing units (Central Processing Units, CPU) 1541, graphics processors (Graphics Processing Units, GPU) 1542, specialized programmable data processing units in the form of electrically programmable gate arrays (Field Programmable Gate Areas , FPGA) 1543, hardware accelerators 1544 for certain tasks, etc. These devices, together with Read-only memory (ROM) 945 1545, Random Access Memory 1546, high capacity internal memory such as internal, non-user hard drives, SSD drives, and similar memory 1547 may be connected by system bus 1548. In some computer systems, system bus 1548 may be accessed in the form of one or more physical connectors, allowing the system to be expanded with additional CPUs, GPUs, and the like. Peripherals can be connected either directly to the 1548 core system bus or to the 1551 peripheral bus. Examples of peripheral bus architectures are PCI, USB, and the like.

[120] CPU 1541, GPU 1542, FPGA 1543, and accelerators 1544 may execute instructions that, collectively, may constitute the computer code described above. The computer code may be stored in ROM 1545 or RAM 1546. Temporary data may be stored in RAM 1546, while permanent data may be stored in large capacity internal memory 1547, for example. A high speed of storing data in and retrieving data from memory devices can be achieved by using a cache memory that can be closely associated with one or more CPU 1541, GPU 1542, mass memory 1547, ROM 1545, RAM 1546, etc. .

[121] Computer-readable storage media may store computer code for performing various computer-executable operations. Such media and computer code may be specially designed and manufactured for the purposes of the present invention, or may be widely available and known to those skilled in the art of computer software.

[122] As a non-limiting example, a computer system with architecture 1500, and in particular core structure 1540, can provide the desired functionality as a result of execution by a processor (or processors) (including CPUs, GPUs, FPGAs, accelerators, etc.) , software implemented on one or more tangible computer-readable storage media. Such computer-readable storage media can be media associated with mass storage devices described above that are available to users, or non-volatile storage devices in the base structure 1540, such as built-in mass storage device 1547 or ROM 1545. Software that implements various embodiments of the present invention may be stored in such devices and executed by the internal structure 1540 of the computer system. The computer-readable storage medium, depending on specific requirements, may include one or more storage devices or memory chips. The software may provide execution, by the underlying structure 1540, and in particular by its processors (including CPUs, GPUs, FPGAs, etc.), of the necessary procedures, or parts of the necessary procedures described in this document, including the creation of data structures, stored in RAM 1546 and modifying these data structures in accordance with procedures defined by the software. In addition or alternatively, the computer system may provide the desired functionality as a result of the operation of logic, hard-coded or otherwise embodied in an electrical circuit (for example, an accelerator 1544), which may work with or instead of software to perform the required procedures or parts. the required procedures described in this document. Reference to software, where appropriate, may imply such logic and vice versa. Reference to a computer-readable medium, where appropriate, may refer to an electrical circuit (eg, an integrated circuit) that stores executable software, an electrical circuit that implements executable logic, or both. All suitable combinations of hardware and software are within the scope of the present invention.

[123] Several embodiments of the present invention have been described herein, however, modifications, changes and equivalent substitutions are possible and fall within the scope of the present invention. Accordingly, it is to be understood that those skilled in the art are capable of creating a variety of systems and methods that, while not expressly described herein, accomplish the intent of the present invention and are therefore within its scope and spirit.

Claims (40)

1. A video encoding method performed by at least one processor and including: receiving video data; defining an access block delimiter syntax in at least one network abstraction layer (NAL) block of said video data; determining whether the access unit separator syntax indicates a slice type value for said NAL unit; determining whether an access block delimiter syntax in said NAL unit indicates at least one of a video coding level (VCL) value by means of a random access point (RAP) syntax; determining whether the access unit separator syntax in said NAL unit indicates an access unit sequence number value for said NAL unit associating an access unit among neighboring access units by a number indicated by said access unit sequence number value; and signaling access unit boundary values for said NAL unit according to whether the access unit delimiter syntax indicates at least one of a slice type value, a VCL value, and an access unit sequence number value. 2. The method of claim 1, wherein determining whether the access block separator syntax in the NAL unit indicates a VCL value and/or an access unit sequence number value for the NAL unit comprises determining whether at least one of the VCL values is set to any of the following values: 0, 1 or 2. 3. The method of claim 2, wherein signaling access block boundary values for the NAL unit includes, if it is determined that the access block separator indicates that said at least one VCL value is set to 0, signaling at least one of the following: : a coded delay picture value slice, a stepwise temporal sublayer access (STSA) coded picture value slice, a random access advance skip picture (RASL) coded value slice, and a random access advance decodable picture (RADL) coded value slice. 4. The method of claim 2, wherein signaling the access block boundary values for the NAL unit comprises, if it is determined that the access block separator indicates that said at least one VCL value is set to 1, signaling at least one of the following: : decoder instantaneous update (IDR) image value coded slice, pure random access (CRA) image value coded slice, and decoder gradual update (GDR) image value coded slice. 5. The method of claim 2, wherein signaling access block boundary values for the NAL unit includes, if it is determined that the access block delimiter indicates that at least one VCL value is set to 2, signaling a plurality of VCL values for a plurality of coded slices. images in the access block. 6. The method of claim 1, wherein determining whether the NAL unit access unit separator syntax indicates a VCL value and/or an access unit sequence number value for the NAL unit comprises determining whether the NAL unit sequence number value identifies an access unit. 7. The method of claim 6, wherein determining whether the access unit separator syntax in the NAL unit indicates a VCL value and/or an access unit sequence number value for the NAL unit comprises determining whether the access unit sequence number value lies in the range of 0 up to 225. 8. The method of claim 6, wherein determining whether the NAL unit access unit separator syntax indicates a VCL value and/or an access unit sequence number value for the NAL unit includes determining whether the access unit sequence number value for the NAL unit identifies access among neighboring access blocks. 9. The method of claim 1, wherein determining whether the access block separator syntax in the NAL unit indicates a slice type value for said NAL unit comprises determining whether the slice type value is set to any of the following values: 0, 1, or 2. 10. The method of claim 9, wherein determining whether the access block separator syntax indicates a slice type value also includes determining the presence of an intra-predictive slice and/or an inter-predictive slice. 11. Device for video encoding, including: at least one memory configured to store computer program code; at least one processor configured to access the computer program code and to perform operations according to the instructions of the computer program code, the computer program code including: an acquisition code configured to cause at least one processor to acquire video data; a first determination code configured to cause at least one processor to determine an access block delimiter syntax in at least one network abstraction layer (NAL) block of said video data; a second determination code configured to cause at least one processor to determine whether said access unit delimiter syntax indicates a slice type value for said NAL unit; a third determination code configured to cause at least one processor to determine whether an access block delimiter syntax in said NAL unit indicates at least one of a video coding level (VCL) value by means of a random access point (RAP) syntax; a fourth determination code configured to cause at least one processor to determine whether the access unit separator syntax in said NAL unit indicates an access unit sequence number value for said NAL unit associating an access unit among neighboring access units by a number indicated by said sequence value access block numbers; and a signaling code configured to cause at least one processor to signal access unit boundary values for said NAL unit according to whether the access unit delimiter syntax indicates at least one of a slice type value, a VCL value, and a unit sequence number value access. 12. The apparatus of claim 11, wherein the third determination code is further configured to cause the at least one processor to determine whether the access unit separator syntax in the NAL unit indicates a VCL value and/or an access unit sequence number value for the NAL unit, by determining if at least one of the VCL values is set to any of the following values: 0, 1, or 2. 13. The apparatus of claim 12, wherein the signaling code is further configured to cause at least one processor to signal access boundary values for a NAL unit if it has been determined that the access unit separator indicates that at least one VCL value set to 0 by signaling at least one of the following: a coded slice of a late picture value, a coded slice of a stepwise temporal sublayer access (STSA) picture value, a coded slice of a forward random access skip picture (RASL), and a coded slice of a forward decodable picture value. random access images (RADL). 14. The apparatus of claim 12, wherein the signaling code is further configured to cause at least one processor to signal access boundary values for a NAL unit if it is determined that the access unit delimiter indicates that said at least one VCL is set. equal to 1 by signaling at least one of the encoded instant decoder update (IDR) image value slice, the pure random access (CRA) encoded image value slice, and the decoder incremental update (GDR) image value encoded slice. 15. The apparatus of claim 12, wherein the signaling code is further configured to cause at least one processor to signal access boundary values for the NAL unit if it is determined that the access unit separator indicates that at least one VCL value is set. equal to 2 by signaling a plurality of VCL values for a plurality of coded picture slices in the access block. 16. The apparatus of claim 11, wherein the third determination code is further configured to cause at least one processor to determine whether the syntax of the access unit delimiter in the NAL unit indicates a VCL value and/or an access unit sequence number value for the NAL unit, by determining whether the access unit identifies an access unit sequence number value for the NAL unit. 17. The apparatus of claim 16, wherein the third determination code is further configured to cause at least one processor to determine whether the syntax of the access unit delimiter in the NAL unit indicates a VCL value and/or an access unit sequence number value for the NAL unit by determining whether the value of the access block sequence number lies in the range from 0 to 225. 18. The apparatus of claim 16, wherein the third determination code is further configured to cause the at least one processor to determine whether the access unit delimiter syntax in the NAL unit indicates a VCL value and/or an access unit sequence number value for the NAL unit by determining whether the access unit sequence number value for the NAL unit identifies said access unit among neighboring access units. 19. The apparatus of claim 11, wherein the second determination code is further configured to cause the at least one processor to determine whether the access unit delimiter syntax in the NAL unit indicates a slice type value for the NAL unit by determining whether the slice type value is set equal to any of the following values: 0, 1, or 2. 20. A computer-readable storage medium that stores a program that enables a computer to execute a method, including: receiving video data; defining an access block delimiter syntax in at least one network abstraction layer (NAL) block of said video data; determining whether the access unit separator syntax indicates a slice type value for said NAL unit; determining whether an access block delimiter syntax in said NAL unit indicates at least one of a video coding level (VCL) value by means of a random access point (RAP) syntax; determining whether the access unit separator syntax in said NAL unit indicates an access unit sequence number value for said NAL unit associating an access unit among neighboring access units by a number indicated by said access unit sequence number value; and signaling access unit boundary values for said NAL unit according to whether the access unit delimiter syntax indicates at least one of a slice type value, a VCL value, and an access unit sequence number value.

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