RU2812762C1 - Adaptive colour conversion alarms for cu level and tu level - Google Patents

Abstract

FIELD: video encoding and decoding.

SUBSTANCE: signalling a coding unit (CU) level enable flag and a transform unit (TU) level encoded luminance flag for an adaptive colour transform (ACT) encoded block. A method and device are provided for receiving video data, obtaining a CU, determining whether a CU flag is set to a predetermined flag state, determining whether a CU tree type is set to a predetermined tree type, determining whether an ACT flag should be signalled based on any from whether the CU flag is set to a predetermined flag state and whether the tree type of the CU is set to a predetermined tree type, and encoding video data based on whether the ACT flag is signalled.

EFFECT: increased efficiency of encoding.

12 cl, 15 dwg, 4 tbl

Description

CROSS REFERENCE TO RELATED APPLICATION

[1] This application claims priority to provisional application US 63/037,170, filed June 10, 2020, and US 17/319,328, filed May 13, 2021, which are hereby expressly incorporated by reference into this application in their entirety.

BACKGROUND OF THE ART

1. Field of technology to which the invention relates

[2] The present disclosure relates to the signaling of a coding unit (CU) level enable flag and a transform unit (TU) level coded luminance flag for an adaptive color transform (ACT) mode coded block.

2. Description of the state of the art

[3] ITU-T VCEG (Q6/16) and ISO/IEC MPEG (JTC 1/SC 29/WG 11) published the H.265/HEVC (High Efficiency Video Coding) standard in 2013 (version 1), 2014 . (version 2), 2015 (version 3), and 2016 (version 4). In 2015, these two standards organizations jointly formed JVET (Joint Video Exploration Team) to explore the potential of developing the next video encoding standard beyond HEVC. In October 2017, they launched a joint call for proposals for video compression with capabilities beyond HEVC (CfP). By February 15, 2018, a total of 22 CfP responses had been submitted for standard dynamic range (SDR), 12 CfP responses for high dynamic range (HDR), and 12 CfP responses for 360 degree video categories, respectively. In April 2018, all CfP responses received were evaluated at the 122nd MPEG/10th JVET meeting. As a result of this meeting, JVET officially launched the standardization process for next generation video encoding beyond HEVC. The new standard was called Versatile Video Coding (VVC), and JVET was renamed the Joint Video Expert Team.

[4] However, there are technical issues, for example, if the CU coded block does not have a coefficient, then ACT mode signaling may be redundant, or a CU with ACT mode must have one or more than one coefficients in the CU coded block. For an ACT-mode inter-unit, if cu_coded_flag must be 1 to represent that the CU has at least one coefficient in the conversion unit, then there is no corresponding constraint for the ACT-mode intra-CU, and only the ACT-mode intra-unit must be output equal to 1 if both encoded chroma channel TU flags are zero. In addition, cu_act_enabled_flag must be signaled twice based on a different prediction mode of the current CU. As such, technical solutions to such problems are described here, for example.

DISCLOSURE OF THE INVENTION

[5] According to exemplary embodiments, a method and apparatus are included, comprising a memory configured to store computer program code, and a processor or processors configured to access the computer program code and operate in accordance with instructions of the computer program code. The computer program code includes a first acquisition code configured to cause at least one processor to obtain video data, a second acquisition code configured to cause at least one processor to obtain a coding unit (CU) block of video data, a first determination code configured to cause at least one processor determines whether a flag of the CU is set to a predetermined flag state, a second determination code configured to cause the at least one processor to determine whether the tree type of the CU is set to a predetermined tree type, a third determination code configured to cause at least one processor determines whether to signal an adaptive color transform (ACT) flag based on any of whether the CU flag is set to a predetermined flag state and whether the CU tree type is set to a predetermined tree type, and an encoding code configured to cause the at least one processor to encode video data based on whether the ACT flag is signaled.

[6] According to an exemplary embodiment, determining whether the ACT flag should be signaled is based only on whether the CU flag is set to a predetermined flag state.

[7] According to an exemplary embodiment, determining whether the ACT flag should be signaled is based on both whether the CU flag is set to a predetermined flag state and whether the CU tree type is set to a predetermined tree type.

[8] According to an exemplary embodiment, the predefined tree type indicates a single tree type rather than a double tree type.

[9] According to an exemplary embodiment, determining whether the adaptive color transformation (ACT) flag should be signaled is performed regardless of whether the CU prediction mode is intra-mode.

[10] According to an exemplary embodiment, the computer program code further includes a fourth determination code configured to cause the at least one processor to determine whether both encoded transform unit (TU) flags are zero, and whether the CU is encoded in ACT mode.

[11] According to an exemplary embodiment, the encoded TU flags are chroma channel flags.

[12] According to an exemplary embodiment, the computer program code further comprises a fifth determination code configured to cause the at least one processor to determine whether a coded luminance flag TU should be output equal to 1 based on determining that both coded TU flags are zero and that the CU is coded in ACT mode.

[13] According to exemplary embodiments, determining that the encoded luminance flag TU should be output equal to 1 is performed regardless of whether the CU prediction mode is intra-mode.

[14] According to exemplary embodiments, encoding of video data is further based on determining whether the encoded luminance flag TU should be output equal to 1.

BRIEF DESCRIPTION OF THE DRAWINGS

[15] Additional features, spirit and various advantages of the disclosed subject matter will be better understood from the following detailed description and the accompanying drawings, in which the following are depicted.

[16] FIG. 1 is a simplified illustration of a schematic diagram in accordance with embodiments.

[17] FIG. 2 is a simplified illustration of a schematic diagram in accordance with embodiments.

[18] FIG. 3 is a simplified illustration of a schematic diagram in accordance with embodiments.

[19] FIG. 4 is a simplified illustration of a schematic diagram in accordance with embodiments.

[20] FIG. 5 is a simplified illustration of a diagram in accordance with embodiments.

[21] FIG. 6 is a simplified illustration of a diagram in accordance with embodiments.

[22] FIG. 7 is a simplified illustration of a diagram in accordance with embodiments.

[23] FIG. 8 is a simplified illustration of a diagram in accordance with embodiments.

[24] FIG. 9A is a simplified diagram illustration in accordance with embodiments.

[25] FIG. 9B is a simplified illustration of a diagram in accordance with embodiments.

[26] FIG. 10 is a simplified illustration of a block diagram in accordance with embodiments.

[27] FIG. 11 is a simplified illustration of a block diagram in accordance with embodiments.

[28] FIG. 12 is a simplified illustration of a block diagram in accordance with embodiments.

[29] FIG. 13 is a simplified diagram illustration in accordance with embodiments.

[30] FIG. 14 is a simplified diagram illustration in accordance with embodiments.

[31] FIG. 15 is a simplified illustration of a schematic diagram in accordance with embodiments.

IMPLEMENTATION OF THE INVENTION

[32] The proposed features discussed below can be used individually or combined in any order. In addition, embodiments may be implemented by processing circuits (eg, one or more processors or one or more integrated circuits). In one example, one or more processors executes a program that is stored on a non-transitory computer-readable medium.

[33] In FIG. 1 illustrates a simplified block diagram of a communication system (100) according to an embodiment of the present disclosure. Communications system 100 may include at least two terminals 102 and 103 interconnected via network 105. For unidirectional data transmission, first terminal 103 may encode video data at a local location for transmission to another terminal 102 via network 105. Second terminal 102 may receive encoded video data of another terminal from the network 105, decode the encoded data, and display the recovered video data. Unidirectional data transfer may be common in media serving applications and the like.

[34] In FIG. 1 shows a second pair of terminals 101 and 104 that provide support for bidirectional encoded video transmission, which may occur, for example, during video conferencing. For bidirectional data transmission, each terminal 101 and 104 may encode video data captured at a local location for transmission to another terminal via network 105. Each terminal 101 and 104 may also receive encoded video data transmitted by the other terminal, may decode the encoded data, and may display the reconstructed data. video data on the local display device.

[35] As shown in FIG. 1, terminals 101, 102, 103, and 104 may be depicted as servers, personal computers, and smartphones, but the principles of the present disclosure are not limited to these. Embodiments of the present invention find use in laptop computers, tablet computers, media players, and/or specialized videoconferencing equipment. Network 105 represents any number of networks that transmit encoded video data between terminals 101, 102, 103 and 104, including, for example, wired and/or wireless communication networks. Communications network 105 may communicate over circuit-switched and/or packet-switched channels. Representative networks include telecommunications networks, local area networks, wide area networks, and/or the Internet. For purposes of this discussion, the architecture and topology of network 105 may not be essential to the operation of the present disclosure unless explained below herein.

[36] In FIG. 2 illustrates, as an example of an application for the disclosed subject matter, the placement of a video encoder and a video decoder in a streaming environment. The disclosed subject matter may be equally applicable to other video-enabled applications including, for example, video conferencing, digital television, compressed video storage on digital media including CD, DVD, memory card, etc., and so on. .

[37] The streaming system 200 may include a capture subsystem 203, which may include a video source 201, such as a digital camera, producing, for example, a stream 213 of uncompressed video samples. This sample stream 213 may be allocated as a large amount of data relative to the encoded bit streams and may be processed by an encoder 202 coupled to camera 201. Encoder 202 may include hardware, software, or a combination thereof to enable or implement aspects of the disclosed subject matter of the invention, as described in more detail below. The encoded video bitstream 204, which can be allocated as a smaller amount of data compared to the sample stream, can be stored on the streaming server 205 for future use. One or more streaming clients 212 and 207 may access the streaming server 205 to retrieve copies 208 and 206 of the encoded video bitstream 204 . Client 212 may include a video decoder 211 that decodes an incoming copy of the encoded video bitstream 208 and produces an outgoing video sample stream 210 that can be displayed on a display 209 or other rendering device (not shown). In some streaming systems, video bitstreams 204, 206 and 208 may be encoded according to certain video encoding/compression standards. Examples of these standards are noted above and described below.

[38] FIG. 3 may be a functional block diagram of a video decoder 300 according to an embodiment of the present disclosure.

[39] Receiver 302 may receive one or more encoded video sequences to be decoded by decoder 300; in the same or another embodiment, one coded

video sequences at a time, where the decoding of each encoded video sequence is independent of other encoded video sequences. The encoded video sequence may be received from channel 301, which may be a hardware/software connection to a storage device in which the encoded video data is stored. Receiver 302 may receive encoded video data with other data, such as encoded audio data and/or ancillary data streams, which may be sent to their respective using entities (not shown). Receiver 302 may separate the encoded video sequence from other data. To combat network jitter, a buffer memory 303 may be connected between receiver 302 and entropy decoder/parser 304 (“parser”). When receiver 302 receives data from a storage/forwarding device with sufficient bandwidth and controllability or from an iso-synchronous network, the buffer 303 may not be needed or may be small. For use on best quality packet networks, such as the Internet, a buffer 303 may be required, which may be relatively large and may preferably be of an adaptive size.

[40] Video decoder 300 may include a parser 304 for recovering symbols 313 from the entropy encoded video sequence. Categories of these symbols include information used to control the operation of the decoder 300, and potentially information to control a visualization device, such as a display 312, that is not integral to the decoder, but may be connected to it. The control information for the rendering device(s) may be in the form of additional enhancement information (SEI messages) or video suitability information parameter set portions (not shown). Parser 304 may parse/entropy decode the received encoded video sequence. Encoding of the encoded video sequence may be performed in accordance with a video encoding technology or standard and may follow principles well known to those skilled in the art, including variable length encoding, Huffman encoding, arithmetic encoding with or without context sensitivity, and so on. Parser 304 may extract from the encoded video sequence a set of subgroup parameters for at least one of the subgroups of pixels in the video decoder based on at least one parameter corresponding to the group. Subgroups may include groups of pictures (GOPs), pictures, tiles, slices, macroblocks, coding units (CUs), blocks, transform units (TUs), prediction units (PUs), and so on. An entropy decoder/parser can also extract information from the encoded video sequence, such as transform coefficients, quantizer parameter values, motion vectors, and so on.

[41] Parser 304 may perform an entropy decoding/parsing operation on a video sequence received from buffer 303 so as to create symbols 313. Parser 304 may receive encoded data and selectively decode specific symbols 313. Additionally, parser 304 may determine whether specific symbols should 313 be provided to motion compensated prediction module 306, upscaling/demapping module 305, intraprediction module 307, or loop filter 311.

[42] Symbol recovery 313 may include a variety of different modules depending on the type of video image or portions thereof encoded (such as: inter- and intra-picture, inter- and intrablock) and other factors. Which modules are engaged and how can be controlled by subgroup control information parsed from the encoded video sequence by parser 304. The flow of such subgroup control information between parser 304 and the plurality of modules is not shown below for clarity.

[43] In addition to the functional modules already mentioned, the decoder 300 can be conceptually divided into a number of functional modules, as described below. In a practical implementation operating under commercial constraints, many of these modules interact closely with each other and can be at least partially integrated into each other. However, for purposes of describing the disclosed subject matter, it is appropriate to conceptually subdivide it into functional modules as follows.

[44] The first module is a scale/inverse module 305. The scaling/inverse transform module 305 receives the quantized transform factor, as well as control information, including which transform to use, block size, quantization factor, quantization scaling matrices, and so on, as symbol(s) 313 from parser 304. It may output blocks containing sample values that can be entered into the aggregator 310.

[45] In some cases, the output samples of the scaling/demapping module 305 may refer to an intra-coded block; that is, to a block that does not use prediction information from previously reconstructed images, but may use prediction information from previously reconstructed portions of the current image. Such prediction information may be provided by intra-frame prediction module 307. In some cases, intra-frame prediction module 307 generates a block of the same size and shape as the block being reconstructed using surrounding already reconstructed information extracted from the current (partially reconstructed) image 309. Aggregator 310 in some cases adds, for each sample, prediction information generated by the module 307 intraprediction, to the output sample information provided by the scaling/inverse transform module 305.

[46] In other cases, the output samples of the scaling/demapping module 305 may relate to an intercoded block and potentially a motion compensated block. In such a case, motion compensated prediction module 306 may access reference image memory 308 to retrieve samples used for prediction. After motion compensation of the selected samples in accordance with the symbols 313 associated with the block, these samples can be added by the aggregator 310 to the output of the scaler/inverter (here called residual samples or residual signal) to generate information about the output samples. The addresses in the reference picture memory from which the motion-compensated prediction module selects prediction samples may be controlled by motion vectors available to the motion-compensated prediction module in the form of symbols 313, which may have, for example, X, Y, and reference picture components. Motion compensation may also include interpolation of sample values retrieved from reference image memory, where precise subsample motion vectors, motion vector prediction mechanisms, and so on are used.

[47] The output samples of aggregator 310 may be subject to various loop filtering techniques in loop filter module 311. Video compression technologies may include intra-loop filtering technologies that are controlled by parameters included in the encoded video bitstream and provided to loop filtering module 311 as symbols 313 from parser 304, but may also respond to meta-information obtained during decoding of previous ones (in decoding order). ) parts of a coded image or coded video sequence, as well as respond to sample values previously restored and filtered through loop filtering.

[48] The output of loop filter module 311 may be a stream of samples, which may be output to renderer 312 and also stored in reference picture memory 557 for use in future inter-frame prediction.

[49] Certain encoded images, after complete reconstruction, can be used as reference images for future prediction. After a coded picture has been fully recovered and the coded picture has been identified as a reference picture (eg, by parser 304), the current reference picture 309 may become part of the reference picture buffer 308, and fresh current picture memory can be reallocated before the next coded picture can be restored.

[50] Video decoder 300 may perform decoding operations according to a predefined video compression technology, which may be documented in a standard such as ITU-T Recommendation H.265. The encoded video sequence may conform to the syntax specified by a video compression technology or standard in use, in the sense that it matches the syntax of the video compression technology or standard as specified in the video compression technology document or standard and, in particular, in its profiles document. It may also be necessary for compliance to ensure that the complexity of the encoded video sequence is within the boundaries defined by the technology level or video compression standard. In some cases, levels limit the maximum image size, the maximum frame rate, the maximum reconstruction sampling rate (measured, for example, in megasamples per second), the maximum reference image size, and so on. The limits set by the layers can in some cases be further limited by hypothetical reference decoder (HRD) specifications and HRD buffer management metadata signaled in the encoded video sequence.

[51] In an embodiment, receiver 302 may receive additional (redundant) coded video data. Additional data may be included as part of the encoded video sequence(s). The additional data may be used by video decoder 300 to correctly decode the data and/or to more accurately reconstruct the original video data. The additional data may be in the form of, for example, temporal, spatial or signal-to-noise ratio (SNR) enhancement layers, redundant slices, redundant images, forward error correction codes, and so on.

[52] FIG. 4 may be a functional block diagram of a video encoder 400 according to an embodiment of the present disclosure.

[53] Encoder 400 may receive video samples from video source 401 (which is not part of the encoder), which may capture video image(s) for encoding by encoder 400.

[54] Video source 401 may provide a source video sequence for encoding by encoder 303 in the form of a digital video sample stream, which may have any suitable bit depth (eg: 8 bits, 10 bits, 12 bits, ...), any color space (eg , VT.601 Y CrCB, RGB, ...) and any suitable reading structure (for example, Y CrCb 4:2:0, Y CrCb 4:4:4). In a multimedia serving system, video source 401 may be a storage device storing pre-prepared video. In a video conferencing system, video source 401 may be a camera that captures local image information as a video sequence. Video data may be provided as many individual images that, when viewed sequentially, convey motion. The images themselves can be organized as a spatial array of pixels, in which each pixel can contain one or more samples depending on the sampling structure used, color space, etc. One skilled in the art can readily understand the relationship between pixels and samples. The description below is oriented towards readings.

[55] In an embodiment, encoder 400 may encode and compress images of the original video sequence into encoded video sequence 410 in real time or with any other timing constraints as required by the application. Providing an appropriate encoding rate is one of the functions of the controller 402. The controller controls other functional modules, as described below, and is operatively coupled to these modules. The connection is not depicted for clarity. Parameters set by the controller may include parameters related to speed control (image skip, quantizer, lambda value of rate-distortion optimization methods, ...), image size, group of picture (GOP) layout, maximum motion vector search range, and so on . Other functions of controller 402 may be readily apparent to one skilled in the art as they may relate to video encoder 400 optimized for a particular system design.

[56] Some video encoders operate in what one skilled in the art would readily recognize as a "coding loop". As a simplified description, an encoding loop may consist of an encoding portion of an encoder 402 (hereinafter "source encoder") (responsible for generating symbols based on the input image to be encoded and the reference image(s)), and a (local) decoder 406, built into the encoder 400, which reconstructs the symbols to create sample data that the (remote) decoder can also create (since any compression between the symbols and the encoded video bitstream is lossless in the video compression technologies discussed in the disclosed subject matter). This reconstructed stream of samples is entered into reference image memory 405. Since decoding a symbol stream produces bit-accurate results regardless of the location of the decoder (locally or remotely), the contents of the reference picture buffer are also bit-accurate between the local encoder and the remote encoder. In other words, the prediction portion of the encoder "sees" as reference picture samples exactly the same sample values that the decoder would "see" using prediction during decoding. This fundamental principle of reference picture synchronicity (and the resulting drift if synchronicity cannot be maintained, for example due to channel errors) is well known to one skilled in the art.

[57] The operation of the "local" decoder 406 may be the same as that of the "remote" decoder 300, which has already been described in detail above with reference to FIG. 3. Briefly referring also to FIG. 4, however, since symbols are available and encoding and/or decoding of symbols into a coded video sequence by entropy encoder 408 and parser 304 can be lossless, the entropy decoding portions of decoder 300, including channel 301, receiver 302, buffer 303, and parser 304 cannot be are fully implemented in the local 406 decoder.

[58] At this point, the observation can be made that any decoding technology other than parsing/entropy decoding that is present in the decoder must also be present in substantially identical functional form in the corresponding encoder. The description of encoding technologies may be shortened because they are the inverse of the fully described decoding technologies. Only some areas require more detailed description, which is given below.

[59] As part of its operation, source encoder 403 may perform motion-compensated predictive encoding that predictively encodes the input frame with reference to one or more previously encoded frames from the video sequence that have been designated “reference frames.” Thus, encoding engine 407 encodes differences between blocks of pixels of the input frame and blocks of pixels of the reference frame(s) that can be selected as prediction reference(s) for the input frame.

[60] Local video decoder 406 may decode encoded frame video data, which may be referred to as reference frames, based on the symbols generated by source encoder 403. The operations of the encoding engine 407 may preferably be lossy processes. When the encoded video data can be decoded in a video decoder (not shown in FIG. 4), the reconstructed video sequence can usually be a copy of the original video sequence with some errors. Local video decoder 406 copies decoding processes that may be performed by the video decoder on reference frames and may cause the reconstructed reference frames to be stored in reference picture cache 405 . Thus, encoder 400 can locally store copies of reconstructed reference frames that have common content as reconstructed reference frames that will be received by the far-end video decoder (assuming no transmission errors).

[61] Predictor 404 may perform predictive searches for encoding engine 407. That is, for a new image to be encoded, predictor 404 may search reference picture memory 405 for sample data (as reference pixel block candidates) or certain metadata such as reference picture motion vectors, block shapes, and so on, which may serve as a suitable prediction standard for new images. Predictor 404 may operate on a block-by-pixel basis of samples to find appropriate prediction templates. In some cases, as determined by the search results obtained by the predictor 404, the input image may have prediction patterns taken from a plurality of reference images stored in the reference image memory 405.

[62] The controller 402 may control the encoding operations of the video encoder 403, including, for example, setting parameters and subgroup parameters used to encode video data.

[63] The output signals of all of the above functional modules may be entropy encoded in an entropy encoder 408. The entropy encoder translates the symbols generated by the various functional modules into an encoded video sequence by lossless symbol compression according to techniques known to those skilled in the art, such as, Huffman coding, variable length coding, arithmetic coding and so on.

[64] Transmitter 409 may buffer the encoded video sequence(s) generated by entropy encoder 408 to prepare it for transmission via communication link 411, which may be a hardware/software connection to a storage device that will store the encoded video data. Transmitter 409 may combine encoded video data from video encoder 403 with other data to be transmitted, such as encoded audio data and/or ancillary data streams (sources not shown).

[65] The controller 402 may control the operation of the encoder 400. During encoding, the controller 405 may assign each encoded image a specific encoded image type, which may affect the encoding techniques that can be applied to the corresponding image. For example, images can often be classified into one of the following frame types:

[66] An intra-picture (1-picture) may be one that can be encoded and decoded without using any other frame in the sequence as a prediction source. Some video codecs allow different types of intra-pictures, including, for example, pictures with independent decoder update. One skilled in the art is aware of these variants of I-images and their respective applications and features.

[67] A prediction picture (P-picture) may be one that can be encoded and decoded using intra-prediction or inter-prediction using at most one motion vector and a reference index to predict the sample values of each block.

[68] A bidirectional prediction picture (B picture) may be one that can be encoded and decoded using intra prediction or inter prediction using at most two motion vectors and reference indices to predict the sample values of each block. Likewise, multi-prediction images can use more than two reference images and associated metadata to reconstruct a single block.

[69] Source images can typically be spatially divided into multiple blocks of samples (eg, blocks of 4x4, 8x8, 4x8, or 16x16 samples each) and encoded on a block-by-block basis. Blocks may be predictively encoded with reference to other (already encoded) blocks, as determined by the encoding assignment applied to the corresponding block images. For example, I-picture blocks may be encoded without prediction, or they may be predictively encoded with reference to already encoded blocks of the same image (spatial prediction or intra-prediction). P-picture pixel blocks may be encoded without prediction, by spatial prediction, or by temporal prediction with reference to one previously encoded reference picture. Blocks of B pictures may be encoded without prediction, by spatial prediction, or by temporal prediction with reference to one or two previously encoded reference pictures.

[70] Video encoder 400 may perform encoding operations in accordance with a predefined video encoding technology or standard, such as ITU-T Recommendation H.265. In operation, video encoder 400 may perform various compression operations, including predictive encoding operations, that exploit temporal and spatial redundancy in the input video sequence. The encoded video data may therefore follow the syntax specified by the video encoding technology or standard being used.

[71] In an embodiment, transmitter 409 may transmit additional data with encoded video. Source encoder 403 may include such data as part of the encoded video sequence. The additional data may include temporal/spatial/SNR enhancement layers, other forms of redundant data such as redundant images and slices, additional enhancement information (SEI) messages, video suitability information (VUI) parameter set fragments, and so on.

[72] In FIG. Figure 5 shows the intra prediction modes used in HEVC and JEM. To capture arbitrary edge directions present in natural video, the number of directional intra-modes is increased from 33, as used in HEVC, to 65. Additional directional modes in JEM over HEVC are shown with dashed arrows in FIG. 1(b), and the planar mode and DC mode remain the same. These denser directional intraprediction modes apply to all block sizes and to both luma and chrominance intraprediction. As shown in FIG. 5, the directed intra prediction modes indicated by the dotted arrows, which are associated with the odd intra prediction mode index, are called odd intra prediction modes. Directed intraprediction modes, indicated by solid arrows, which are associated with the even intraprediction mode index are called even intraprediction modes. Herein, the directed intraprediction modes indicated by solid or dotted arrows in FIG. 5 are also called corner modes.

[73] JEM uses a total of 67 intraprediction modes for brightness intraprediction. To encode the intramode, a list of most probable modes (MPM) of size 6 is constructed based on the intramodes of neighboring blocks. If the intramode is not included in the MPM list, a flag is signaled indicating whether the intramode belongs to the selected modes. JEM-3.0 has 16 selectable modes, which are selected equally as every fourth corner mode. In JVET-D0114 and JVET-G0060, 16 secondary MRMs are obtained to replace uniformly selected modes.

[74] In FIG. Figure 6 shows the N reference tiers used for intradirectional modes. There is a block unit 611, segment A 601, segment B 602, segment C 603, segment D 604, segment E 605, segment F 606, first support tier 610, second support tier 609, third support tier 608 and fourth support tier 607.

[75] In both HEVC and JEM, as well as some other standards such as H.264/AVC, the reference samples used to predict the current block are limited to the nearest reference line (row or column). In the multi-reference line intra-prediction method, the number of candidate reference lines (row or columns) is increased from one (i.e., the closest) to N for intra-guided modes, where N is an integer greater than or equal to one. In fig. 2 uses a 4x4 prediction unit (PU) as an example to show the concept of a multi-reference line intra-prediction method. The intradirectional mode can randomly select one of the N reference tiers to generate predictors. In other words, the predictor p(x,y) is generated from one of the reference samples SI, S2,... and SN. A flag is signaled to indicate which reference tier is selected for intradirectional mode. If N is set to 1, the intra-prediction method is the same as the traditional method in JEM 2.0. As shown in FIG. 6, reference lines 610, 609, 608 and 607 consist of six segments 601, 602, 603, 604, 605 and 606 along with an upper left reference reference. In this document, the reference tier is also called the reference line. The coordinate of the top left pixel in the current block is (0,0), and the coordinate of the top left pixel in the 1st reference row is (-1, -1).

[76] In JEM, for the luminance component, neighboring samples used to generate intrapredictive samples are filtered before the generation process. Filtering is controlled by the specified intraprediction mode and transform block size. If the intraprediction mode is DC or the transform block size is 4x4, adjacent samples are not filtered. If the distance between the specified intra-prediction mode and the vertical mode (or horizontal mode) is greater than the specified threshold, the filtering process is activated. To filter neighboring samples, the [1, 2, 1] filter and bilinear filters are used.

[77] A position-dependent intraprediction combination (PDPC) method is an intraprediction method that causes a combination of unfiltered boundary reference samples and HEVC-style intraprediction with filtered boundary reference samples. Each prediction sample pred[x][y] located at (x, y) is calculated as follows:

where R _x-1 , R _-1,y represent the unfiltered reference samples located above and to the left of the current sample (x, y), respectively, and R _-1 , _-1 represents the unfiltered reference sample located in the upper left corner of the current block. The weights are calculated as follows:

[78] FIG. 7 illustrates a diagram 700 of DC mode PDPC weights (wL, wT, wTL) for positions (0, 0) and (1, 0) within one 4x4 block. When PDPC is applied to DC, planar, horizontal and vertical intra modes, no additional edge filters such as DC HEVC mode edge filter or horizontal/vertical mode edge filters are required. Fig. 7 illustrates the definition of reference samples Rx,-1, R-l,y and R-1,-1 for PDPC applied to the upper right diagonal mode. The prediction reference pred(x', y') is located at (x', y') in the prediction block. The x-coordinate of the reference reference Rx, -1 is given as: x=x'+y'+1, and the y-coordinate of the reference reference R-1, y is similarly determined by the expression: y=x'+y'+1.

[79] FIG. 8 illustrates a local illuminance compensation (LIC) chart 800 and is based on a linear model for illuminance changes using a scaling factor a and an offset b. And it is turned on or off adaptively for each inter-mode coded coding unit (CU).

[80] When LIC is applied to a CU, the least squares error method is used to obtain the parameters a and b using the neighboring samples of the current CU and their corresponding reference samples. More specifically, as shown in FIG. 8, subsampled (2:1 downsampled) adjacent CU samples and corresponding samples (identified by the motion information of the current CU or sub-CU) in the reference image are used. IC parameters are derived and applied for each prediction direction separately.

[81] When a CU is encoded with merge mode, the LIC flag is copied from neighboring blocks in a similar manner to copying motion information in merge mode; otherwise, the LIC flag is signaled to the CU to indicate whether LIC is applied or not.

[82] FIG. 9A illustrates intra prediction modes 900 used in HEVC. HEVC has a total of 35 intraprediction modes, including mode 10 horizontal mode, mode 26 vertical mode, and mode 2, mode 18 and mode 34 diagonal modes. The intraprediction modes are signaled by three most probable modes (MPMs) and 32 remaining modes.

[83] In FIG. 9B shows, in the VVC embodiments, that there are a total of 87 intraprediction modes, where mode 18 is a horizontal mode, mode 50 is a vertical mode, and mode 2, mode 34, and mode 66 are diagonal modes. Modes -1~-10 and modes 67~76 are called wide-angle intraprediction (WAIP) modes.

[84] The prediction sample (x, y) located at position (x, y) is predicted using the intra prediction mode (DC, planar, angular) and a linear combination of the reference samples according to the PDPC expression:

where Rx,-1, R-1,y represent the reference samples located above and to the left of the current sample (x, y), respectively, and R-1,-1 represents the reference sample located in the upper left corner of the current block.

[85] For DC mode, the weights are calculated as follows for a block with dimensions width and height:

with nScale=(log2 (width) - 2+log2 (height) - 2+2) >> 2, where wT denotes the weighting coefficient for the reference sample located in the reference row above with the same horizontal coordinate, wL denotes the weighting coefficient for the reference sample located in the left reference row with the same vertical coordinate, and wTL denotes the weight coefficient for the top left reference sample of the current block, nScale indicates how quickly the weight coefficients decrease along the axis (wL decreasing from left to right or wT decreasing from top to bottom), namely the rate of decrease of the weighting factor, and this is the same along the x-axis (from left to right) and y-axis (from top to bottom) in the current version. And 32 denotes the initial weights for neighboring samples, and the initial weight is also the top (left or top left) weights assigned to the top left sample in the current SV, and the weights of neighboring samples in the PDPC process must be equal to or less than this initial weight .

[86] For planar mode wTL=0, while for horizontal mode wTL=wT and for vertical mode wTL=wL. PDPC weights can only be calculated with addition and shift. The value of pred(x,y) can be calculated in one step using Equation 1.

[87] The methods proposed herein can be used individually or combined in any order. In addition, each of the encoder and decoder methods (or embodiments) may be implemented by processing circuits (eg, one or more processors or one or more integrated circuits). In one example, one or more processors executes a program that is stored on a non-transitory computer-readable medium. In the following, the term "block" can be interpreted as a prediction block, coding block or coding unit, that is, CU.

[88] FIG. 10 illustrates exemplary embodiments of the flow chart 1000 such that in step S100, data can be received such that in step S101 it can be determined whether to implement processing for a unit such as an encoding unit and/or a transformation unit. If yes, in step S102 it can be determined whether the coding unit includes intra-mode prediction. If yes, in step S103 it can be determined whether the coding unit includes a flag indicating whether ACT SPS is enabled, and if such flag has such an indication, in step S104 it can also be determined whether the tree type for the coding unit is type single tree or not. According to exemplary embodiments, sps_act_enabled_flag equal to 1 indicates that adaptive color mapping may be used, and cu_act_enabled_flag may be present in the encoding unit syntax; sps_act_enabled_flag equal to 0 may indicate that adaptive color mapping cannot be used, and cu_act_enabled_flag may not be present in the encoding unit syntax; and when sps_act_enabled_flag is not present, it may be output to 0.

[89] If it is determined in steps S102, S103 and S104 that the intramode, flag indicating that ACT SPS is enabled, and that the tree is a single tree type, then in step S105, the processing may set a flag indicating that ACT is enabled in this coding unit on step S105. In exemplary embodiments, a cu_act_enabled_flag equal to 1 may indicate that the remainders of the current unit are encoded in the YCgCo color space; cu_act_enabled_flag equal to 0 may indicate that the remainder of the current coding unit is encoded in the original color space; and when cu_act_enabled_flag is not present, it can be output as 0. Thus, based on this syntax, an interblock can be encoded in ACT mode if cu_coded_flag is equal to 1, which can be interpreted to mean that ACT mode can be enabled for the interblock if the current CU has more than one coefficient.

[90] The additional processing described herein may then be implemented in step S106, as well as looping back to step S101 described above. Alternatively, in step S102, if it is determined that the mode is not set for intra, and/or in step S103, if it is determined that the sps_act_enabled flag does not include such enabled indication, then in step S107 it can be determined whether there is an indication regarding prediction flag PLT, and if not, then in step S108, determining the value of general_merge_flag. If such values in S102, S107 and S108 are set as described below, the processing may set the cu_coded_flag in step S109, after which in step S110, or from steps S107 and S108 if such cu_coded_flag is currently set, in step S111 it can be determined whether the coding unit includes a flag indicating whether ACT SPS is enabled, and if there is such an indication in such a flag, in step S112, then it can be determined whether the intra mode is now indicated, and if not, processing can proceed to step S104, as mentioned above.

[91] FIG. 11 illustrates exemplary embodiments of the flow chart 1100 such that, in step S100, data may be received such that, in step S101, it can be determined whether to implement processing for the encoding unit and/or transformation unit. For example, regardless of whether in step S201 or in step S202, the current CU is in the intra prediction mode (S201) or not (S202), processing may continue in step S203 to determine when both TU coded chroma channel flags are zero. If so, in step S203, then using the illustrated Y', such determination in step S203 may be sufficient to proceed to step S204 to deduce that the encoded luminance flag TU should be output equal to 1, and therefore such derivation may be done regardless of whether the current prediction mode of the current CU block is MODE_INTRA or not. Moreover, in addition to such a positive determination, in step S203 it may also be that both encoded chrominance channel TU flags are zero, whether the current CU is also encoded in ACT mode, and if so, then it can proceed to step S204 rather than immediately after S203. However, in step S204 thereafter and with negative determinations in step S203, processing can continue as described in any of steps S100 and S106 as described above. In embodiments, for an ACT-enabled encoding block, tu_y_coded_flag may not be signaled in the bitstream and should be output equal to 1 when both TU coded chroma channel flags are zero. Moreover, the cu_act_enabled_flag signal may be signaled according to such exemplary embodiments without checking the prediction mode of the current CU (S201 and/or S202), so that in the embodiments, for example, for a coding unit, only two conditions, sps_act_enabled_flag and treeType are SINGLE_TREE. can be checked for cu_act_enabled_flag signaling, and therefore the advantage of avoiding conditional cu_act_enabled_flag signaling twice based on the prediction mode can be achieved, for example, as described below and also shown in FIG. 12.

[92] For embodiments with the tu_y_coded_flag of the current CU, which may be intentionally not signaled when the TU coded flags of both chrominance channels are 0 and the ACT flag is 1, see Table 1 where, among other things, ...CuPredMode[chType][ x0][y0]=MODE_INTRA "&& !cu_act_enabled_flag"… enabled with TU level signaling for ACT:

[93] According to embodiments with the cu_act_enabled_flag signaling state for the current CU, including sps_act_enabled_flag and tree type, only according to exemplary embodiments, as shown in Table 2 regarding the cuactenabledflag signaling in the CU layer for the ACT:

[94] For example, FIG. 12 illustrates exemplary embodiments of a flowchart 1200 such that in step S100, data can be received such that in step S301 it can be determined whether to implement processing for the encoding unit and/or the transformation unit. If so, in step S302 it can be determined whether the coding unit includes a flag indicating whether ACT SPS is enabled, and if such flag has such an indication in step S304, then it can also be determined whether the tree type for the coding unit is type of single tree. According to such exemplary embodiments, sps_act_enabled_flag equal to 1 indicates that adaptive color mapping may be used, and cu_act_enabled_flag may be present in the encoding unit syntax; sps_act_enabled_flag equal to 0 indicates that adaptive color mapping cannot be used, and cu_act_enabled_flag may not be present in the encoding unit syntax; and when sps_act_enabled_flag is not present, it may be output to 0.

[95] If it is determined in steps S302 and S304 that the flag indicates ACT SPS is enabled and that the tree is a single tree type, then in step S305 the processing may set a flag indicating that ACT is enabled in this encoding unit in step S305. In exemplary embodiments, a cu_act_enabled_flag equal to 1 may indicate that the remainders of the current coding unit are encoded in the YCgCo color space; cu_act_enabled_flag equal to 0 may indicate that the remainder of the current coding unit is encoded in the original color space; and when cu_act_enabled_flag is not present, it can be output as 0. Thus, based on this syntax, an interblock can be encoded in ACT mode if cu_coded_flag is equal to 1, which can be interpreted to mean that ACT mode can be enabled for the interblock if the current CU has more than one coefficient.

[96] The additional processing described herein may then be implemented in step S106, as well as looping back to step S301 described above. Alternatively, in step S302, if it is determined that the flag sps_act_enabled does not include such an enabled indication, then in step S307 it can be determined whether there is an indication related to the PLT prediction flag, and if not, in step S808 determining the value of the flag general_merge_flag. If such values are set in steps S302, S307 and S308 respectively, as shown in FIG. 8, the processing may set the cu_coded_flag described above in step S309.

[97] Accordingly, such embodiments solve various technical problems where, for example, if a coded block of a CU does not have any coefficient, the ACT mode no longer needs to be signaled, whereby, accordingly, a CU with an ACT mode must have one or more than one coefficient in the CU coded block, and for an interblock with ACT mode, cu_coded_flag must be 1 to represent that the CU has at least one coefficient in the transform unit, thereby solving the missing restrictions for intra-CU with ACT mode.

[98] Such functions are useful encoding tools, for example for RGB video. For example, see illustration 1300 in FIG. 13, which illustrates an encoding thread 1301 and a decoding thread 1302, wherein the intra-loop ACT adopted in a screen coding model (SCM) (e.g., HEVC screen content encoding extension software testing model) is illustrated, wherein the ACT is illustrated as operating in the residual domain, and A CU level flag may be signaled to indicate the use of color space conversion. Such color transformation used in SCM may be, according to exemplary embodiments, the following:

[99] Additionally, in illustration 1400 of FIG. 14 illustrates a decoding process according to exemplary embodiments with ACT such that, in view of the above-described embodiments and flowcharts, an ACT tool in HEVC is included in a VVC structure to improve video encoding efficiency, whereby decoding with ACT can be applied. As shown in FIG. 14, illustration 1400 shows that color space conversion can be performed in the residual domain, and in particular, an additional decoding module, namely inverse ACT, can be introduced, for example, after the inverse conversion, to convert the residues from the YCgCo domain back to the original domain . Accordingly, when viewing the above-described FIGS. 10-12 among other disclosures, advantages are achieved over functions in VVC when the maximum transform size is not less than the width or height of one coding unit (CU), one CU leaf node can also be used as a transform processing unit, and hence In the embodiments described herein, the ACT flag may be signaled for one CU to select a color space for encoding its remainders, and following such a HEVC ACT scheme, for an inter- and intra-block copy (IBC) CU, ACT may be turned on only when there is at least one non-zero coefficient in the CU, and for intra-CU ACT can only be turned on when the chrominance components select the same luma component intra prediction mode, i.e. DM mode, thereby preferably at least avoiding such unnecessary or otherwise redundant signaling according to exemplary embodiments.

[100] According to exemplary embodiments, the basic transformations used for color space transformations may relate to the following YCgCo forward and inverse color transformation matrices, as described below, where applicable. For example:

[101] Additionally, to compensate for the change in dynamic range of the residual signals before and after color conversion, QP adjustments such as (-5, -5, -3) can be applied to the transform residual signals. On the other hand, as shown in (1), forward and backward color conversion may be required to access the residues of all three components. Accordingly, embodiments of the present application include a technical enhancement to enable ACT to be disabled in the following scenarios where not all remnants of the three components are available. For example, as disclosed in FIG. 10-12 and in the description, there is a case of separate tree splitting, such that when a separate tree is applied, the luma and chrominance samples within the same CTU are separated by different structures, which may cause the CU only in the luma tree to contain a luma component, and the CU in the chroma tree contain only two chroma components, and there is also the case of intra subpartition prediction (ISP), in which the ISP subpartition can only be applied to luma, while the chrominance signals are encoded without division, and in such an ISP design, except for the last ISP subpartitions , other subsections contain only a luminance component according to embodiments.

[102] Accordingly, there may be such CU level signaling for the ACT, where signaling related to the CU level ACT may be enabled in accordance with encoding syntax tables such as the above tables and/or Table 3:

[103] In embodiments, sps_act_enabled_flag equal to 1 may indicate that adaptive color mapping may be used, and cu_act_enabled_flag may be present in the coding unit syntax; a sps_act_enabled_flag equal to 0 may indicate that adaptive color mapping cannot be used, and cu_act_enabled_flag may not be present in the encoding unit syntax; and when sps_act_enabled_flag is not present, it may be output equal to 0. In embodiments, a cu_act_enabled_flag equal to 1 may indicate that the remainder of the current encoding unit is encoded in the YCgCo color space; cu_act_enabled_flag equal to 0 may indicate that the remainder of the current coding unit is encoded in the original color space; and when cu_act_enabled_flag is missing, it may be output as 0. According to exemplary embodiments, based on the above syntax, an interblock may be encoded in ACT mode if cu_coded_flag is 1, and thus, ACT mode may be enabled for the interblock in such a case, as if there is more than one coefficient in the current CU.

[104] In addition, a syntax may be included with respect to signaling a coded TU level luminance level flag for an ACT block, such as a coded TU flag for three color channels, according to the following conversion unit syntax table, Table 4:

[105] According to exemplary embodiments, the coded flag TU of the semantics associated with the luma component may also be shown as follows: tu_y_coded_flag [x0] [y0] equal to 1 may indicate that the luma transform block contains one or more levels of transform coefficients , not equal to 0, and the array indices x0, y0 can indicate the location (x0, y0) of the top left luminance sample of the transform block in question relative to the top left luminance sample of the image, and when tu_y_coded_flag [x0] [y0] is missing, its value can be inferred as follows way: if cu_sbt_flag is equal to 1 and one of the following conditions (a), (b) is true, tu_y_coded_flag [x0] [y0] is output equal to 0 (a) subTuIndex is equal to 0 and cu_sbt_pos_flag can be equal to 1, (b) subTuIndex can be equal to 1 and cu_sbt_pos_flag may be equal to 0, otherwise, if treeType is equal to DUAL_TREE_CHROMA, tu_y_coded_flag0 [x0] may be output equal to 0, and furthermore, otherwise, tu_y_coded_flag [x0] [y0] may be output equal to 1. In such syntax and associated semantics, there may be no ACT block state check for the encoded TU flag.

[106] Additionally, for an example TU_coded_flag block ACT, the TU coded flag for the luminance component can be described as follows:

[107] Accordingly, the encoded luma TU flag can be output to be 1 when the encoded TU flag of the chrominance channels is zero and the current CU is an intrablock and is encoded with the ACT mode.

[108] As described herein, there may be one or more processor and computer hardware components, such as buffers, arithmetic logic units, memory instructions, configured to determine or store predefined delta values (differences) between the values described herein , according to exemplary embodiments.

[109] Accordingly, by using the exemplary embodiments described herein, the above technical problems can be successfully solved by one or more of these technical solutions. That is, according to embodiments, to solve one or more different technical problems, this disclosure describes new technical aspects in which an access unit delimiter (AUD) may advantageously be signaled to indicate which slice_type values are present in slices of encoded pictures in an access unit. containing the access unit separator NAL unit. Pic_type can be used to determine whether the AU is independent or dependent on an external AU. It is further stated that such novel syntax element signaling is advantageous for random access AU indication and AU boundary detection robustness, respectively, according to exemplary embodiments, and is therefore advantageous, for example, for improving accuracy and efficiency.

[110] The methods described above may be implemented in computer software using computer readable instructions and physically stored on one or more computer readable media, or may be one or more hardware processors specifically configured. For example, in FIG. 12 illustrates a computer system 1200 suitable for implementing certain embodiments of the disclosed subject matter.

[111] Computer software may be encoded using any suitable machine code or computer language that may be subject to assembly, compilation, linking, or similar mechanisms to create code containing instructions that can be executed directly or through interpretation, execution of microcode, and etc., computer central processing units (CPU), graphic processing units (GPU), etc.

[112] The instructions may be executed on various types of computers or components thereof, including, for example, personal computers, tablet computers, servers, smartphones, gaming devices, Internet of Things devices, and the like.

[113] The components shown in FIG. 15 for computer system 1500 are exemplary in nature and are not intended to suggest any limitations as to the scope of use or functionality of computer software implementing embodiments of the present invention. The configuration of components should also not be interpreted as having any dependency or requirement relating to any one or combination of components illustrated in the exemplary embodiment of computer system 1500.

[114] The computer system 1500 may include certain human-machine interface input devices. Such a human-machine interface input device may respond to input from one or more human users through, for example, tactile input (e.g., keystrokes, swipes, control glove movement), audio input (e.g., voice, hand clapping), visual input (for example: gestures), olfactory input (not shown). Human-machine interface devices can also be used to capture certain media not necessarily directly related to conscious human input, such as sound (e.g. speech, music, ambient sound), images (e.g. scanned images, photographic images captured from a camera for still images), video (e.g. 2D video, 3D video, including stereoscopic video).

[115] Human-machine interface input devices may include one or more of (only one of each illustrated): keyboard 1501, mouse 1502, trackpad 1503, touch screen 1510, joystick 1505, microphone 1506, scanner 1508, camera 1507 .

[116] The computer system 1500 may also include certain human-machine interface output devices. Such human-machine interface output devices may stimulate the senses of one or more human users through, for example, tactile output, sound, light, and smell/taste. Such human-machine interface output devices may include haptic output devices (e.g., haptic feedback from a touch screen 1510 or joystick 1505, but there may also be haptic feedback devices that do not serve as input devices), audio output devices (eg: speakers 1509, headphones (not shown)), display devices (eg, screens 1510, including CRT screens, LCD screens, plasma screens, OLED screens, each with or without touch screen input capabilities , each with or without haptic feedback capability—some of which may be capable of producing two-dimensional visual output or more than three-dimensional output through means such as stereographic output; virtual reality glasses (not shown), holographic displays, and smoke tanks (not shown)) and printers (not shown).

[117] Computer system 1500 may also include human accessible storage devices and associated media, such as optical media, including CD/DVD ROM/RW 1520 with CD/DVD or similar media 1521, flash drive 1522, removable 1523 hard drive or solid state drive, previously developed magnetic media such as tape and floppy disk (not shown), specialized ROM/ASIC/PLD based devices such as dongles (not shown), etc.

[118] Those skilled in the art will also understand that the term "machine readable medium" as used in connection with the subject matter disclosed herein does not cover transmission media, carrier waves, or other time signals.

[119] Computer system 1500 may also include an interface 1599 to one or more communications networks 1598. Networks 1598 may be wireless, wired, optical, for example. Additionally, 1598 networks can be LAN, WAN, metro, automotive, industrial, real-time, latency tolerant, etc. Examples of networks 1598 include local area networks such as Ethernet, wireless LANs, cellular networks including GSM, 3G, 4G, 5G, LTE, and the like, wired television or wireless wide area digital networks including cable television, satellite television, and terrestrial television broadcasting, automotive and industrial equipment, including CAN bus, etc. Some 1598 networks typically require external network interface adapters that are connected to certain general purpose data ports or peripheral buses (1550 and 1551) (for example, the USB ports of a 1500 computer system); others are typically integrated into the core of the computer system 1500 by connecting to a system bus, as described below (for example, an Ethernet interface to a PC computer system or a cellular network interface to a smartphone computer system). Using any of these networks 1598, the computer system 1500 can communicate with other entities. Such communication may be unidirectional, receive only (for example, broadcast television), unidirectional, send only (for example, CAN bus to certain CAN bus devices), or bidirectional, such as for other computer systems using a local or wide area digital network . Each of these networks and network interfaces may use specific protocols and protocol stacks, as described above.

[120] The aforementioned human-machine interface devices, human-accessible storage devices, and network interfaces may be attached to the core 1540 of the computer system 1500.

[121] Core 1540 may include one or more central processing units (CPUs) 1541, graphics processing units (GPUs) 1542, graphics adapters 1517, specialized programmable gate array processors (FPGAs) 1543, hardware accelerators 1544 for specific tasks, etc. These devices, along with read-only memory (ROM) 1545, random access memory 1546, internal storage devices such as internal hard drives not accessible to the user, solid-state drives, and the like. 1547 may be connected via the 1548 system bus. On some computer systems, the 1548 system bus may be available as one or more physical connectors to allow expansion with additional CPUs, GPUs, and the like. Peripherals can be connected either directly to the 1548 core system bus or via the 1551 peripheral bus. Architectures for the peripheral bus include PCI, USB, etc.

[122] The CPU 1541, GPU 1542, FPGA 1543, and accelerators 1544 may execute certain instructions that, in combination, may constitute the aforementioned computer code. This computer code may be stored in ROM 1545 or RAM 1546. Transient data may also be stored in RAM 1546, while persistent data may be stored in, for example, internal mass storage 1547. Rapid storage and retrieval to either storage device may be available via using a cache memory that may be closely coupled to one or more of the CPU 1541, GPU 1542, mass storage device 1547, ROM 1545, RAM 1546, or the like.

[123] A computer-readable medium may contain computer code for performing various computer-implemented operations. The media and computer code may be specifically designed and constructed for the purposes of the present invention, or they may be well known and available to those skilled in the computer software art.

[124] By way of example, and not limitation, a computer system having architecture 1500, and in particular core 1540, may provide functionality through processor(s) (including CPU, GPU, FPGA, accelerators, and the like) executing software embodied on one or more tangible machine-readable media. Such computer-readable media may be media associated with a user-accessible mass storage device, as described above, as well as certain storage devices of the core 1540 that are non-transitory in nature, such as the internal mass storage device 1547 or the ROM 1545. Software implementing various embodiments implementation of the present invention may be stored in such devices and executed by the core 1540. The computer readable medium may include one or more storage devices or chips according to specific needs. Software may cause the core 1540 and, in particular, processors therein (including CPUs, GPUs, FPGAs, and the like) to perform certain processes or certain portions of specific processes described herein, including defining data structures stored in RAM 1546 and modifying such data structures according to processes defined by the software. In addition or alternatively, a computer system may provide functionality as a result of logic built into hardware circuitry or otherwise embodied in circuitry (e.g., accelerator 1544), which may operate instead of or in conjunction with software to perform certain processes or portions of specific processes described in this document. A reference to software may include logic and vice versa where applicable. Reference to a computer-readable medium may include circuitry (eg, an integrated circuit (IC)) storing software for execution, circuitry embodying logic for execution, or both, where applicable. The present invention includes any suitable combination of hardware and software.

[125] Although this description discloses several exemplary embodiments, there are variations, permutations, and various substitute equivalents that fall within the scope of the invention. Thus, it will be appreciated that those skilled in the art will be able to develop numerous systems and methods that, although not explicitly shown or described herein, embody the principles of the disclosure and are thus within its spirit and scope of protection.

Claims (41)

1. A video encoding method performed by at least one processor, comprising the following steps: receiving video data; obtaining a coding unit (CU) block of video data; determining whether a flag of the CU is set to a predetermined flag state; determining whether the tree type of the CU is set to a predetermined tree type; determining whether to signal an adaptive color conversion (ACT) flag based on either of whether the CU flag is set to a predetermined flag state and whether the CU tree type is set to a predetermined tree type; And encoding video data based on whether the ACT flag is signaled; wherein the method additionally contains: determining whether both encoded transformation unit (TU) flags are zero and whether the CU is encoded with ACT mode; And determining that the encoded luminance flag TU should be output equal to 1, based on determining that both encoded TU flags are zero and that the CU is encoded with the ACT mode. 2. The method of claim 1, wherein determining whether the ACT flag should be signaled is based on both whether the CU flag is set to a predetermined flag state and whether the CU tree type is set to a predetermined tree type . 3. The method of claim 1, wherein the predefined tree type indicates a single tree type, and wherein the predefined flag state comprises sps_act_enabled_flag equal to 1. 4. The method of claim 1, wherein the encoded TU flags are chroma channel flags. 5. The method of claim 1, wherein determining that the encoded luminance flag TU should be output equal to 1 is implemented regardless of whether the CU prediction mode is an intra mode. 6. The method of claim 5, wherein the encoding of the video data is further based on determining whether the encoded luminance flag TU should be output equal to 1. 7. A device for video encoding performed by at least one processor, comprising: at least one memory configured to store computer program code; at least one processor configured to access and operate in accordance with the instructions of the computer program code, the computer program code including: a first acquisition code configured to cause the at least one processor to receive video data; a second acquisition code configured to cause the at least one processor to obtain a coding unit (CU) block of video data; a first determination code configured to cause the at least one processor to determine whether a CU flag is set to a predetermined flag state; a second determination code configured to cause the at least one processor to determine whether the tree type of the CU is set to a predetermined tree type; a third determination code configured to cause the at least one processor to determine whether to signal an adaptive color conversion (ACT) flag based on either of whether the CU flag is set to a predetermined flag state and whether the CU tree type is set to a predetermined flag state. a certain type of tree; And encoding code configured to cause the at least one processor to encode video data based on whether the ACT flag is signaled; wherein the computer program code further comprises: a fourth determination code configured to cause the at least one processor to determine whether both encoded conversion unit (TU) flags are zero and whether the CU is encoded in ACT mode; a fifth determination code configured to cause the at least one processor to determine whether the coded luminance flag TU should be output equal to 1 based on determining that both coded TU flags are zero and that the CU is coded in ACT mode. 8. The apparatus of claim 7, wherein the determination of whether to signal the ACT flag is based on both whether the CU flag is set to a predetermined flag state and whether the CU tree type is set to a predetermined tree type . 9. The apparatus of claim 7, wherein the predetermined tree type indicates the type of the unit tree, and wherein the predetermined flag state comprises sps_act_enabled_flag equal to 1. 10. The apparatus of claim 7, wherein the encoded TU flags are chroma channel flags. 11. The apparatus of claim 7, wherein determining that the encoded luminance flag TU should be output to 1 is performed regardless of whether the CU prediction mode is intra mode. 12. A non-transitory computer-readable medium storing a program causing a computer to execute a process, the process comprising: receiving video data; getting a coding unit (CU) block; determining whether a flag of the CU is set to a predetermined flag state; determining whether the tree type of the CU is set to a predetermined tree type; determining whether to signal an adaptive color conversion (ACT) flag based on either of whether the CU flag is set to a predetermined flag state and whether the CU tree type is set to a predetermined tree type; And encoding video data based on whether the ACT flag is signaled; wherein the process additionally contains: determining whether both encoded transformation unit (TU) flags are zero and whether the CU is encoded in ACT mode; And determining whether the encoded luminance flag TU should be output equal to 1, based on determining that both encoded TU flags are zero and that the CU is encoded in ACT mode.