RU2774795C1 - Logic circuit - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: invention relates to methods and apparatus for processing information. The technical result is achieved due to the method for operation of the logic circuit containing, in response to a first command directed at the address of the logic circuit linked with the replaceable component of the printing apparatus, via a serial data bus, wherein the first command indicates a first period of time, the stages of: by the logic circuit, generating a low voltage condition on the serial data bus based on the first period of time; monitoring the duration of the low voltage condition using a logic circuit timer without a reference to the clock signal of the serial data bus; and removing, outside of said period of time, the low voltage condition, so that the serial data bus enters a different, high and/or default, voltage state or condition.

EFFECT: implementation of management and control of replaceable components of printing equipment.

22 cl, 8 dwg

Description

BACKGROUND OF THE INVENTION

[0001] Serial data bus protocols, such as the Integrated Circuit Interconnection Protocol (I ² C or I2C, and this designation is adopted here) and the Serial Peripheral Interface (SPI) protocol, allow at least one 'master' integrated circuit (IC) to communicate with at least one 'slave' IC, eg via a bus. I2C and other communication protocols transmit data according to the clock period. For example, a voltage signal may be generated where a voltage value is associated with data. For example, a voltage value above x volts may indicate a logic "1", while a voltage value below x volts may indicate a logic "0", where x is a predetermined numerical value. By generating the proper voltage in each of several clock cycles, data can be transferred over a bus or other communication line.

[0002] Some 2D and 3D printing systems include one or more replaceable components of the printing device, such as print media containers (e.g., inkjet cartridges, toner cartridges, ink tanks, building material sources, etc.), ink jet print head assemblies, etc. In some examples, the logic associated with the replaceable component(s) of the print device communicates with the logic of the print device in which they are installed, for example, by transmitting information, for example, their identifier, capabilities, status, etc.

[0003] In some examples, these transmissions use I2C transmissions. In such examples, the master IC can generally be provided as part of the print device (which may be referred to as the 'master'), and the print device plug-in will contain the 'slave' IC, although this is not true in all examples. There may be many slave ICs connected to the I2C link (eg containers of different print agent colors). The slave(s) IC may/may contain logic for performing data operations prior to responding to requests from the printing system logic.

[0004] In some examples, this may be intended to locate the physical location of slave devices that are attached along a serial bus. For example, you can assume that devices, for example, replaceable components of the printer, occupy some specified physical position in the printer. For example, in a printer with ink supplies connected to a serial bus, there may be an expected position for, for example, a black cartridge, a yellow cartridge, a cyan cartridge, and a magenta cartridge, each of which may have a specific address according to the communication protocol. By detecting whether ink cartridges of a particular color have been incorrectly installed or swapped, printing with incorrect or intended colors can be prevented. The previous patent disclosure is US Patent Application Publication Number US 2011/0029705.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Non-limiting examples will be described below with reference to the accompanying drawings, in which:

[0006] FIG. 1 shows an example of a printing system;

[0007] FIG. 2 is an example of a replaceable component of a printing device;

[0008] FIG. 3 is an example of a printing device;

[0009] FIG. 4 is an example of a method for operating a logic circuit associated with a replaceable component of a printing apparatus;

[0010] FIG. 5 is a schematic example of a printer logic diagram and a logic diagram associated with removable printer device components connected to a serial bus;

[0011] FIG. 6 is an example of another method of operation of a logic circuit associated with a replaceable component of a printing apparatus;

[0012] FIG. 7 is an example of a set of logic circuits; and

[0013] FIG. 8 is an example of a replaceable printer component containing a set of logic circuits.

DETAILED DESCRIPTION

[0014] Some examples of I2C transmission applications are described herein in the context of a print device. However, not all examples are limited to such uses, and at least some of the principles set forth herein may be used in other contexts.

[0015] In some examples, logic in a printer may receive information from logic associated with a removable printer component via a communication interface and/or may send commands to a removable printer component. Exemplary printing devices include a 2D imaging device and a 3D additive manufacturing device, such as inkjet printers, dry toner printers, liquid toner printers, powder pad 3D inkjet printers, and the like. Exemplary printing device components include ink tanks; ink bottles; print heads; inkjet print head cartridges; dry toner tanks; dry toner cartridges; photoconductive cartridges; processing cartridges; liquid toner tanks; 3D printing agents including inks, stimulating agents, adhesives, inhibitors, etc.; building material for 3D printing; service components of the printing device; and/or any other component that may be interchangeable with respect to the host print device and may or may not contain print material. In this invention, the print material or print agent may include ink, dry or liquid toner, 3D printing agents, 3D building material (plastic, metal, etc.), fibers, and so on. The above reservoirs may contain colored print material.

[0016] Transfers between the printing device and removable components of the printing device installed in the device may provide various functions. For example, the identifier, functionality, and/or status of a print device plug-in component and/or the logic associated therewith may be communicated to the print device logic via a communication interface. For example, logic associated with (or provided on or in) the print agent container may convey an identifier, such as a serial number and/or product brand, and/or identification characteristics, such as a color, a color map, a color map reconstruction recipe, the maximum amount of printing agent or functionality per printing device in which it is installed, see, for example, international patent applications no. The status, such as the fill level, may be provided via the communication interface, for example, such that the printing device may generate an indication of the fill level to the user. In some examples, the authentication process may be performed by the printing device. For example, the printing device may verify that the replacement part of the printing device comes from an authorized source to ensure its quality. For example, logic associated with a removable component of a printing device may store secret keys and may be configured to generate session keys, session key identifiers, and/or message authentication codes to generate authenticated cryptographic responses to the printer, see, for example, U.S. Patent No. 9,619,663. The logic may also include additional authentication mechanisms, such as specialized hardware to calculate responses in predetermined, relatively short, time windows, see, for example, US Pat. No. 9,561,662. In some examples, the authentication process may include control integrity to ensure that the replaceable print device component and/or the logic associated with it functions as expected.

[0017] In turn, instructions for performing a job may be sent to the logic circuit of the printer device component from the logic circuit associated with the printer device via a communication interface. For example, they may include instructions for performing an authentication or encryption function, a print media level registration function, print jobs, or other jobs.

[0018] In at least some of the examples described below, a set of logic circuits is described. the set of logic circuits may be associated with, for example, attached to, or located at least partially within a printer device plug-in component, and configured to communicate with the printer device controller via a bus provided as part of the printer device.

[0019] As used herein, the term 'set of logic circuits' refers to one or more logic circuits that can be interconnected or connected to each other with the possibility of data exchange. When more than one logic is provided, they may be encapsulated as a single unit, or may be encapsulated separately, or may not be encapsulated, or some combination of the above may be possible. Each set may be configured to communicate via a serial bus interface.

[0020] In some examples, each set of logic circuits is provided with at least one processor and memory. In one example, a set of logic circuits may be, or may function as, a microcontroller or a secure microcontroller. During operation, the set of logic circuits may be attached to or combined with a replaceable component of the printing device.

[0021] In some examples, a set of logic circuits may respond to requests (or commands) of various types from a host device (eg, a printer device). The request may include a request for data, such as identification and/or authentication information (eg, a 'read' request). In other examples, the request may contain a 'record' request. Another request from the host may be a request to perform an action, such as performing at least one measurement or performing a print job, or the like. Another type of request may be a data processing action request.

[0022] In an interaction example, the host device may send a command to a set of logic circuits associated with a removable component of the printer device, which can execute the command and load the received data into memory (in some examples, into a buffer and / or a specific memory register). The host can send an additional command to read the response, whereby the response is sent as serial data over the connected bus. Such a process can be used, for example, to obtain data stored in the memory of a set of logic circuits. For example, the first request may be a request for this bundle identifier, and may result in the bundle identifier being loaded into a memory buffer. A subsequent 'read' request may result in the data being read from the buffer and transmitted as a serial data signal.

[0023] In at least some examples, a plurality of such sets of logic circuits (each of which may be associated with one or another removable component of the print device) can be connected to the I2C bus.

[0024] In FIG. 1 shows an example of a printing system 100. Printing system 100 includes a print device 102 coupled to a replaceable print device component 104 via communication line 106 . Although for clarity, the replaceable component 104 of the printer is shown external to the device 102 of the printer, in some examples, the replaceable component 104 of the printer may be enclosed in the printer. Printing device 102 may be a 2D printing device or any type of 3D printing device.

[0025] The replaceable component 104 of the printer may, for example, contain a consumable resource of the printer 102 or a component that is likely to have a shorter life (in some examples, significantly less) than the printer 102. For example, the print device component 104 may physically store ink, toner, 3D printing agent, or 3D printing powder, and may be intended to be replaced after significant consumption. The replaceable component 104 of the printing device may, for example, contain a container or cartridge of print material (which may be a container of building material for 3D printing, or a container for liquid printing agent for 2D or 3D printing). In some examples, the replaceable print device component 104 may include a print head or other dispenser component. While this example shows a single replaceable print device component 104, in other examples, there may be multiple replaceable print device components, such as containing different color print agent containers, printheads (which may be combined with the containers), and the like.

[0026] In some examples, link 106 may comprise a serial bus, such as an I2C capable or compatible bus (hereinafter referred to as an I2C bus).

[0027] FIG. 2 shows an example of a replaceable print device component 200 that the replaceable print device component 104 shown in FIG. 1. The printer plug-in component 200 includes a data interface 202 integrated into the logic circuitry 204. During operation of the replaceable component 200 of the printer, the set of 204 logic circuits decodes the data received through the interface 202 data. Data interface 202 may include an I2C interface.

[0028] In some examples, logic circuitry 204 may be further configured to encode data for transmission over data interface 202. In some examples, there may be more than one data interface 202 provided for a single component 200.

[0029] In some examples, logic circuitry 204 may be configured to act as a 'slave' in I2C transmissions.

[0030] The replaceable print device component 200 in this example includes a print media reservoir 206, which may contain any of the print media examples discussed above.

[0031] In FIG. 3 shows an example of a printing device 300. The printer 300 may provide the printer 102 shown in FIG. 1. The print device 300 includes a controller 304 that includes an interface 302 for communicating with a replaceable print device component and a communication bus 306 . Controller 304 contains logic circuitry. In some examples, interface 302 is an I2C interface and communication bus 306 is a communication bus with I2C capabilities.

[0032] In some examples, controller 304 may be configured to act as a host or master in I2C transmissions. The controller 304 may generate and send commands to at least one pluggable print device component 200, and may receive and decode responses received therefrom.

[0033] Such a print device 102, 300 and replaceable component(s) of the print device 104, 200 and/or their logic circuitry may be manufactured and/or sold separately. In an example, a user may receive the print device 102, 300 and own the device 102, 300 for several years, while many replacement parts of the print device 104, 200 may be purchased over the years, for example, as the print agent is used to create the printed product. Therefore, there may be at least a degree of forward and/or backward compatibility between the print device 102, 300 and the replaceable components 104, 200 of the print device.

[0034] FIG. 4 shows an example of a method that can be implemented by a set of logic circuits associated with a replaceable component of a printing device. In some examples, the method may be carried out such that the printer device in which the replaceable print device component is installed can determine the physical location of the replaceable print device component. While the methods provided here can be used with communication protocols other than I2C, such as the Serial Peripheral Interface (SPI) protocol, it can be noted that in I2C protocols, multiple devices are connected in series on a single bus without any means of immediately detecting or declaring them. physical location or order. However, when considering, for example, SPI, there are two wiring configurations, parallel and series connected. In a parallel wiring configuration, there is a separate line dedicated to each ‘slave’ logic circuit, and in a serial wiring configuration, the devices are wired in series in a particular order, so their relative position can be verified in some other way. Therefore, the method provided here may be of particular benefit with protocols where it is otherwise difficult to verify the physical location of a device, such as I2C. However, this is not a limitation.

[0035] Block 402 comprises receiving a first command sent to an address of logic associated with a removable print device component via a serial data bus, such as an I2C bus. In some examples, the first command may indicate an operating mode. In some examples, the first command may indicate a period of time. The address may be an I2C bus interface address stored and/or hardwired in the logic/logic set. The first command may be sent to an address by the controller of the print device. The first command may be a predefined command.

[0036] Block 404 comprises generating, by logic, a low voltage condition on the serial data bus. As described in more detail below, this may comprise essentially providing a connection between the serial data bus (and in particular the data line of the serial data bus) and ground. In one example, the low voltage is a nominal ground or reference voltage, eg, approximately 0 V. As will also be described below, the low voltage is lower than the high or default voltage state or condition.

[0037] Block 406 comprises monitoring the duration of the low voltage condition using a logic timer. The timer may comprise an integral timer internal to the logic circuit, for example, comprising a resistance-capacitance (RC) circuit configured to act as a timer, logic gates provided with a counter, crystal or ring oscillator, a phase locked loop (also known as as a phase lock loop) and the like, or any timer that logically forms part of a logic circuit provided in conjunction with a replaceable component of the printing apparatus. The timer may provide an internal clock signal that is provided even in the absence of a clock signal on the serial data bus. The timer can count and thus allows you to determine the duration of the timer period specified in the first command.

[0038] The timer may be for measuring the time period of the command. In some cases, the timer is intended to measure time independently of other, general purpose, cycles in the actual set of I2C logic circuits, for example, I2C clocks and/or processing cycles of the host CPU or logic circuit. For example, a timer may be configured to count faster than a clock and may start and stop counting regardless of the timing of the clock. The timer may be configured to count independently of the speed of the logic/host CPU, eg having nominal specifications unrelated to the CPU.

[0039] In other examples, the logic circuit/logic stack may track a period of time based on tracking an external timer, such as an external clock generator, or by tracking external or internal waveforms, oscillating signals, etc., which in some cases may be useful for determining the length of a period of time. In one example, a set of logic circuits timer may be a timer in wireless communication with the logic circuit (and thus one timer can be shared by more than one logic circuit).

[0040] The method may comprise resetting the bus, or removing the low voltage condition, at the end of the time period such that the serial data bus assumes a different high and/or default voltage state or condition). This may, for example, include interruption of the connection to the ground. Outside of the time period, for example, before and after the duration of the time period initiated in response to the first command, the logic/logic stack may generate a high voltage condition. Alternatively, such a high voltage condition can be a default condition created by including a ‘pull-up’ resistor on the bus, as described below.

[0041] To consider, for example, the I2C data bus, it contains two communication lines: a serial data line (SDA) and a serial clock line (SCL). SDA and SCL can be two-way lines connected to the positive supply voltage through a current source or pull-up resistor.

[0042] In the absence of a signal on the line (ie, in the absence of a clock signal on the SCL and/or in the absence of a data signal on the data line), both lines may default to a high voltage state. The specific value of the voltage in the high voltage state depends on many operational factors, but in some examples may be several volts, for example, from about 3 to 6 volts. Therefore, although the overall 'high' voltage may be relatively low, it is high compared to the 'low' bus voltage condition, which may be, for example, less than 1 volt.

[0043] A master/master device (for example, in the present context, a processing circuit or a printer controller in which a plug-in printer is installed) can generate a clock signal by driving the voltage of the SCL line to a low state, for example, using a free-drain configuration to, in fact, , provide grounding. For example, a switch (eg, a FET) may be activated (closed) to instruct a low voltage state, then reopened so that a pull-up resistor on the line can drive the voltage to a high state. In other examples, a free collector configuration can be used in which a bipolar transistor (BJT) can be used for a similar result. The pull-down and reset timing provides a clock that is controlled by the master's processing circuitry.

[0044] For data communication, either the master or the slave (in this example, the logic associated with the plug-in print device) can selectively control the voltage on the SDA in a similar manner, lowering it (e.g., providing a connection to ground) or allowing it to be ' floating high' (for example, interrupting the connection to ground). This is clocked: according to the I2C protocol, the state of the SDA line when the SCL line is high provides at least one bit of data. Generally, if the SDA line is in a low (and steady) state when SCL is in a high state, it means binary 0, and if the SDA line is in a high (and steady) state when SCL is in a high state, it means binary 1 , although obviously, in a given system, this may vary.

[0045] In one example of the method shown in FIG. 4, instead of providing a data signal that is timed to match the high state of the SCL line, the state of the SCL line is not considered. Instead, the voltage drops for a duration that is tracked by the logic timer (again, for example, by securing a connection to ground), then 'reset', or may go high by default (for example, by interrupting this connection). Indeed, in some embodiments, there may be no clock provided by the host for at least part, and in some examples, the entire duration of the low voltage condition.

[0046] As mentioned above, this method can be used in the context of locating the physical location of replaceable components of a printing device, which will be described with reference to FIG. 5. For example, this method can be used when determining whether a replaceable component of a print device, such as a print media source, is installed at a designated position. In some instances, this may eliminate or reduce the use of a 'mechanical coding', whereby the replaceable print device component has a specific shape consistent with a 'slot' having a mating shape. This in turn reduces manufacturing complexity, since interchangeable components of the printing device, for example with different types of print media, such as different colors, can share a common physical design. In some examples, a combination of mechanical coding and the methods described here may be used. For example, in some applications where black (K) ink is typically dispensed more frequently than other colors (e.g., in contexts where text is frequently printed), black media supply cartridges may be physically larger than, for example, cyan supply cartridges. , magenta, or yellow media in the CMYK cartridge set. Therefore, in some instances, mechanical coding may be used for the black cartridge (for example, due to the fact that the black cartridge is much larger than cartridges of other colors), which may be sufficient to ensure that the black cartridges are placed in the intended 'slot', and the methods described here can be used to ensure that cartridges of other colors are in the right places.

[0047] In some examples, the time period tracking function, such as with a timer, can be used for other purposes. For example, a set of logic circuits may be configured to have more than one I2C address, for example, to facilitate communication with different logic circuits or different functions contained in the set, over the same I2C bus interface of the logic set (for example, through the same the same single communication pad, and the same single power pad, the same single ground pad, and/or the same single clock pad). For example, default read/write data transfers and low voltage generation and/or logging may be associated with the primary address of the logic stack, which is the aforementioned stack address. The set of logic circuits may be configured to temporarily "switch" (ie, respond to commands addressed to it) to a secondary, eg, temporary, I2C address upon receipt of the appropriate command. This command may include a second time period. This second period of time may be monitored by the logic bank, for example using a timer, to determine the time during which the logic bank must respond to commands received at the secondary address. For example, the logic may be associated with a primary address during a first time period and a secondary address during a second time period, the second time period being monitored using a timer. In this context, the first time period may be any time period outside of the second time period. In some practical examples, this second time period may be longer than the time period for generating a low voltage condition to allow sufficient time for data to be transferred to the secondary address, which time period may be longer than, for example, detecting the installation location of a replacement component. printing devices of this invention. Activating at least one more address may comprise setting (e.g., writing, overwriting, or changing) or causing another address to be set (e.g., a temporary second address), such as by writing another address to a memory location that specifies the address of the logic circuitry.

[0048] The logic circuitry may be configured to provide a first set of responses, or operate in a first mode, in response to instructions sent to a first address and provide a second set of responses, or operate in a second mode, in response to instructions sent to a secondary address. address. In other words, the address can trigger different functions provided by the circuit. In some examples, the first response set is available in response to commands sent to the first address and not in response to commands sent to the secondary address, and the second response set is available in response to commands sent to the secondary address and not in response to commands, sent to the first address. In some examples, the first set of the first set of responses may be cryptographically authenticated (eg, accompanied by message authentication, or otherwise cryptographically 'signed' and/or encrypted) and the second set of responses may not be cryptographically authenticated. In some examples, for example, the second address may be used to access other cells or sensors and the like that may be provided on or otherwise associated with the logic circuit.

[0049] Due to the multi-purpose nature of the time period tracking function, the execution times of these multiple jobs (e.g., location detection and transfer to a secondary address) can be specified depending on the characteristics of each platform of the printing device, for example, including speed, capabilities, logical set specifications circuits, the number of plug-in components that can be connected to a single bus, bus speed, etc.

[0050] FIG. 5 shows an example of a serial bus 500 containing only four lines: two active lines, SDA and SCL, as described above, a voltage source connection Vdd, and a ground connection GND. Active lines are two-way. The voltage source connection Vdd is connected to the first voltage source 502, and the SDA line is connected to the second voltage source 504 via a pull-up resistor 506.

[0051] A host device 508, for example, including a printer device controller coupled to an A/D converter 510, is coupled to bus 500. Bus 500, master device 508, and A/D converter 510 may be provided by a printer device. The host device 508 contains the processing circuit associated with the printer (in some examples included in it). Four 'slave devices' 512a-d, which contain logic associated with the removable printer components 514a-d, in this example attached to them, are also connected to the bus 500. In this example, each of the removable printer components 514a-d contains an ink cartridge of one color or another.

[0052] In this example, each slave device 512a-d attached to bus 500 has its own unique address and may be a receiver and/or transmitter. In typical operation, the serial clock and serial data signals are provided from the master device 508 on the clock signal line SCL and the data line SDA, while the operating voltage for the slaves is provided between the voltage source line Vdd and the ground line GND. Data signals may also be sent from slave device 512 to master device 508.

[0053] In an example, a transmission that starts with a start condition and ends with a stop condition may be referred to as an I2C “burst”. In an example of an I2C packet sent by master 508, this may contain the slave's address, an indication of whether the command is a read or write command (in some examples, these may together constitute a byte), a command code (which may be a second data byte), and , in some examples, any additional command data (eg, additional command parameters, message authentication codes (MACs), cyclic redundancy checks (CRCs), etc., which may be one or more subsequent bytes of data).

[0054] In the example operation of the method shown in FIG. 4, the master device 508 may first issue a start condition that acts as an ‘attention’ signal to all connected slave devices 512. This may, for example, be characterized by a voltage drop on the SDA line when the SCL voltage is high. The master 508 may then send a byte including the address of the slave 512 that the master 508 wishes to access and a bit that provides an indication of whether the access is a read or write operation.

[0055] After receiving the address byte, all slave devices 512a-d will compare it with their own address. In the absence of a match, slave 512 will generally wait for the next start condition that is initiated by master 508.

[0056] If the address matches, the circuit of this slave device 512a-d will receive the subsequent command information and then generate an acknowledgment response signal (“ACK” signal) (which may comprise pulling down the SDA line for a specific clock period).

[0057] In some of the examples herein, the command may be a command that causes the slave device 512 to generate a low voltage condition for a period of time. The low voltage condition may be prescribed after the generation of the ACK response signal. The host 508 may then generate a stop condition.

[0058] After the master device 508 receives the handshake signal, (and in some examples after generating a stop condition), the master device 508 may attempt to confirm that the slave device 512 has generated a low voltage condition on the SDA (and, in some examples, may stop sending clock signal to SCL while this low voltage condition is pending).

[0059] In this example, a resistive voltage divider circuit is provided on the serial bus SDA 500 to provide electronic determination of the respective physical locations of the slave devices 512. In particular, several divider resistors 516a-d are provided on the data line SDA, and there is a connection 518 from the data line SDA analog-to-digital converter (ADC) 510. This configuration creates a divider ladder circuit (resistor ladder circuit) that causes the signal voltage from each device 512 to vary depending on the physical position of device 512, as devices 512 are connected to the divider circuit at different points. For example, the signal from slave 512d would pass through four of the divider resistors 516, while the signal from slave 512a would pass through only one of the divider resistors 516a. By registering the voltage value, the position of the slave device 512 generating the low voltage condition can be determined. In other words, each slave device 512 creates a specific low voltage condition. The voltage may be sensed using the ADC 510. The ADC 510 includes circuitry that converts an analog voltage into a digital signal indicative of the voltage level. This digital signal is used by the master 508 to electronically differentiate the physical location of the slaves 512 on the bus based on the voltage level of the signals from the slaves 512. The voltage can be compared to the expected voltage for the device 512 having the address used in the command.

[0060] ADC 510 may receive control signals from and provide data to host 508 over a communication line (which may be another communication bus). Although ADC 510 is shown separately from host 508, ADC 510 may physically form part of host 508, or may be located separately from it.

[0061] The ADC 510 and the ladder divider circuit can be configured to discriminate location by detecting the order of device voltages on bus 500 without interfering with identifying the high and low states used in data transfer. In other words, all of the characteristically low voltages generated on the bus by each slave device 512 can be relatively removed from the threshold to characterize each data bit as high or low.

[0062] By way of one example, host 508 may be configured to detect any signal below a threshold as a low voltage condition when receiving data. For example, any voltage below 2V, or below 1V, at a high SCL voltage may be identified as a low data bit (in some examples, 0), while values above this threshold may be identified as a high data bit (in some examples, 1) . In some examples, the threshold for detecting a low data bit is below 1.3 V.

[0063] However, the host 508 using the converted voltage from the ADC 510 can be configured to distinguish between specific signals that are below this threshold and slightly above zero (or nominally 0 V) (e.g., up to a few hundred millivolts (mV) ) to provide positional identification. Each divider resistor 516 may have sufficient resistance that the voltage created between the sum of the divider resistors 516 and the pull-up resistor 504 is below the low voltage threshold. However, the divider resistors 516 may be chosen small enough that the identification of the high voltage signals from the master 508 during normal operation is not unduly compromised, i. so that the high voltage remains relatively close to the maximum voltage provided by the second voltage source 504.

[0064] In one embodiment, divider resistors 516 each have a resistance of about 51 ohms, although this is only one of many resistance levels that can be used, and resistance levels can vary between different resistors 516. In such an example, the first and second sources Voltages 502, 504 may provide about 3.3 volts, and pull-up resistor 506 may be a resistor of about 1000 ohms (1 kΩ), i. a significantly higher resistance value than the divider resistors 516.

[0065] In other words, the divider resistors 516 can act as separate ‘additional’ pull-up resistors on the SDA line, preventing drops to nominal 0 V. This can provide, for example, a voltage spread of about 100-200 mV around the above values. The ADC 510 can measure them with 'counts'. For example, in a 3.3V system where a 9-bit ADC is provided, this in turn means that each sample represents about 6mV (which is obtained by dividing 3.3V by 512). Therefore, the ADC 510 can be expected to record from about 20 counts for the lowest voltage cartridge to about 80 counts for the highest voltage.

[0066] As mentioned above, the positions of at least some of the replaceable components of the printing device can be checked using mechanical coding, rather than the methods described here. Therefore, the number of recorded voltage levels may be less than the number of, for example, used print cartridges.

[0067] It can be noted that, since specific addresses are associated with the replaceable components 514a-d of the printer device, a specific command can be sent to, for example, 514a, the voltage is sampled, and then the process can be repeated for each of the replaceable components 514b, c and d of the device print in sequence. If the replaceable components 514a-d of the printer are in the expected locations, you can expect a change in the voltage value in the direction of increase in the case measured in this order. If, on the other hand, replaceable printer components 514a-d are not in the expected locations, this pattern (or, more generally, the expected relative stresses) will not be observed and a warning may be generated.

[0068] In practice, the period of time during which the SDA line is kept low may exceed the sampling time period. For example, slave device 512 may be instructed by master device 508 to hold the SDA line low for 50 ms. During this time, the host ADC 510 may sample the data line SDA in a number of time periods, such as 3 to 10 time periods. In some examples, if at least one of these readings falls outside a certain threshold range, the instruction may be repeated, producing new samples. In other examples, samples may be taken until a threshold of 'good' samples is exceeded. In some such examples, there may be a maximum allowed number of samples before an error condition is declared, for example, sampling will continue until 5 samples are taken that are within the expected range, or a maximum of 10 samples have been taken. If a ‘good’ set of samples is not obtained, an error may be indicated. The samples may be averaged to generate a representative value for this printer plug-in 514a-d.

[0069] The sampling period may be relatively short. For example, after slave 512 is instructed to hold the SDA line low, master 508 may wait for the bus to be sampled so that the bus can be negotiated (eg, about 10 ms). Samples can be acquired in about 1 ms. However, the SDA line may be kept low for a longer period, such as 50 ms, to allow rechecking and the like. This period may be specified in the first instruction, or, in some examples, associated with it (eg, by referring to a lookup table or register maintained in slave 512).

[0070] Therefore, it is not necessary to keep the SDA line low for the entire time period specified in the first command, where applicable. However, it is possible that, at least statistically, slave 512 keeps the SDA line low in such a way that the sampling period is likely to last for the time that the SDA line is held low during at least one of the valid set of tests.

[0071] Obviously, the SDA line can be kept low, in fact, by sending a data signal formed by a sequence of data bits associated with a low voltage condition (eg, a sequence of 0-bits). As a result, the SDA line will be kept low for a period of time. However, when sending a data signal, the slave 512 can refer to the signal on the SCL, rather than its own internal timer, to determine when to reset the SDA line so that it can return to a high state (i.e., when to remove a low voltage condition, such that the serial data bus acquires a different high and/or default voltage state or condition). However, in the methods provided herein, the low voltage condition was applied after the first instruction was given, regardless of any clock signal on the SCL bus (and in some cases, in the absence of any such clock signal on the SCL bus).

[0072] FIG. 6 shows another example of a method for operating a logic circuit (eg, a set of logic circuits as described above) associated with a replaceable component of a printing device. In this example, at block 602, the logic receives, via the I2C data bus, the first command, which indicates the first time period. In this example, the first instruction also contains a start condition indication, a logic set address, an identification field indicating the write command, and a stop condition indication (eg, rising voltage on the data line during the high portion of the clock pulse).

[0073] In some examples, the time period may be selected based on attributes of the host device or its schema. In general, the period of time may be long enough to ensure that good samples are captured, but not so long as to unnecessarily lengthen the time taken to check the position of the printer's replaceable component.

[0074] Block 604 comprises generating, by logic, a low voltage condition on the I2C serial data line after receiving a stop condition indication (which itself follows the transmission of the command) and for substantially the duration of the first time period. As mentioned above, although in some examples the low voltage condition may be generated for the entire time period, in some examples the method may comprise allowing the serial data line to be ‘float high’ for part of the first time period, i. line can be kept low in intermittent mode. In some examples, the serial data line may be held low for at least 60% of the first time period, or at least 70% of the first time period, or at least 80% of the first time period, or at least 90% of the first time period, or at least 95% of the first time period. In some examples, the voltage is kept low for a sufficient proportion to reliably match the sampling period. The duration of the low voltage condition comprises at least one sampling period, where the sampling is performed by the processing circuit of the printing device, as described above. In addition, if the data line is kept low for an excessively long period of time, it results in blocked transmissions and may, for example, cause the host to generate a timeout error or the like.

[0075] Generating a low voltage condition after receiving a stop condition indicates that the bus will not block during the current transmission of a data packet.

[0076] In this example, the generation of the low voltage condition coincides with a state in which no clock exists on the serial data bus, and block 606 comprises monitoring the duration of the low voltage condition using an integrated logic timer.

[0077] The method further comprises, at block 608, in response to a read request, having an identification field indicating the read mode, implementation, by the read operation logic. In other words, in addition to the specific features described here, the logic circuit can function as an I2C slave. The logic circuitry may exhibit other characteristics of an I2C slave, such as participating in authentication and/or credential exchanges, receiving or executing read and/or writing commands, performing processing tasks, etc.

[0078] FIG. 7 shows an example of a logic circuit 700 for communicating with a removable component of a printing device, comprising logic 702, a serial data bus interface 704, a timer 706, and, in this example, a memory 708. During operation of the logic circuit 700, logic 702, in response to upon the first command sent to the logic bank 700 via the serial data bus connected to the serial data bus interface 704, the logic bank 700 in this example is configured to generate a low voltage condition on the serial data bus and tracks the duration of the time period using the timer 706. In some examples, timer 706 may be in communication with logic 702, such as over a wired or wireless link. In some examples, timer 706 may be provided on a common substrate with logic 702.

[0079] In some examples, logic 702 may be configured to track the duration of a period of time without reference to a serial data bus clock. The serial data bus interface 704 may include an I2C data bus interface.

[0080] The first command may indicate a period of time, and logic 702 may be configured to generate a low voltage condition on the serial data bus for substantially the duration of the first period of time. Logic 702 may implement any aspects of the methods described above with respect to FIG. 4-6.

[0081] In response to the second command, logic 702 may be configured to write data received via serial data bus interface 704 to memory 708. In response to a read request, logic 702 may be configured to read data from memory 708 and transmitting the data signal through the serial data bus interface 704.

[0082] FIG. 8 shows an example of a replaceable component of a printing device containing a set of logic circuits as shown in FIG. 7. In this example, the replaceable component of the printing device is the print cartridge 800, the width of the housing 802 of which is less than its height. A print fluid outlet 804 (in this example, an outlet provided on the underside of the cartridge 800), an air inlet 806, and a recess 808 are provided on the front surface of the cartridge 800. The recess 808 extends over the top of the cartridge 800, and the I2C bus terminals 810 of the logic circuitry 812 (e.g., logic array 700 as described above) are provided on the side of the notch 808 against the inside wall of the side wall of the housing 802 near the top and front of the housing 802. In this example, the logic array 812 is provided against the internal side of the side wall.

[0083] Examples in the present invention may be provided as methods, systems, or machine-readable instructions, such as any combination of software, hardware, firmware, and the like. Such computer-readable instructions may be included in a computer-readable storage medium (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) that stores computer-readable program codes.

[0084] The present invention has been described with reference to flowcharts and flowcharts of the method, devices, and systems according to examples of the present invention. Although the above flowcharts show a specific execution order, the execution order may differ from that shown. Blocks described with respect to one flowchart may be combined with blocks of another flowchart. It should be understood that at least some of the blocks in the flowcharts and block diagrams, as well as combinations thereof, may be implemented by computer readable instructions.

[0085] Machine-readable instructions may, for example, be executed by a general purpose computer, a special purpose computer, an embedded processor, or processors of other programmable data processing devices to implement the functions described in the description and diagrams. In particular, the processor or processing circuit may execute machine readable instructions. Thus, the functional modules of the device and devices (eg, logic circuitry and/or controllers) may be implemented by a processor executing machine-readable instructions stored in memory, or by a processor acting in accordance with instructions embedded in the logic circuitry. The term ‘processor’ should be interpreted in a broad sense to include CPU, processing unit, ASIC, logic unit or field programmable gate array, etc. All methods and functional modules may be implemented by a single processor or shared between multiple processors.

[0086] Such computer-readable instructions may also be stored in a computer-readable storage (eg, a tangible computer-readable medium) and may cause a computer or other programmable processing devices to operate in a particular mode.

[0087] Such computer-readable instructions can also be downloaded to a computer or other programmable data processing devices, whereby the computer or other programmable data processing devices perform several operations to create computer-implemented processing, thus instructions executable on a computer or other programmable data devices , implement the functions indicated by the block(s) in the flowcharts and/or flowcharts.

[0088] Additionally, the principles set forth herein may be implemented in the form of a computer program product, wherein the computer program product is stored on a storage medium and contains a plurality of instructions to cause the computing device to implement the methods mentioned in the examples of the present invention.

[0089] While the method, apparatus, and related aspects have been described with reference to some examples, various modifications, changes, deletions, and substitutions can be made without departing from the spirit of the present invention. Therefore, the method, apparatus, and related aspects are intended to be limited only by the scope of the following claims and their equivalents. It should be noted that the above examples illustrate more than what is described here, and that many alternative implementations will be available to those skilled in the art without departing from the scope of the following claims. Features described with respect to one example may be combined with features of another example.

[0090] The word "comprising" does not exclude the presence of elements other than those listed in the claims, their mention in the singular does not exclude the plurality, and a single processor or other block may implement the functions of several blocks mentioned in the claims.

[0091] The features of any dependent claim may be combined with the features of any of the independent claims or other dependent claims.

STATEMENTS

In some examples, the method can be described by any of the following statements:

Statement 1. A method comprising, in response to a first command sent to an address of a logic circuit associated with a replaceable component of a printing device, via a serial data bus,

generating, by logic circuitry, low voltage conditions on the serial data bus; and

monitoring the duration of the low voltage condition using a logic timer.

Statement 2. The method according to Statement 1, wherein the first instruction indicates a first time period and generating a low voltage condition on the serial data bus comprises generating a low voltage condition on the serial data bus based on the first time period.

Claim 3. The method of Claim 2, comprising generating a low voltage condition on the serial data bus for substantially the duration of the first time period.

Statement 4. The method according to any of the previous statements, comprising generating a low voltage condition on the serial data line of the serial data bus.

Statement 5. The method according to any of the previous statements, wherein the duration of the low voltage condition comprises at least one sampling period, wherein the sampling is performed by the processing circuit of the printing apparatus during the sampling period.

Statement 6: The method according to any of the previous statements, wherein the generation of a low voltage condition coincides with a state in which no clock signal exists on the serial data bus.

Statement 7. The method according to any previous statement, wherein the first command contains an identification field indicating a write command and indicating a stop condition,

the method further comprising generating, by the logic, a low voltage condition on the serial data bus upon receiving the stop condition indication.

Statement 8. The method according to Statement 7, further comprising, in response to a read request, having an identification field indicating the read mode, implementation, by logic, of the read operation.

Statement 9. The method according to any of the previous statements, wherein the voltage value of the low voltage condition indicates the position of the replaceable component of the printing device in the printing device.

Statement 10. The method according to any of the preceding statements further comprising removing the low voltage condition such that the serial data bus acquires a different high and/or default voltage state or condition.

Statement 11. A set of logic circuits for communicating with a replaceable component of a printing device, comprising:

logic and serial data bus interface,

moreover, the serial data bus interface serves to interface with the serial data bus of the printing device

wherein the logic serves, in response to a first command sent to the set of logic circuits via a serial data bus connected to the serial data bus interface, to generate a low voltage condition on the serial data bus and to monitor the duration of a period of time.

Statement 12. A set of logic circuits according to Statement 11, additionally containing a timer, in which the logic is used to track the duration of a period of time using the timer.

Statement 13: A set of logic circuits according to any of statements 11 and 12, in which the logic serves to remove a low voltage condition on the serial data bus at the end of a period of time.

Statement 14. A set of logic circuits according to any one of statements 11-13, in which the logic is configured to cause the serial data bus to acquire a different high and/or default voltage state or condition outside of a period of time.

Statement 15: A set of logic circuits according to any one of statements 11-14, wherein the logic is to output an acknowledgment response upon receipt of the first command prior to generating a low voltage condition.

Statement 16: A set of logic circuits according to any of statements 11-15, in which the logic is used to keep track of the duration of a period of time without reference to a serial data bus clock signal.

Statement 17. A set of logic circuits according to any of statements 11-16, wherein the first instruction indicates a period of time and the logic is to generate a low voltage condition on the serial data bus within the duration of the period of time.

Statement 18. A set of logic circuits according to any of statements 11-17, in which the logic is configured to generate a low voltage condition for a period of time specified in the first command.

Statement 19. A set of logic circuits according to any one of statements 11-18, wherein the first instruction indicates a period of time and the logic is to generate a low voltage condition on the serial data bus for substantially the duration of the period of time.

Statement 20. A set of logic circuits according to any of the statements 11-19, further comprising a memory, in which, in response to a second command, the logic is used to write the data received through the serial data bus interface to the memory.

Statement 21: A set of logic circuits according to any one of statements 11-20, additionally containing a memory, in which, in response to a read request, the logic is used to read data from the memory and to transmit a data signal through a serial data bus interface.

Statement 22: A logic circuit according to any one of statements 11-21, wherein the serial data bus interface is an I2C data bus interface.

Statement 23. A set of logic circuits according to any of the statements 11-22, configured to

communicate via more than one I2C address on the same I2C bus interface,

receive a command associated with the temporary use of another, secondary I2C address, and the command includes a second period of time,

track the second time period, and

respond to commands directed to the secondary I2C address for a second period of time.

Statement 24: A set of logic circuits according to Statement 22, which depends on Statement 12, in which the set of logic circuits includes a timer and the second period of time is monitored using the timer.

Statement 25. A replaceable component of a printing device containing a set of logic circuits according to any of the statements 11-24.

Statement 26. A replacement print device cartridge for connection to a print device, containing

a reservoir containing the colored print material, and

set of logic circuits:

moreover, the set of logic circuits includes logic and a serial data bus interface,

where the serial bus interface is used to connect to the serial data bus of the print device

where logic serves, in response to a first command, to locate a print device replacement cartridge when connected to a print device, the first command being sent to a set of logic circuits via a serial data bus connected to the serial data bus interface to generate a low voltage condition on the serial data bus and to track the duration of a period of time.

Statement 27. The replacement cartridge for the printing device according to Statement 26, further comprising any of the features of any of Statements 11-25.

Statement 29: A printing device comprising a communication bus comprising a resistor ladder circuit and configured to receive at least two sets of logic circuits according to any one of statements 11-25, wherein the sets of logic circuits have different I2C addresses and where each set is connected to the bus at a particular point in the ladder resistor circuit to generate a particular low bus voltage condition in response to a predetermined command.

Claims (42)

1. A method for operating a logic circuit, comprising, in response to a first command sent to the address of a logic circuit associated with a replaceable component of a printing device, via a serial data bus, wherein the first command indicates a first time period, steps in which: generating, by the logic circuit, a low voltage condition on the serial data bus based on the first time period; monitoring the duration of the low voltage condition using a logic timer without reference to a serial data bus clock; and outside of said time period, the low voltage condition is removed so that the serial data bus assumes a different, high and/or default, voltage state or condition. 2. The method of claim 1, comprising generating a low voltage condition on the serial data bus for substantially the duration of the first time period. 3. A method according to any one of the preceding claims, comprising generating a low voltage condition on the serial data line of the serial data bus. 4. A method according to any one of the preceding claims, wherein the duration of the low voltage condition comprises at least one sampling period, wherein the sampling is performed by the processing circuit of the printing apparatus during the sampling period. 5. A method according to any one of the preceding claims, wherein the generation of the low voltage condition coincides with a state in which no clock signal exists on the serial data bus. 6. The method according to any one of the preceding claims, wherein the first command contains an identification field indicating a write command and indicating a stop condition, the method further comprising generating, by logic, a low voltage condition on the serial data bus after receiving the stop condition indication. 7. The method of claim 6, further comprising, in response to the read request, having an identification field indicating the read mode, performing, by logic, a read operation. 8. A method according to any one of the preceding claims, wherein the low voltage condition voltage value indicates the position of the replaceable print device component in the print device. 9. A set of logic circuits for communicating with a replaceable component of a printing device, containing: logic, timer and serial data bus interface, moreover, the serial data bus interface serves to interface with the serial data bus of the printing device, wherein the logic serves, in response to a first command sent to the first address of the logic set via a serial data bus connected to the serial data bus interface, the first command indicating a period of time, for generating a low voltage condition on the serial data bus based on said period of time and for tracking the duration of said period of time using a timer without reference to the clock signal of the serial data bus; and outside of said time period to cause the serial data bus to acquire a different high and/or default voltage state or condition. 10. A set of logic circuits according to claim 9, in which the timer is configured to: count faster than the clock frequency; and start and stop counting regardless of clock timing. 11. A set of logic circuits according to claim 9 or 10, in which the first command serves to determine the location of the replaceable component of the printing device. 12. A set of logic circuits according to any one of paragraphs. 9-11, in which the logic is to output an acknowledgment response after receiving the first command before generating a low voltage condition. 13. A set of logic circuits according to any one of paragraphs. 9-12, in which the logic serves to generate a low voltage condition on the serial data bus within the duration of the time period. 14. A set of logic circuits according to any one of paragraphs. 9-13, wherein the logic is configured to generate a low voltage condition for a period of time specified in the first command. 15. A set of logic circuits according to any one of paragraphs. 9-14, wherein the first instruction indicates a period of time and the logic is to generate a low voltage condition on the serial data bus for substantially the duration of the period of time. 16. A set of logic circuits according to any one of paragraphs. 9-15, further comprising a memory, in which, in response to the second command, the logic is used to write the data received via the serial data bus interface into the memory. 17. A set of logic circuits according to any one of paragraphs. 9-16, further comprising a memory, in which, in response to a read request, logic is used to read data from the memory and to transmit a data signal through a serial data bus interface. 18. A set of logic circuits according to any one of paragraphs. 9-17, in which the serial data bus interface is an I2C data bus interface. 19. A set of logic circuits according to any one of paragraphs. 9-18, configured to: communicate via more than one I2C address on the same I2C bus interface, receive a command associated with the temporary use of another, secondary I2C address, and the command includes a second period of time, track the second time period, and respond to commands directed to the secondary I2C address for a second period of time. 20. A set of logic circuits according to claim 19, in which the second period of time is tracked using a timer. 21. A replaceable component of the printing device, containing a set of logic circuits according to any one of paragraphs. 9-20. 22. Replaceable print device cartridge for connection to a print device, containing: a reservoir containing the colored print material, and a set of logic circuits according to any one of paragraphs. 9-20, wherein the logic serves, in response to the first command, to determine the location of the replaceable cartridge of the printing device when it is connected to the printing device, and the first command is sent to the first address of the set of logic circuits through a serial data bus connected to the serial data bus interface, while the first command specifies the time period, for generating a low voltage condition on the serial data bus based on said period of time and for tracking the duration of said period of time using a timer without reference to the clock signal of the serial data bus; and outside of said time period to cause the serial data bus to acquire a different high and/or default voltage state or condition.

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