RU2762336C1 - Method for tracing a double-sided printed board for circuits with modular redundancy - Google Patents

Abstract

FIELD: electronics.

SUBSTANCE: invention relates to the design of printed circuit boards, specifically to the methods for PC board tracing. The expected result is achieved by the fact that in the tracing method for a double-sided printed circuit board that protects against USP, including the layout and tracing of the redundant and backup circuits, the layout and tracing of the redundant circuit are performed on the upper layer of the substrate, and the layout and tracing of the backup circuit are performed on the lower layer of the substrate mirror the upper layer, so that the redundant and backup conductors are located under each other. On the upper layer of the substrate, the reference conductor is performed to the left of the redundant conductor, and on the lower layer of the substrate, the reference conductors are performed to the left and right of the backup conductor. At the same time, the value of the line length multiplied by the value of the difference between the maximum linear delay and the largest of the remaining linear delays of the four pulses of the expansion of the ultrashort pulse is no less than the sum of the durations of the front, flat top and descent of the USP, fed between the conductor of the redundant circuit on the upper layer of the substrate and any reference conductor.

EFFECT: reduction in the mass of the printed circuit board, without reducing the suppression of ultrashort pulses (USP).

1 cl, 4 dwg

Description

The invention relates to the design of printed circuit boards, in particular to methods for routing them.

There is a known method of tracing printed circuit conductors with redundancy, including tracing printed conductors with a reference conductor in the form of a separate layer [Gazizov TR, Orlov P.E., Sharafutdinov V.R., Kuznetsova-Tadjibaeva OM, Zabolotsky A. M., Kuksenko S.P., Buichkin E.N. RF patent for invention No. 2603850, published on 10.12.2016]. The disadvantage of this method is the insufficient attenuation of the ultrashort pulse (SCI).

The closest to the claimed one is the method of redundancy chosen for the prototype for printed circuit boards, including the layout and tracing of the redundant and reserve circuits [Gazizov TR, Orlov P.E., Sharafutdinov V.R., Kuznetsova-Tadjibaeva OM, Zabolotsky A.M., Kuksenko S.P., Buichkin E.N. RF patent for invention No. 2603843, published on 10.12.2016]. The disadvantages of this method are the large mass and insufficient weakening of the SQI.

A method is proposed for tracing a double-sided printed circuit board that protects against ultra-short pulses, including the layout and tracing of the redundant and backup circuits, so that the layout and tracing of the redundant circuit is performed on the upper layer of the substrate, signal wires are performed due to gaps in the supporting conductive plate, and the layout and tracing of the redundant the circuit is performed on the lower layer of the substrate in a mirror-like manner to the upper layer, the reserved and redundant signal conductors of the circuits of the same name are located one under the other, and the remaining conductors are electrically connected to each other, characterized in that to the right of the active conductor, on the upper layer of the substrate, there is no reference conductor, the value the length of the line, multiplied by the value of the difference between the maximum linear delay of the line modes and the largest of the others, is not less than the sum of the durations of the front, flat top and decay of an ultrashort pulse applied between the active conductor on the upper layer of the substrate and any opo conductor, and the choice of the cross-sectional parameters ensures the minimization of the signal amplitude at the output.

The technical result consists in reducing the mass of the printed circuit board without reducing the suppression of the SQI. It is achieved due to the absence of one reference conductor and the choice of device parameters.

FIG. 1 a shows the equivalent circuit modeled to confirm the feasibility of the application. It consists of four parallel conductors l = 1 m each. The first conductor of the line at one end is connected to an SQI source, represented in the diagram by an ideal source of emf. E and internal resistance R 1. At the other end, the first conductor of the line is connected to the load, represented by the resistance R 3. The beginning of the signal conductor, on the bottom layer of the substrate, is connected to the plate (circuit ground) through the resistor R 2, and the end through the resistor R 4 The two left-most conductors are reference wires and are directly connected at both ends to circuit ground. Resistance values R 1 = R 2 = R 3 = R 4 = 50 Ohm. The acting SQI has the shape of a trapezoid with the following parameters: amplitude - 2 V, rise - 150 ps, flat top - 200 ps, decay - 150 ps.

FIG. 1b shows a cross section of the modeled structure. Cross-sectional parameters: ε _r - relative permittivity, w ₁ , w ₂ , w ₃ , w ₄ and t - width and thickness of conductors, h - dielectric thickness, s - distance between conductors. Parameter values: ε _r = 4.5, w ₁ = w ₂ = w ₃ = w ₄ = 1000 microns, s = 300 microns, h = 500 microns, t = 105 microns.

The values of the parameters of the cross-section and line length ensure the minimization of the signal amplitude at the output and the fulfillment of the condition

( τ ₄ - τ ₃ ) l ≥ t _r + t _d + t _f (1),

where τ ₄ - τ ₃ is the difference between the maximum linear delay of the line modes and the largest of the others, t _r , t _d and t _f are the duration of the front, flat top and fall of the pulse, respectively.

An impulse noise was applied between the reserved route (active conductor) and the reference conductor; the passive conductor performs the function of the reserve route. The result of the time domain simulation is shown in FIG. 1 c . At the output of the structure (node V 4), 4 decomposition pulses with linear delays are observed: τ ₁ = 4.398 ns / m, τ ₂ = 4.750 ns / m, τ ₃ = 5.736 ns / m, and τ ₄ = 6.359 ns / m. The value of the maximum voltage at the output of the structure is 0.33 V, while for the prototype it is 0.5 V. The decomposition of the impulse noise into a sequence of pulses of lower amplitude is due to the difference in the delays of linear modes in the structure formed by this method of arranging printed conductors for circuits with modal redundancy ... In the case of impulse noise supply between the passive conductor and any reference conductor, the maximum voltage at the structure output is 0.45 V (Fig. 1d ). The absence of one conductor reduces the mass, thus, the technical result, which the claimed method is aimed at, is shown.

Claims (1)

A double-sided PCB routing method that protects against ultra-short pulses, including the layout and routing of the redundant and redundant nets, so that the layout and routing of the redundant nets is done on the top layer of the backing, and the layout and routing of the backup net is done on the bottom backing layer, mirrored to the top layer, so that redundant and reserve conductors are located one under the other, characterized in that on the upper layer of the substrate, the reference conductor is made to the left of the reserved conductor, and on the lower layer of the substrate, the reference conductors are made to the left and right of the reserve conductor, while the value of the line length multiplied by the value of the difference the maximum linear delay and the largest of the remaining linear delays of four ultrashort pulse decomposition pulses, not less than the sum of the durations of the front, flat top and falloff of an ultrashort pulse fed between the conductor of the redundant circuit on the upper layer of the substrate and any op eternal conductor.

Images