RU2739723C1 - Continual processor - Google Patents

Abstract

FIELD: physics.SUBSTANCE: invention relates to a continual processor. Processor comprises interconnected analogue unit for calculating output function y=ƒ(x1, x2, … xn), unit for calculating logic function of condition θ(x1, x2, … xn), logic function calculation unit ϕ(y, x1, x2, … xn), two inverters, logic circuit 3-AND, two controlled closing switches, two resistors.EFFECT: technical result is higher efficiency of controlling analogue calculations.1 cl, 3 dwg

Description

The invention relates to automation and analog computing and can be used to build functional units of analog computers, automatic regulation and control, analog processors. The technical result is the expansion of the functionality of analog computing control in comparison with the prototype. To achieve the specified technical result, it is proposed to include in the control circuit of analog calculations a check of the calculation conditions and restrictions on the values of the output signals.

Technology area

The invention relates to automation and analog computing and can be used to build functional units of analog computers, automatic regulation and control, analog processors.

State of the art

By now, numerous versions of analog processors are known that allow comparison, selection and ranging of analog signals [1, 2, 3, 4, 5]. A common disadvantage of these devices is a narrow functional specialization, the lack of the possibility of using analog processors as a universal element of electronic circuits of automatic control devices. This disadvantage leads to the need to use hybrid circuits in automatic control devices, in which analog-to-digital signal conversion is first performed, and then the formation of control signals using computing devices [6]. The use of additional digital devices leads to a decrease in speed and an increase in the power consumption of automatic control devices, as well as to a deterioration in their weight and size characteristics.

The closest in technical essence to the proposed device is a unified situational control device (situator) for controlling analog calculations [7], containing an analog unit that implements the processing function F (y ₁ , y ₂ , ..., y _k1 ), a controlled closing key, logical block performing the logical function "AND" of the input predicate variables - x ₁ Λ x ₂ … Λ x _k2 (k ₁ ≤k ₂ ), inverter. The inputs of the analog block are connected to the analog inputs of the situator, the output of the analog block is connected to the first information contact of the key, the second information contact of the key is connected to the analog output of the situator; the logical inputs of the situator are connected to the inputs of the logical block, the output of the logical block is connected to the control input of the key, to the first logical output of the situator and to the inverter, the output of the inverter is connected to the second logical output of the situator.

The disadvantage of the prototype is the analysis of the computational process solely on the basis of the input signals required for calculating the output function. The prototype does not analyze the conditions for using the function and restrictions on its values. This narrows the applicability of the situational processor to complex computing devices.

The objective of the invention is to increase the functionality of analog devices by including in their composition circuits for logical processing of the state of the computing process and, as a consequence, expanding the possibility of using them in complex computing devices.

The technical result is to expand the functionality of analog computing control and a deeper structural unification of analog processors in comparison with the prototype, which makes this technical solution a universal tool for solving problems of automatic control. To achieve the specified technical result, it is proposed to include in the control circuit of analog computations a check of the computation conditions and restrictions on the values of the output signals.

The set goal in a continuous processor (CP) is achieved by the fact that it includes: an analog unit for calculating the output function y = ƒ (x ₁ , x ₂ , ... x _n ) 1 (Fig. 1), a unit for calculating the logical function of the condition θ ( xx ₁ , x ₂ , ... x _n ) 2, a block for calculating the logical limiting function ϕ (y, x ₁ , x ₂ , ... x _n ) 3, two inverters 4, a logic circuit 3-AND 5, two controlled closing switches 6, two resistors 7, analog inputs 8 of blocks 1, 2 and 3 (Fig. 1) are connected to analog inputs 9 (Fig. 2) KP, the input of the first inverter 4 is connected to the inverting logic input 10 KP and to the first terminal of the first resistor 7, the output of the first inverter 4 is connected to the first input of the logic circuit 3-AND 5, the second terminal of the first resistor 7 is grounded, the second input of the logic circuit 3-AND 5 is connected to the logic input 11 of the readiness signal of the input signals of the CP, the third input of the logic circuit 3-AND 5 is connected to the output of block 2 for calculating the logical function of the condition, the output of the analog block 1 for calculating the output f functions is connected to the input contact of the first key 6 and to the functional input 12 of the block 3 for calculating the logical function of limitation, the output of the logic circuit 3-AND 5 is connected to the control input of the second closing key 6, the output of block 3 is connected to the input contact of the second key 6, the output contact of the second switch 6 is connected to the input of the second inverter 4, to the first terminal of the second resistor 7, to the control input of the first closing switch 6 and to the logical output 13 KP, the second terminal of the second resistor 7 is grounded, the output contact of the first switch 6 is connected to the analog output 14 KP, the output the second inverter 4 is connected to the inverse logic output 15 KP.

The listed distinctive features in the claimed invention make it possible to expand the functionality of analog devices by means of computing control circuits.

FIG. 1 shows the functional diagram of the gearbox. A schematic diagram of the device is shown in FIG. 2.

The calculation of the value of the parameter y = ƒ (x ₁ , x ₂ ,… x _n ) is performed when analog signals x ₁ , x ₂ ,… x _{n are} applied to the inputs of 9 KP. At the same time, the logical signal of readiness of the input analog signals arrives at the input 11, and the logical signal at the input 10 in the case of blocking of calculations.

Analog block 1 calculates the value of the function y = ƒ (x ₁ , x ₂ , ... x _n ), transfers the calculated value to the first information input of the key 6 and to the functional input 12 of block 3.

In order to prevent incorrect results from reaching the analog output 14, the transmission of the output signal is blocked by the first switch 6, which breaks the output circuit. The first key 6 is controlled by a logical signal, which is transmitted through the second key 6 from the block for checking the restrictions 3. The signal of the calculated value of the function y = ƒ (x ₁ , x ₂ , ... x _n ) is sent to the functional input 12 of block 3 from the output of block 1, and from the analog inputs 9 of the device to the analog inputs 8 input analog signals are received. In block 3, constraints on the values of the function y = ƒ (x ₁ , x ₂ ,… x _n ) are checked. Comparators are used as comparison elements in block 3, the limiting parameters of which are set by the input signals x ₁ , x ₂ , ... x _n .

At the output of block 3, the function ϕ takes one of two values:

If the logical function of checking the constraints ϕ (y, x ₁ , x ₂ , ... x _n ) = 1 and the second key 6 is closed, then the first key 6 is closed and the result of calculating the function y = ƒ (x ₁ , x ₂ ,… x _n ) in block 1 goes to the output of 14 KP. If the logical function of checking constraints ϕ (y, x ₁ , x ₂ ,… x _n ) = 0 and the second key 6 is closed, then the first key 6 remains in the open state and the result of the function calculation y = ƒ (x ₁ , x ₂ ,… x _n ) in block 1 does not reach the output 14 of the control panel. When the second key 6 is open, the second terminal of the second resistor 7 and the control input of the first key 6 will have a zero potential, the first key 6 remains in the open state and the result of calculating the function y = ƒ (x ₁ , x ₂ , ... x _n ) in block 1 does not get to the exit 14 CP.

и выполнения условий расчета.The closure of the second key 6 occurs when the logic level "1" is fed to its control input from the output of the logic circuit 3-AND 5. The logic circuit 3-AND 5 performs the conjunction of logical signals: readiness of input parameters q _Г , negation of blocking

and fulfillment of the calculation conditions.

The blocking signal (q _BL = 1) is transmitted from the inverting logic input 10 of the device through the first inverter 4 to the first input of the logic circuit 3-AND 5.

The readiness signal of the input parameters q _G arrives at the second input of the logic circuit 3-AND 5 from the logic input 11 KP. It receives a logical value "1" if the values of all parameters x ₁ , x ₂ , ... x _{n are} fed to the analog inputs of the 8 KP. If at least one parameter from the set {x ₁ , x ₂ ,… x _n } was not obtained, then q _Г = 0.

The signal of the logical function θ (x ₁ , x ₂ , ... x _n ) of the fulfillment of the calculation conditions is calculated in block 2. Function 9 takes one of two values:

Resistors 7 in the logical circuits of the device are included to reset the input levels in the absence of signals.

When the second key 6 is closed, and when the constraints (1) are fulfilled, simultaneously with the transfer of the value of the parameter y to the analog output 14 KP, the readiness signal q = 1 is transmitted to the logical output 13 KP from the first terminal of the second resistor 7. Signal q, like the value of the parameter y, is an integral part of the calculation result. When the second key 6 is opened or when constraints (1) are not met, the ready signal is q = 0. To the inverse logic output 15 through the second inverter 4, a signal q is transmitted, which is opposite to the signal q.

The values of the logical functions ϕ (y, x ₁ , x ₂ ,… x _n ) and θ (x ₁ , x ₂ ,… x _n ) are calculated based on the comparison of analog signals in the time continuum. Thus, the keys 6 are controlled continuously, and all the output signals of the control panel are continuously changing at the rate of change of the signals at the inputs of the control panel.

The patented KP is effective in managing high-speed technical and technological processes. Such systems require a parametric analysis of the state of the object and the environment in real time to connect certain procedures and control functions. Let's consider a simple example of using the device.

Suppose you want to generate a control signal

The function ƒ ₁ (x ₁ , x ₂ ) in the task has the highest priority. It is applied if both signals x ₁ and x _{2 are} applied to the input of the device, the conditions for selecting the function ƒ _{1 are} not violated and the restrictions on the value Z = ƒ1 (x ₁ , x ₂ ) are fulfilled. Function ƒ ₂ (x ₁ ) is applied when at least one requirement for the use of function ƒ _{1 is} violated, signal x _{1 is} applied to the input, the conditions for selecting function ƒ _{2 are} not violated, and restrictions on the value Z = ƒ ₂ (x ₁ ) are fulfilled. Function ƒ ₃ (х ₃ ) is applied when at least one requirement for the use of functions ƒ ₁ and ƒ ₂ is violated, signal x _{2 is} applied to the input, the conditions for selecting function ƒ _{3 are} not violated and restrictions on the value Z = ƒ ₃ (x ₂ ).

The task is implemented in the form of a function selector (SF) by connecting three KPs: 16, 17, 18 (Fig. 3). SF processes analog signals x ₁ and x ₂ , which are fed to inputs 19 and 20. Logic levels of signs of signals (readiness) q ₁ and q ₂ are fed to inputs 21 and 22. Logic circuits 2I 23, 2OR 24 and 3OR 25 are included in the SF to control the work. KP 16 implements the function ƒ ₁ (x ₁ , x ₂ ). KP 17 implements the function ƒ ₂ (x ₁ ). KP 18 implements the function ƒ ₃ (x ₂ ).

In the selector, calculations are organized so that functions with a higher priority automatically block calculation functions with a lower priority. Blocking is performed by transmitting signals to the inverse logic outputs of the device with a lower priority from the logic outputs of the devices with a higher priority. Since, according to the conditions of the problem, the functions ƒ ₁ , ƒ ₂ , ƒ ₃ cannot be executed simultaneously, the functional outputs of the three controllers are shorted 26, and the logical outputs of the controllers are disjunctively combined 27.

The inclusion of logic functions in the control circuit of analog computations allows, in comparison with existing technical solutions of analog processors:

• to expand the functionality of analog processors in the direction of introducing additional functions for controlling calculations,

• by unifying the CP structure, implement a universal approach to the creation of analog processors, reduce the labor intensity and complexity of the development of analog processors that solve various computational problems,

• by unifying the presentation of signals at the inputs and outputs, use the CP as components of complex analog processors, the operation of which is based on the logic of signal processing,

• by eliminating digital processing, to increase the speed of functional and logical operations on analog signals.

The above information allows us to conclude that the proposed CP provides the declared advantages over the prototype.

The analysis of the prior art carried out by the applicant made it possible to establish that analogs characterized by sets of essential features that are identical to all features of the claimed commercial proposal are absent, which indicates that the claimed invention meets the "novelty" condition of patentability.

The proposed device is industrially applicable to existing technical means and meets the criterion of "inventive step", since they do not explicitly follow from the prior art.

Thus, the proposed technical solution meets the established conditions of patentability of the invention.

1. Patent RU No. 2173879 IPC G06G 7/25 published on 20.09.2001.

2. Patent RU No. 2281551 IPC G06G 7/52 published on 10.08.2006.

3. Patent RU No. 2446462 IPC G06G 7/52 published on 27.03.2012.

4. Patent RU No. 2474875 IPC G06G 7/52 published on February 10, 2013.

5. Patent RU No. 2514784 IPC G06G 7/25 published on May 10, 2014

6. R.G. Sanfelice. Analysis and Design of Cyber-Physical Systems. A Hybrid Control Systems Approach // Cyber-Physical Systems: From Theory to Practice / D. Rawat, J. Rodrigues, I. Stojmenovic. - CRC Press, 2016 .-- ISBN 978-1-4822-6333-6.

7. Patent RU No. 2541850, IPC G06G 7/25 published on February 20, 2015.

Claims (1)

Continuous processor (CP), which includes an analog unit for calculating the output function y = ƒ (x ₁ , x ₂ ,… x _n ), a unit for calculating the logical function of the condition θ (x ₁ , x ₂ ,… x _n ), a unit for calculating limiting logic function ϕ (y, x ₁ , x ₂ , ... x _n ), two inverters, 3-AND logic circuit, two controlled closing switches, two resistors, analog inputs of blocks for calculating the output function y = ƒ (x ₁ , x ₂ , ... x _n ), calculating the logical function of the condition θ (x ₁ , x ₂ , ... x _n ), calculating the logical function of limiting are connected to the analog inputs of the control panel, the input of the first inverter is connected to the inverting logic input of the blocking signal to the control panel and to the first output of the first resistor, the output of the first inverter is connected to the first input of the 3-AND logic circuit, the second terminal of the first resistor is grounded, the second input of the 3-AND logic circuit is connected to the logic input of the readiness signal of the input signals of the KP, the third input of the 3-AND logic circuit is connected to the output log calculator of the condition, the output of the analog block for calculating the output function is connected to the input contact of the first key and to the functional input of the block for calculating the logical function of limitation, the output of the logic circuit 3-AND is connected to the control input of the second closing key, the output of the block for calculating the logical function of limitation is connected to the input contact of the second key, the output contact of the second key is connected to the input of the second inverter, to the first terminal of the second resistor, to the control input of the first closing key and to the logical output of the CP, the second terminal of the second resistor is grounded, the output contact of the first switch is connected to the analog output of the CP, the output of the second inverter connected to the inverse logic output of the control panel.

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