RU2725137C1 - Excitation system of synchronous generator with external two-directional forcing - Google Patents

Abstract

FIELD: electrical engineering.SUBSTANCE: invention relates to electrical engineering and can be used in voltage regulators of synchronous AC generators of autonomous electric power sources. Excitation system with synchronous generator with external bidirectional boost includes synchronous generator (1) having armature winding (2) and winding of inductor (3), which is connected to output of first rectifier (4), summing transformer (5) having four windings: primary current (6); primary winding of voltage (7); secondary winding (8) and control winding (9) connected to output of voltage corrector (10), external direct current source (11), for example, a starter storage battery, a first electronic switch (12), current transformer (13), shunt (14), to which second rectifier (15) is connected, an analogue-to-digital converter (ADC) (16), first (17) and second (18) memory registers, first (19) and second (20) logic element, subtractor (21), setting register (22), first numerical comparator (23), first differentiator (24), RS-trigger (25), second differentiator (26), first logic element OR (27), START bus (28), shaper-limiter (29), inverter (30), second RS flip-flop (31), delay element (32), second numerical comparator (33), second (34), third (35), fourth (36), fifth (37), sixth (38) and seventh (39) electronic switch, second OR logic element (40). System provides for forced change of excitation during load release and outburst.EFFECT: technical result is expansion of functional capabilities by increasing of forcing capacity at load release.1 cl, 2 dwg

Description

The invention relates to electric machines, namely, to regulate the excitation of synchronous generators used in autonomous sources of electrical energy, mobile power units and power plants.

Known excitation systems of synchronous generators containing voltage regulators (coal, pulse, vibration) / 1 /.

The disadvantage of these systems is their low speed, since the regulators regulate the voltage deviation.

Known excitation systems of synchronous generators containing camouflage elements (resistors, autotransformers, summing transformers) / 2 /.

The disadvantage of these systems is the low accuracy, since they perform regulation according to the main disturbing factor, not taking into account other disturbances.

Known combined excitation systems of a synchronous generator containing a summing transformer that performs phase compounding and a voltage corrector that controls compounding / 3 /.

Their disadvantage is not high boosting ability and, as a consequence, the inability to start asynchronous motors with a squirrel-cage rotor comparable in power to the generator.

The closest in technical essence to the invention is a synchronous generator excitation system containing a synchronous generator, a summing transformer and a voltage corrector, the input of which is connected to the winding of the generator armature, and the output to the control winding of the summing transformer, the secondary winding of which is connected through the first rectifier to the inductor winding synchronous generator, the primary current winding of the transformer is connected in series with the winding of the generator armature, and the primary voltage winding is connected to the terminals of the generator, and in parallel with the winding of the generator inductor, an external DC source is connected through an electronic key, the control electrode of which is connected to the output of the OR element connected to the first input with the START bus, and the second input - with a direct trigger output, a single input of which through the first differentiator is connected to the outputs MORE and EQUAL of the numerical comparator, the output LESS of which is connected to the first input of the AND element, the output is The second through the second differentiator is connected to the trigger trigger input, and the second input to the inverter output connected to the output of the shaper-limiter, the input of which is connected to the output of the second rectifier, which is connected by the input to the potential terminals of the shunt included in the secondary circuit of the current transformer, the primary winding of which is connected in series with the winding of the generator armature, in addition, the output of the second rectifier is connected to the input of an analog-to-digital converter, the output bits of which are connected to the corresponding bits of the information inputs of the first and second memory registers, the recording inputs of which are connected respectively to the first and second output of the pulse distributor, connected by an input to the output of a stable frequency pulse generator, while the corresponding bits of the outputs of the first and second memory registers are connected respectively to the first and second inputs of the subtractor, the output bits of which are connected to the corresponding bits of the of the input of the numerical comparator, the bits of the second input of which are associated with the corresponding bits of the output of the master register / 4 /.

This excitation system has a high boosting ability when the generator loads surge. However, it does not affect the excitation during load shedding.

The purpose of the invention is the expansion of functionality by increasing the boosting ability during load shedding.

The purpose of the invention is achieved in that the excitation system of a synchronous generator with external bi-directional forcing, The excitation system of a synchronous generator with external bi-directional forcing, containing an external DC source, first and second rectifiers, a shunt, shaper-limiter, the first RS-trigger, the first and second differentiators , the first and second memory registers, specifying the register, analog-to-digital converter, subtracter, first numerical comparator, first electronic key, logical element NOT, first logical element AND, first logical element OR, connected by the first input to the START bus, synchronous generator, summing a transformer and a voltage corrector, the input of which is connected to the winding of the armature of the generator, and the output to the control winding of the summing transformer, the secondary winding of which is connected to the input of the first rectifier, the primary current winding of the summing transformer is connected in series with the primary winding of the transformer and the generator armature winding, and the primary voltage winding is connected to the generator terminals, and the output of the second rectifier is connected to the input of the analog-to-digital converter, the output bits of which are connected with the corresponding bits of the information inputs of the first memory register, while the corresponding output bits of the first memory register are connected respectively to the first input of the subtractor, the output bits of which are connected with the corresponding bits of the first input of the numerical comparator, the bits of the second input of which are connected with the corresponding bits of the output of the master register, in addition, the output of the second rectifier is connected to the input of the driver-limiter connected to the output with the input of the logical element NOT, provided the second logical element AND, the second logical element OR, the delay element, the second numerical comparator, the second, third, fourth, fifth, sixth and seventh electronic key, the second RS-trigger, the inverse output of which is connected to the control it is the input of the first electronic key, direct output - with the second inputs of the first and second logical element And, a reset input - with the first output of the third electronic key, and a single input - with the second output of the third electronic key, the second input of which is connected to the output MORE than the first numerical comparator connected by the outputs EQUAL and LESS to the first input of the third electronic key, the control input of which is connected to the output of the second differentiator, and the control input of the second electronic key, the first input of which is connected to the output of the negative difference sign of the subtractor, the second input - with the output of the positive difference sign of the subtractor, the second output - with a single input of the second RS-flip-flop, and the first output - with the reset input of the second RS-flip-flop, the direct output of which is connected to the first input of the second logical element And, and the inverse output - to the first input of the first logical element And, connected by the output with the second input of the first logical element OR, the first input of which is connected to the reset input of the second memory register and to the first input of the second OR logic element, the output of which is connected to the reset input of the first memory register, and the second input - with the output of the delay element, the input of which is connected to the output of the logical element NOT and the recording input of the second the memory register, the bits of the information input of which are associated with the corresponding bits of the output of the first memory register and the bits of the second input of the second numerical comparator, the output of which is MORE connected to the input of the first differentiator, connected by the output to the recording input of the first memory register, the outputs LESS and EQUAL are to the input of the second differentiator and the bits of the second input to the corresponding bits of the output of the analog-to-digital converter, in addition, the inputs of the first, fifth and sixth electronic keys are connected to the positive pole of the first rectifier, the negative pole of which is connected to the first terminal of the inductor connected by the second terminal to the outputs of the the fourth, seventh and seventh electronic key, the input of which is connected to the output of the fifth electronic key and the negative pole of the external DC source, the positive pole of which is connected to the output of the sixth electronic key and the input of the fourth electronic key connected by the control input to the control input of the fifth electronic key and the output the first logical element OR, and the control inputs of the sixth and seventh are connected to the output of the second logical element I.

The fourth, fifth, sixth and sixth electronic keys and their connections provide a change in the direction of the excitation boost. The second RS-trigger, the second logical element AND, the second and third electronic keys and their connections determine the direction of the force. The second numerical comparator, the second logical element OR, the delay element and their connections provide a measurement of the amplitude of the load current to analyze the nature of its change.

In FIG. 1 is a diagram of a synchronous generator excitation system; FIG. 2 - diagrams of signals on the main elements of the circuit.

The excitation system includes a synchronous generator 1, having an armature winding 2 and an inductor 3 winding, which is connected to the output of the first rectifier 4, summing transformer 5, having four windings: primary current 6; primary winding voltage 7; the secondary winding 8 and the control winding 9 connected to the output of the voltage corrector 10, an external DC source 11, for example, a starter battery, a first electronic key 12, a current transformer 13, a shunt 14 to which a second rectifier 15, an analog-to-digital converter ( ADC) 16, the first 17 and second 18 memory registers, the first 19 and second 20 logic element, the subtractor 21, the register 22, the first numerical comparator 23, the first differentiator 24, the RS-flip-flop 25, the second differentiator 26, the first logical element OR 27 , START bus 28, driver-limiter 29, inverter 30, second RS-trigger 31, delay element 32, second numerical comparator 33, second 34, third 35, fourth 36, fifth 37, sixth 38 and seventh 39 electronic key, second logical element OR 40.

The excitation system of a synchronous generator operates as follows.

For the initial excitation of the generator 1, a short signal is supplied to the bus 28 START. At the same time, the circuit is restored to its initial state: memory registers 17 and 18 are reset, and a signal appears at the inverted output of trigger 25. The signal from the START bus 28 through the OR gate 27 is fed to the control inputs of the keys 36 and 37, which, when opened, briefly include an external source 11 in the circuit of the inductor 3 of the generator. The generator 1 is excited and a voltage appears on the armature winding 2, which is supplied to the voltage winding 7 of the summing transformer 4. A current starts flowing through the winding 7 and a magnetomotive force (MDS) of the winding 7 appears. Under its action, a magnetic flux arises, which induces an electromotive force (EMF) in the secondary winding 8. It is fed to the input of the rectifier 4 and the excitation current flows through the winding of the inductor 3 through the switch 12, providing a given voltage level at idle and at low loads.

When connected to the terminals of the generator 1 load flowing through the windings of the armature 2 current generates a reaction of the armature, which tends to change the voltage. At the same time, the load current flows through the current winding 6 of the transformer 5 and the MDS of the winding 6 appears, which geometrically folds with the MDS of the winding 7. The resulting MDS increases with active and inductive load and decreases with capacitive load. Accordingly, the magnetic flux of the transformer 5, the EMF in the secondary winding 8 and the excitation current of the generator 1 in the winding of the inductor 3 are changed. This compensates for the effect of the armature reaction, and the voltage of the generator remains at the same level.

To improve the accuracy of regulation, the current from the output of the voltage corrector 10 is supplied to the control winding 8 of the transformer 4. If the voltage of the generator has increased for any reason, the output current of the corrector 10 flowing through the winding 8 increases. The saturation of the steel of the core of the transformer 5 increases, and the electromagnetic transmission from the primary windings 6 and 7 to the secondary winding 8 is reduced. The EMF of the winding 8 decreases, the excitation current decreases, and the voltage of the generator is restored to the same level. If the voltage of the generator decreases, then the saturation of the steel of the transformer also decreases, and the electromagnetic transmission and the excitation current increase, stabilizing the voltage at a given level.

Simultaneously with the processes described above, the magnitude of the load current i (t) flowing along the primary winding of the transformer 13 is analyzed.

The current of the secondary winding of the current transformer 13 i ₂ (t) = i (t) / k, where k is the transformation coefficient of the transformer 1, flowing through the shunt 14, causes a voltage drop u ₂ (t) = i ₂ (t) r, where r is the resistance of the shunt 14, which is fed to the input of the rectifier 15. At the output of the rectifier 15, a pulsating voltage u (t) = | u ₂ (t) | X15 (Fig. 2) supplied to the input of the ADC 16. At the output of the converter 16, the code X16 (Fig. 2) of the instantaneous value of the input voltage K (t) = u (t) / u _p , where u _p is the quantization step of the ADC 16, is generated .

This X16 code is essentially a code for the instantaneous value of the generator load current. The increasing code X16 from the output of the ADC 16 is supplied to the first input of the comparator 33. A zero code is supplied to the first input of the comparator 33 from the input of the memory register 17. Therefore, a signal appears at the output of MORE comparator 33. At the edge of this signal, the differentiator 24 gives a pulse to the input of the memory register 17 into which the current instantaneous current value code X16 is recorded. As the X16 code grows at the output of the ADC 16, the code is rewritten into the memory register 17 and the X17 code of the load current amplitude is formed at its output. After writing the code of the current amplitude to the memory register 17, the overwrite stops and a signal appears at the output of EQUAL and LESS than the comparator 33. At the same time, the pulsating voltage X15 from the output of the rectifier 15 is fed to the input of the driver-limiter 29, which generates a rectangular pulse X29, which is input to the element 30 A short pulse X30 appears at the output of the element NOT 30 with the beginning of each half of the current wave. This pulse X30 writes the code X17 to the memory register 18 from the output of the memory register 17 and the code X18 of the previous amplitude of the load current appears at the output of the memory register 18. With a time delay, the pulse X30 from the output of the element NOT 30 through the delay element 32 passes through the OR element 40 and resets the memory register 17, preparing it for the formation of the next code of the amplitude of the load current.

As a result, each half of the period forms the previous code X18 of the current amplitude I _{m (i)} at the output of the memory register 18 and the subsequent code X17 of the amplitude of the current load I _{m (i + 1)} at the output of the memory register 17.

These codes X17 and X18 are fed to the inputs of the subtractor 21 and the output code X21 of the difference of the previous and subsequent amplitudes of the load current ΔI _m = I _{m (i)} -I _{m (i + 1)} (amplitude increment for half the period) that arrives to the first input of the comparator 23. At the second input of the comparator 23 from the output of the setter 22, a code X22 of the permissible difference of the current amplitudes ΔI _{m additional} is supplied, at which a forced change in excitation is not required.

If the increment of the current amplitude does not exceed the permissible value ΔI _m ≤ΔI _{m ext.} and forcing is not required, then signal X23 ⁽²⁾ appears at the output of EQUAL or LESS than comparator 23. At the time of the formation of the next current amplitude code, pulse X26 triggers 25 to zero, and signal X25 ⁽²⁾ from its inverse output goes to the control input of the key 12, which opens directly connects the rectifier 4 to the inductor 3.

If the increment of the current amplitude exceeds the permissible value ΔI _m > ΔI _{m add.} and forcing is required, signal X23 ⁽¹⁾ appears at the output of MORE comparator 23. At the time of the formation of the next current amplitude code, when pulse X26 appears at the output of differentiator 26, key 35 is opened and trigger 25 is brought into a single state. The signal X25 ⁽¹⁾ from the direct output of the trigger 25 prepares the elements And 19 and 20 on the second inputs.

With a load surge, the previous current amplitude is less than the next I _{m (i)} <I _{m (i + 1)} and the code X17 is larger than the code X18, therefore, the difference code X21 at the output of the subtractor 21 has a negative sign. At the moment of completion of the generation of the current amplitude code by pulse X26 from the output of the differentiator 26, the key 34 is briefly opened and the signal X21 ^(-) from the output of the sign of the negative difference of the subtractor 21 trigger 31 is brought to the zero state. The signal X31 ⁽²⁾ from the inverted output of the trigger 31 opens the And 19 element, and from its output through the OR element 27, the signal X19 is sent to the control inputs of the keys 36 and 37. These keys 36 and 37 are opened and connected in series according to the external source 11 with rectifier 4 , providing a forced increase in excitation during a load surge.

When loading the load, the previous current amplitude is greater than the next I _{m (i)} > I _{m (i + 1)} and the code X17 is less than the code X18, therefore, the difference code X21 at the output of the subtractor 21 has a positive sign. The signal X21 ⁽⁺⁾ from the output of the sign of the positive difference of the subtractor 21, the trigger 31 is transferred to a single state. The signal X31 ⁽¹⁾ from the direct output of the trigger 31 opens the element And 20, the signal X20 from the output of which the keys 38 and 39 are turned on. These keys 38 and 39 include an external source 11 in series with the rectifier 4, which provides a forced decrease in excitation during load shedding.

Thus, the proposed excitation system of the generator has a high boosting ability, limited only by the parameters of the external source 11. At the same time, bi-directional boosting of the excitation is ensured both during the surge and during the load shedding of the generator.

Sources of information

1. Polyansky V.F., Popov A.V. Electrical equipment of ships and enterprises: Textbook for universities. - M .: Transport, 1989, p. 233-236.

2. Sugakov V.G., Khvatov O.S. Fundamentals of automatic regulation of output electrical parameters Part 2. Automatic regulation of the voltage of autonomous sources of electrical energy. Textbook for universities. - Kstovo: NVVIKU (VU), 2007, p. 44-52.

3. Sugakov V.G., Khvatov O.S. Systems of automatic regulation of electrical energy parameters of ship power plants. Part 2. Automatic voltage regulation of ship electrical energy sources. Tutorial. - N. Novgorod: Publishing house of FSEI HPE "VGAVT", 2011, p. 59-95.

4. The excitation system of a synchronous generator. Description of the invention to patent RU 2470454, cl. Н02Р 9/14, 2012.

Claims (1)

The excitation system of a synchronous generator with external bi-directional forcing, containing an external DC source, first and second rectifiers, a shunt, a shaper-limiter, a first RS-trigger, the first and second differentiators, the first and second memory registers, a register, an analog-to-digital converter, a subtractor, a first numerical comparator, a first electronic key, a logical element NOT, a first logical element AND, a first logical element OR, connected by the first input to the START bus, a synchronous generator, a summing transformer and a voltage corrector, the input of which is connected to the generator armature winding, and the output - to the control winding of the summing transformer, the secondary winding of which is connected to the input of the first rectifier, the primary current winding of the summing transformer is connected in series with the primary winding of the current transformer and the armature of the generator, and the primary voltage winding is connected to the terminals of the generator, and the output of the second rectifier the capacitor is connected to the input of an analog-to-digital converter, the output bits of which are associated with the corresponding bits of the information inputs of the first memory register, while the corresponding bits of the outputs of the first memory register are connected respectively to the first input of the subtractor, the output bits of which are connected to the corresponding bits of the first input of the numerical comparator, bits the second input of which is associated with the corresponding bits of the output of the master register, in addition, the output of the second rectifier is connected to the input of the shaper-limiter, connected by the output to the input of the logic element NOT, characterized in that in order to expand the functionality by increasing the boosting capacity during load shedding, it is equipped with a second logical AND element, second logical OR element, delay element, second numerical comparator, second, third, fourth, fifth, sixth and seventh electronic key, second RS-flip-flop, whose inverse output is connected with the control input of the first electronic key, direct output - with the second inputs of the first and second logical element And, the reset input - with the first output of the third electronic key, and a single input - with the second output of the third electronic key, the second input of which is connected to the output MORE than the first numeric a comparator connected by the outputs EQUAL and LESS to the first input of the third electronic key, the control input of which is connected to the output of the second differentiator and the control input of the second electronic key, the first input of which is connected to the output of the negative difference sign of the subtractor, the second input - with the output of the positive difference sign of the subtractor, the second output - with a single input of the second RS-flip-flop, and the first output - with the reset input of the second RS-flip-flop, the direct output of which is connected to the first input of the second logical element And, and the inverse output - to the first input of the first logical element And, connected by the output with the second input of the first logical ele OR, the first input of which is connected to the reset input of the second memory register and to the first input of the second logical element OR, whose output is connected to the reset input of the first memory register, and the second input - to the output of the delay element, the input of which is connected to the output of the logical element NOT and the recording input of the second memory register, the bits of the information input of which are associated with the corresponding bits of the output of the first memory register and the bits of the second input of the second numerical comparator, whose output is MORE connected to the input of the first differentiator, connected by the output to the recording input of the first memory register, LESS and EQUAL are the input of the second differentiator, and the bits of the second input to the corresponding bits of the output of the analog-to-digital converter, the inputs of the first, fifth and sixth electronic keys are connected to the positive pole of the first rectifier, the negative pole of which is connected to the first terminal of the inductor connected to the second terminal with the outputs the first, fourth and seventh electronic key, the input of which is connected to the output of the fifth electronic key and the negative pole of the external DC source, the positive pole of which is connected to the output of the sixth electronic key and the input of the fourth electronic key connected to the control input with the control input of the fifth electronic key and the output the first logical element OR, and the control inputs of the sixth and seventh are connected to the output of the second logical element I.

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