RU2708501C1 - Parallel-series adder-subtractor by higher positions forward on neurons - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to the computer equipment. Device comprises a number input unit, a comparator unit, a parallel-serial adder unit-subtractor unit, a register of a greater number, unit for determination of transfer and borrowing, unit of registers of smaller number, unit of result registers, device control unit, threshold and neuron-like elements. Arithmetic operations of the computer are performed in a parallel-serial format in direct codes by bytes, the result is calculated using a sum operation modulo two, transfer during summation of binary numbers is determined on a threshold element.

EFFECT: technical result is faster execution of arithmetic operations.

1 cl, 10 dwg

Description

The invention relates to technical means of computer science and computer technology and can be used to create arithmetic-logic devices, to create high-speed and economical digital devices for adding and subtracting numbers in direct codes.

The well-known "Digital Adder Circuit" (No. 99109089/09, dated 04/07/1997), which allows performing the operation of combining cheshel in a binary number system.

It is known "Device for addition" (No. 4892584/24, dated 12/19/1990), which calculates the sum of binary numbers.

As a prototype, “Adder-Subtractor with Higher Digits Ahead on Neurons” (No. 2205444 of 05.27.2003) was selected, which calculates the sum and difference of binary numbers in direct codes.

The disadvantage of the proposed technical solutions is the low speed of the operations of addition and subtraction, a complex algorithm of work.

In the presented parallel-serial adder-subtractor

arithmetic operations are performed by senior bits ahead on neurons: summation and subtraction of binary numbers.

The technical task of the proposed solution is to increase the speed of arithmetic operations, increase the reliability of the adder-subtractor, simplify the algorithm of the device.

The solution to the problem is that a parallel-serial adder-subtracter with higher digits forward on the neurons contains, a number input unit, a comparation unit, a larger number register block, a transfer and loan determination block, a lower number register block, a result register block, a control unit, additionally a parallel-serial adder-subtracter unit is introduced, the first and second information outputs of the number input unit being connected respectively to the first and second information inputs of the comparation unit, the fourth control output of which is connected to the third control input of the control unit, the first information output of which is connected to the second information input of the result register block, the control input of which is connected to the third control output of the comparator block, the second information output of which is connected to the first information input of the lower number register, the first control input of which is connected to the second control output of the comparation unit, the first information output of which is connected to the first m information input of the register block of a larger number, the first control input of which is connected to the first control output of the comparation unit, the control input of which is connected to the control output of the number input unit and with the control input of the transfer and loan determination unit, the first information input of which is connected to the second information output of the block more registers, the second information input of which is connected to the third information output of the control unit, the second control output of which is connected to the second m control input of the register block of a larger number, the first information output of which is connected to the first information input of the parallel-sequential adder-subtracter block, the second information input of which is connected to the information output of the transfer and borrow determination unit, the second information input of which is connected to the second information output of the register block a smaller number, the second information input of which is connected to the second information output of the control unit, the first control output of which connected to the second control input of the lower number register block, the first information output of which is connected to the third information input of the parallel-serial adder-subtracter block, the information output of which is connected to the first information input of the result register block, the first and second control inputs "RESET" and "START "the control unit are the external inputs of the parallel-serial adder-subtracter higher bits forward on the neurons.

BVCh - the block of input of numbers serves for input of operands and an operation sign.

BKO - the comparation unit is used to compare binary numbers, if it is necessary to perform the subtraction operation.

BPSSV - block parallel-serial adder-subtractor serves to perform addition and subtraction operations.

BRgBCH - a block of registers of a larger number is used to store the first number in the case of the addition operation or to store a larger modulo number in the case of the subtraction operation.

BOPZ - unit for determining the transfer of seizure - is used to detect the transfer from the lower digits to the higher digits during the summation or to form a loan from the higher digits to the lower digits in the case of subtraction of numbers.

BRGMCH - a block of registers of a smaller number serves to store the second number in the case of the addition operation or to store a smaller module in the case of the operation of subtraction.

BRGR - a block of result registers is used to store the amount when adding or difference when subtracting numbers, as well as the sign of the result.

BU - the unit is used to control the device.

The algorithm for adding numbers in direct codes allows you to get the result in direct code. The sum and difference of binary numbers is calculated in direct codes by the higher order digits. Sign digits of numbers determine which operation must be performed on numbers using the sum operation modulo two. If the signs are the same, then the result will be zero. Otherwise, the result will be one. After that, the addition or subtraction operation is selected. Summation is performed if the numbers have the same signs, the sign of the first number is assigned to the result. Subtraction is performed if the numbers have different signs, the sign is assigned the sign of a larger modulo number.

In FIG. 1 shows a block diagram of an adder-subtractor.

In FIG. 2 shows a variant of the technical implementation of the number input unit.

In FIG. 3 presents a variant of the technical implementation of the comparation unit.

In FIG. 4 shows a functional diagram of a parallel-serial sum

math-subtractor on neurons.

In FIG. 5 shows a functional diagram of a block of registers of a larger number.

In FIG. 6 presents a variant of the technical implementation of the unit for determining the transfer, loan.

In FIG. 7 shows a functional diagram of a block of registers of a smaller number.

In FIG. Figure 8 shows an embodiment of the technical implementation of the result register block.

In FIG. 9 - informative GAW device operation.

In FIG. 10 - labeled GAW device operation.

A parallel-serial adder-subtractor with higher digits forward on neurons contains: a number input block, a comparator block, a parallel-serial adder-subtracter, a block of higher number registers, a transfer and loan determination block, a lower number register block, a result register block, a control block, majority , threshold and neural-like elements (Fig. 1).

To describe the operation algorithm of control unit 8, the following identifiers are used.

1. IF is the first number.

2. HF - the second number.

3. DBCh - data of a larger number.

4. DMCH - data of a smaller number.

5. RV - signal of equality of numbers received from the output of the comparator.

6. BL - the signal is greater, received from the output of the comparator unit.

7. MN - the signal is less received from the output of the comparator unit.

8. ZnR - a significant discharge of the result.

9. CB - the signal of the sum-subtraction.

10. RES - binary bits of the result.

11. UP - information signal control unit registers of the result, which includes signals: zeroing, synchronization, recording permission, storage, issuance.

12. Bn - binary digits of a smaller number coming from a block of registers of a smaller number.

13. An - binary digits of a larger number coming from a block of registers of a larger number.

14. ПЗm – information signal of transfer to high bits or loan from high bits of binary numbers.

15. VBCH - output binary information of a larger number.

16. VMCH - binary output information of a smaller number.

17. SOUP - information signal control the operation of the block of registers of a smaller number.

18. SU - information signal control the operation of the block of registers of a larger number.

19. SDV - a left shift signal of binary information of a register block of a smaller number.

20. SSD - a signal to shift to the left the binary information of the register block of a larger number.

21. ZnRA - a sign discharge of the first number.

22. ZnRV - a significant discharge of the second number.

23. СРС - senior level of the amount.

24. SR - the discharge of the sum or difference.

25. SSB - reset signal triggers block registers of the result.

26. SRZP - a signal to enable the recording of information in the triggers of the result registers.

27. SZPRZ - signal prohibiting the recording of information in the first nine triggers of the block of result registers.

28. SRZ - permission signal recording the sign of the result in the trigger block of the result registers.

29. PPR - a sign of the result.

30. RESET - a reset signal (reset) of all combinational blocks of the adder-subtracter.

31. START - signal the start of the adder-subtractor.

The operation of the device control algorithm.

The contents of the GAW control is shown in Fig.9 and reflects the operation of the control unit (Fig.1).

In blocks 2 and 3 of the algorithm, according to the signals "U00" and "RESET: = 1", all elements of the device memory are set to zero.

In block 4 of the algorithm according to the "START" command, all the units of the device are put into operation (Fig. 1).

In block 5 of the algorithm using the SR encoder, the decimal numbers A10, B10 are entered into the adder-subtractor with their signs ZnA, ZnV (Fig.2).

суммы по модулю два определяется признак операции суммирование или вычитание сигнал СВ. Если сигнал СВ=0, то вычисляется сумма чисел чисел, если СВ=1, то это выполняется операция вычитания чисел (фиг.2).In block 6 of the operation algorithm

sum modulo two is determined by the sign of the operation of the summation or subtraction of the signal SV. If the signal CB = 0, then the sum of the numbers of numbers is calculated, if CB = 1, then this is the operation of subtracting numbers (figure 2).

In block 7 of the algorithm, for the commands: BKO: = IF, BKO: = HF, the first and second binary numbers are fed to the input of the comparation block; for the commands: BKO: = CB, BOPZ: = CB, the input of the comparation and transfer and loan determination blocks is fed the sign of operation is the signal CB (Fig. 3, 6).

In block 8 of the algorithm, the following commands: BRGBCH: = DBCH, BRgMCH: = DMCH downloads to the block registers a larger number of BRGBM and a smaller number of BRGMCH data of more DBCh and less DMCh binary numbers (Figs. 1, 5, 7).

In block 9 of the algorithm according to the commands: BOPZ: = VBCH, BOZ: = VMCh, the greater the number of VBCh and the smaller VMCh numbers are supplied to the unit for determining the transfer and reception of binary information (Fig. 6).

In block 10 of the algorithm for the commands: BPSV: = An, BPSV: = Bn, BPSV: = ПЗm to the input of the parallel-sequential adder-subtractor block BPSV, the next eight bits of larger An and lower Bn numbers are fed, as well as transfer of the loan ПЗm for addition operands (figure 4).

In block 11 of the algorithm, the sign of operation signal SV is analyzed - summation or subtraction (figure 2). If the CB attribute is equal to zero, then this means that the input numbers have the same signs. In this case, the addition operation between the numbers will be performed. When this is a transition to block 16 of the algorithm. If the CB attribute is equal to one, then the signs of the numbers are different, in this case, the operation of subtracting the smaller from the larger module will be performed. When this is a transition to block 12 of the algorithm.

In block 12 of the algorithm, the output from the comparator to the equality of the input numbers of the RV signal is analyzed. If the numbers are not equal, then the sign of equality of PB takes the value of one, in this case, the transition to block 18 of the algorithm. If the numbers are equal, then the sign of the equality of PB takes the value zero, in this case, the transition to block 13 of the algorithm.

In block 13 of the algorithm, the output signal of the comparator KOM is analyzed for a ratio greater or less; in this case, the numbers are not equal. If the first number of IFs is greater than the second number of HFs, then the signal greater than BL is equal to one - the output is YES. In this case, the transition to block 14 of the algorithm. If the first IF number is less than the second RF number, then the signal greater than the BL is equal to zero, in this case the signal is less than MH equal to one - the output is NO. In this case, the transition to the block 15 of the algorithm (figure 3).

 In block 14 of the algorithm at the command BRGBH: = IF, a larger number is loaded into the register block of a larger number (Fig. 5). At the command BRGMCH: = HF number smaller modulo is loaded into the block of registers of a smaller number (Fig.7).

 In block 15 of the algorithm by the command BRGBH: = HF, a larger modulo number is loaded into the larger block register block (Fig. 5). At the command BRGMCH: = IF the number of the smaller modulo is loaded into the block of registers of the smaller number (Fig.7).

In block 16 of the algorithm, according to the command REZ 8p: = A 8p + B 8p + PZ 7p, the next eight bits of input numbers and seven bits of transfer and borrow are summed in the block of parallel-sequential adder-subtractor (Fig. 4).

In block 17 of the algorithm at the command BRgR: = RES 8p, the next eight bits of the result are recorded in the block of result registers (Fig. 8).

In block 18 of the algorithm, by the command BrgR: = 0, a zero value is written to the block of result registers (Fig. 8).

In block 19 of the algorithm, the sign of obtaining bits of the SPR result is analyzed. If all digits of the sum or difference are received - the output is YES, then the transition to the 21 block of the algorithm is performed. If not all digits are obtained with the output - NO, then the transition to the 20th block of the algorithm is performed, in this case a cycle is formed to obtain the next digits of the result.

Blocks 16, 17, 19, 20 of the algorithm form a cycle to obtain all bits of the result.

In block 20 of the algorithm according to the commands: BRGBCH: = SSD, BRgMCH: = SDV from the control unit, left-shift signals of SSD and SDV are sent to the inputs of the register of blocks of larger and smaller numbers. The feed is carried out to shift the binary information in the registers by eight bits to the left to obtain the next eight bits of the result (Figs. 1, 5, 7).

In block 21 of the algorithm, by the command BrgR: = REZ, the final RES result is recorded in the block of result registers. At the command Trzn: = ZnR, the sign of the digit of the result ZnRv is recorded, the binary trigger Trzn of the block of result registers (Fig. 8).

Block 22 of the algorithm is the final block of the algorithm.

The operation of a parallel-sequential adder-subtractor with the highest discharges forward on neurons is as follows.

The external control signals "Start" and "Reset" are sent to the control unit 8. From the output of the encoder, the binary numbers of the IF and HF are sent to the registers of a larger number and a smaller number. On the adder modulo two is determined by the sign of the implementation of the option of summing or subtracting the signal SV. If the numbers have the same signs, then the sum of the numbers is calculated, the sign of any of the terms is assigned to the result. If the signs of the numbers are different, then a subtraction operation is performed. From a larger modulo number, a smaller one is subtracted. The sign of the result in this case is assigned the sign of a larger modulo number. The proposed arithmetic device performs the operations of summing and subtracting the leading digits in front of eight bits of binary numbers in parallel. The transfer to the higher digits during the summation is determined. A loan is calculated from the higher ranks to the lower ones when subtracting.

Block 1 input numbers contains the encoder WF DD9, the adder modulo two DD10 (figure 2). This block allows you to enter binary numbers. From the output of the encoder, binary codes of numbers are formed with their own characters: IF, HF, ZnRA, ZnRV. Signed bits of numbers from the output of the encoder go to the input of the adder modulo two. The summation-subtraction signal CB is generated at the output of the element DD10. The adder modulo two is implemented on a neural element. The output signal is calculated by the formula:

(1)

(one)

If the signal CB is equal to one, then the subtraction operation is performed. If the signal CB is equal to zero, then the addition operation is performed. The output signals of the block 1 input numbers are binary codes of the operands presented in direct codes and a sign of operation CB (figure 2).

Block 2 comparator contains a comparator KOM DD11, a circuit of electronic keys DD12, a circuit of electronic keys with an inverse input DD13, a circuit of electronic keys with an inverse input DD14, a circuit of electronic keys DD15, logic gates OR DD16 and DD17 (Fig. 3). This block is designed to determine a larger number modulo if the numbers have different signs. Modules of n-bit binary numbers are received at the input of the KOM comparator. A signal of the operation of summation-subtraction of the CB signal is received. If the input of the adder-subtracter receives numbers with the same signs, then the comparison of numbers modulo does not occur, the comparator is blocked by the signal SV. In this case, modulo addition of numbers is performed. If numbers with different signs arrive at the input of the adder-subtractor, then a larger operand is written in the register block of a larger number. The sign of the sum-subtract operation is the signal CB in this case is unity, the comparator compares the numbers. In the block of registers of a smaller number, a smaller number is loaded modulo. The operation subtracts from the larger the modulus of the number of the smaller. Comparator KOM DD11 is a circuit for comparing numbers on neural-like elements. There are three outputs at the output of the comparator: BL — the first number of the IFs of the second high frequency, RV — the numbers of IFs and RFs are equal in absolute value, MN — the first number of IFs is less than the second RF. Logic circuits AND DD12, DD13, DD14, DD15 are made on neural-like elements. The conjunction scheme is described using the formula [w1 = 1, w2 = 1, .., wn = 1; T = n-1], where w1, w2, .., wn are the gain and T are the threshold voltage, n is number of inputs. The disjunction scheme is described using the formula [w1 = 1, w2 = 1, .., wn = 1; T = 0], where w1, w2, .., wn are the amplification factors, and T is the threshold voltage equal to zero, n is the number inputs. The inverter is described by the formula [w = -1; T = -1]. The inputs of the logic circuits And DD12 and DD15 receives the first binary number of the inverter with its sign. The inputs of the logic circuits And DD13 and DD14 receives the second binary number of the RF with its sign. The outputs of the logic circuits AND DD12 and DD13 are fed to the input of the logic circuit OR DD16. The outputs of the logic circuits AND DD14 and DD15 go to the input of the logic circuit OR DD17. The output of the logic circuit OR DD16 of a binary larger number of DBCs is input to the register block of a larger number (Fig. 1). The output of the logic circuit OR DD17 of a binary lower number of DMCs is supplied to the input of a block of registers of a lower number (Fig. 1). Binary numbers arrive at the input of the comparator, the output of the operands is formed at the output of the circuit. If at the output a larger number of BLs is one, then this means that the first IF number is greater than the second RF number modulo. The remaining outputs of the comparator will be equal to zero. A single output of the BL will open the circuit AND DD12 through which the first number of inverters will receive the input of the circuit OR DD16. Logical circuit AND DD13 will be locked since controlled by inverse signal. From the output of the OR OR DD16 circuit, the information signal will go to the block of registers of a larger number. The logic circuit AND DD14 will be opened, through it a second module with a lower modulus of RF will be fed to the input of the OR circuit DD17, from the output of this circuit, an information signal will be fed to the input of the register block of a smaller number. If the output signal is less than MN, it will be equal to a single value, which means the second number of RF is larger in magnitude than the first number of IF. In this case, the logic circuits DD13 and DD15 will be open and through their information signals will go to the inputs of the circuits OR DD16 and DD17, respectively. Through the DD13 circuit, a second RF number of greater magnitude will be fed to the input of the OR circuit DD16, then it will be written to the register block of a larger number. Through the DD15 circuit, the first number of the inverter with a smaller modulus will go to the input of the OR circuit DD17, then it will be written to the register block of the smaller number. If the input numbers are equal in absolute value and have equal signs, then the signal equal to RV will be equal to one, and signals greater than BL and less MN will be equal to zero. Logic circuits And DD12 and DD15 will be locked, and DD13 and DD14 will be open. The logic OR OR DD16 and DD17 will receive the second number of RF. In this case, the addition of two second numbers of treble. The sign of the result ZnR will always be formed from the output of the logic OR OR DD16, because the output will be a larger modulus number (figure 3).

Block 3 parallel-serial adder-subtractor contains schema adders modulo two, made on neural elements DD18 - DD21, DD23 - DD26, threshold element DD22. A transfer is formed on the threshold element DD22 when adding the most significant bits of numbers. Addition and subtraction of binary numbers is performed in eight digits. The result of operations is a nine-bit sum or an eight-bit difference, which is input to the block of result registers for recording and storage. The full single-bit adder is designed to add three single-bit binary numbers according to the formula

(2)

(2)

- сумма чисел, Ai,Bi - двоичные разряды и перенос Pi-1из младшего разряда в старший.Where

- the sum of numbers, Ai, Bi - binary digits and transfer of Pi-1 from the least significant to the highest.

A full one-bit subtractor calculates the difference by the formula

(3)

(3)

where R _{i is the} difference, Ai- is reduced, Bi- is deductible, Z _{i + 1} is the loan coming from the neighboring lower level.

и разности

двоичных чисел одинаковые, вычисляются по формулеAmount Formulas

and differences

binary numbers are the same, calculated by the formula

(4)

(4)

where Ai, Bi - binary digits, PZ - transfer / loan.

The neural elements DD18 and DD23 calculate the sum and difference of the high order bits of binary numbers. The high-order bits of the binary numbers A1 and B1 are input to the neural-like element DD18. The input of the neural-like element DD23 receives the sum of these numbers and transfer / loan ПЗ2 from the block for determining transfer, loan. At the output of the neural-like element DD23, the sum and difference CP1 of the most significant bits of binary numbers are calculated. On the threshold element DD22, the CPC transfer from the upper bits of the sum is calculated. The neural elements DD19 and DD24 calculate the sum and difference CP2 of the lower-order bits of the binary numbers. At the input of the neural-like element DD19, the lower bits of the binary numbers A2 and B2 are received. The input of the neural-like element DD24 receives the sum of these numbers and transfer / loan ПЗ3 from the block for determining transfer, loan. At the output of the neural-like element DD24, the sum and difference CP2 of the lower-order bits of binary numbers are calculated. The neural-like elements DD20 and DD25 calculate the sum and difference CP3 of the next lower-order bits of binary numbers. The lower-order bits of the binary numbers A3 and B3 enter the input of the neural-like element DD20. The input of the neural-like element DD25 receives the sum of these numbers and transfer / loan ПЗ4 from the block for determining transfer, loan. At the output of the neural-like element DD25, the sum and difference CP3 of the lower-order bits of binary numbers are calculated. The neural-like elements DD21 and DD26 calculate the sum and difference of the CP8 low-order bits of binary numbers. The low-order bits of the byte of binary numbers A8 and B8 are fed to the input of the neural-like element DD21. The input of the neural-like element DD26 receives the sum of these numbers and transfer / loan ПЗ9 from the block for determining transfer, loan. At the output of the neural-like element DD26, the sum and difference CP8 of the least significant bits of the byte of binary numbers are calculated. Block 3, a parallel-serial adder-subtractor, calculates the sum and difference of eight bit binary code (Fig. 4).

Block 4 registers of a larger number contains n – two-input OR logic circuits executed on threshold elements DD27 - DD29, n – binary triggers Trn executed on elements DD30 - DD33, where n is the number of bits of the input number (Fig. 5). Block 4 registers of a larger number is designed to store the binary code of a larger modulo operand. Before the start of the adder-subtractor upon arrival of the information signal SU from block 8, all the triggers of the block are reset. Upon arrival from block 2 of the comparator of the information signal of a larger number of DBC, the binary code of one of the numbers is loaded. The first inputs of the logic circuits OR DD27 –DD29 receive binary bits of a larger number. The second inputs of the logic circuits OR receive information from the outputs of the triggers Tr 9 - Trn of the second byte of numbers. The outputs of the logic circuits OR are the inputs of the triggers Tr1 - Trn (figure 5). When a control signal arrives more than BL at the inputs of Tr1 – Trn triggers, the received binary code is recorded and stored in the block triggers. A signal larger than the BL is an input control signal for all the memory elements of the block. Upon the arrival of the control signal for the shift of the SDS from the control unit 8, received at the inputs of all the triggers of the block, the operation of shifting information to the left by eight digits is performed. The binary code of the number recorded in the block triggers will be shifted eight bits to the left. The input of the first trigger Tr1 DD30 receives a binary digit from the output of the ninth trigger Tr9 block. Binary triggers of this block form a reversible register with a shift of information by eight digits to the left (figure 5).

Block 5 of determining the transfer of seizure contains s - adders modulo two DD34 -DD36, performed on neural-like elements, s - majority elements DD37 – DD39, defining the transfer to the senior digits during the summation and borrowing from the senior digits when subtracting (Fig.6). At the first inputs of the adders modulo two, the binary digits of the number from the block of registers of a larger number arrive. The second inputs of all adders of the block receive a sign of the operation of summing-subtracting the signal SV. If the CB signal is equal to zero, then the addition operation is performed, while the adders perform the role of repeaters. Input binary digits arrive at the first inputs of the corresponding majority elements of the block. If the signal CB is equal to one, then all input binary codes are fed to the inputs of the majority elements in the reverse code, the subtraction operation is performed. In this case, the modulo two adders perform the function of inverters. The binary inputs from the outputs of the previous majority elements arrive at the second inputs of the majority elements. This block uses three-input majority elements. A unit at the output of a majority element is formed when there will be a majority of units at the input, in this case two or three. The third inputs of the majority elements receive binary bits from a block of registers of a smaller number. The output signal of the PZ of the majority element will be equal to one in the case when there is a transfer from the lower digits to the higher digits when adding numbers and when a borrowing occurs in the lower digits from the older ones when performing the operation of subtracting from the larger modulus of the smaller number (Fig. 6).

Block 6 of the lower number registers contains n - triggers Trn, executed on the elements DD40 - DD43, where n is the number of bits of the number, n - OR logic circuits, performed on the threshold elements DD44 - DD46 (Fig.7). This block is designed to store a binary code of a smaller modulus number. Before the start of the adder-subtractor, upon arrival from the block 8 of the information signal of the control system, all the triggers of the block are reset. Upon arrival from block 2 of the comparation of the information signal, the data of a smaller number of DMC is loaded binary code number in the triggers of the block. The first inputs of the logic circuits OR DD44 –DD46 receive binary bits of a smaller number. The second inputs of the logic circuits receive information from the outputs of the triggers Tr9 - Trn of the second byte of numbers. The output from the OR logic circuits is the input for block triggers. When the control signal arrives less than MH at the inputs of the Tr1-Trn triggers, the binary code received from the outputs of the OR circuits of the block is loaded and stored. The control signal MH is the input control signal for all the memory elements of the block. Upon the arrival of the control signal for the shift of the ADD from the control unit 8, the operation of shifting to the left by eight bits is performed. The binary code of the number recorded in the triggers will be shifted eight bits to the left. The input of the first trigger Tr1 DD40 will receive a binary digit from the output of the ninth trigger Tr9 block. Binary triggers of this block form a reversible register with a shift of information by eight digits to the left (Fig.7).

Block 7 of the result registers contains m triggers Тm made on elements DD47 - DD49, where m is the number of bits necessary to obtain a result of a given accuracy (Fig. 8). The trigger Trzn block, made on the element DD50 is designed to store a significant bit of the result, the recording is made upon arrival from the control unit 8 of the control signal write permission SRZ trigger. In the result register block, the difference of numbers is recorded in eight bits CP1 - CP8, the sum is the first nine STRsSm, CP1 - CP8, taking into account the possible transfer from the upper bits of numbers, then eight. The input information signal of the block is the control signal UE coming from the control unit 8. Before starting the adder-subtractor by the reset signal of the PRS, all the triggers of the block are reset. According to the signal recording permission SRZP triggers block receive input information for recording and storage. The first trigger T1 records the transfer from the upper digits of the sum of the numbers of CPC during the operation of summation. The write disable control signal SZPRZ blocks the operation of the first nine triggers T1 - T9 after receiving the first byte of the result. The next bytes of the result are written in parallel to the binary triggers of the block (Fig. 8).

Marked GAW operation of the device is shown in figure 10 where is indicated:

Logical conditions:

X1: "UOO"    X4: RV

  X2: "START"     X5: "BL"

X3: "SV" X6: "PPR"

Operators:

U1: "RESET: = 1" U15: "BPSV: = An"

U2: ZNA                                   U16: "BPSV: = Bn" U3: "A10"                                   U17: "BPSV: = PZm"

U4: ZnV                                        U18: "BRGBH: = IF"          U5: "B10"                                        U19: "BRgMCH: = HF"

         Y6: "NE: = ZnR A ⊕ ZnR IN U20:" BRGBCH: = HF "

 U7: "BKO: = IF"                             U21: "BRgMCH: = IF"

 Y8: "BKO: = HF"                         U22: "REZ 8p: = A 8p + B 8p + PZ 7p"  Y9: "BKO: = CB"                         U23: "BRgR: = REZ 8r"

 U10: "BOPZ: = NE"                          U24: "Brgr: = 0"

 U11: "BRGBH: = DBCh"                U25: "BRGBH: = SSD"  U12: "BRgMCH: = DMCh"                U26: "BRgMCH: = ADD"

 U13: "BOPZ: = VBCh" U27: "BRGR: = REZ"

 U14: "BOPZ: = VMCh" U28: "TrZn: = ZnR"

Claims (1)

A parallel-serial adder-subtracter with higher digits forward on neurons, containing a number input unit, a comparation unit, a larger number register block, a transfer and loan determination unit, a lower number register block, a result register block, a control unit, characterized in that the block is additionally introduced parallel-serial adder-subtracter, and the first and second information outputs of the number input unit are connected respectively to the first and second information inputs of the comparation unit, the fourth control the output of which is connected to the third control input of the control unit, the first information output of which is connected to the second information input of the result register block, the control input of which is connected to the third control output of the comparator block, the second information output of which is connected to the first information input of the lower number register, the first the control input of which is connected to the second control output of the comparation unit, the first information output of which is connected to the first information m input of a larger number of registers, the first control input of which is connected to the first control output of the comparation block, the control input of which is connected to the control output of the number input unit and with the control input of the transfer and loan determination unit, the first information input of which is connected to the second information output of the register block a larger number, the second information input of which is connected to the third information output of the control unit, the second control output of which is connected to the second control an ode to the register block of a larger number, the first information output of which is connected to the first information input of the parallel-sequential adder-subtracter block, the second information input of which is connected to the information output of the transfer and loan determination unit, the second information input of which is connected to the second information output of the lower number register the second information input of which is connected to the second information output of the control unit, the first control output of which is connected to the second control input of the register block of a smaller number, the first information output of which is connected to the third information input of the parallel-sequential adder-subtracter block, the information output of which is connected to the first information input of the result register block, the first and second control inputs are “RESET” and “START” of the block the controls are the external inputs of the parallel-serial adder-subtracter higher bits forward on the neurons.

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